jaseg
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f037001053
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Add local changes
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2020-04-11 17:33:20 +02:00 |
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jaseg
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bc136ef5b1
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Small firmware foo
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2018-04-20 14:04:16 +02:00 |
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jaseg
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6d5c101e2f
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Add global README
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2018-01-05 12:32:21 +01:00 |
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jaseg
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c2e293d976
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Split project into individual source files and add license
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2018-01-05 12:23:24 +01:00 |
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jaseg
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e3094b18d4
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Firmware directory reorganization
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2018-01-05 11:53:52 +01:00 |
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jaseg
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31fc78d0e0
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Add some documentation
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2018-01-05 11:39:20 +01:00 |
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jaseg
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a70ad99b36
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Make status request work, fix uc-side cobs encoding bug
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2017-12-10 20:17:51 +01:00 |
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jaseg
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75d4d0f3df
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Prettified the python side of things a bit
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2017-12-10 16:12:30 +01:00 |
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jaseg
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582e6d7786
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Add discovery and addressing mechanism
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2017-12-10 15:59:56 +01:00 |
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jaseg
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b315bc1e96
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Prettify and document AUX LED handling
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2017-12-10 13:50:54 +01:00 |
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jaseg
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bf2c701353
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Make comm and error LEDs useful
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2017-12-10 13:41:24 +01:00 |
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jaseg
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3ec035844f
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ADC temperature measurement works now
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2017-12-10 13:28:23 +01:00 |
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jaseg
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322b306bf2
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ADC properly triggering now
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2017-12-10 13:11:30 +01:00 |
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jaseg
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49c4d3ab8e
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Rough ADC triggering works now
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2017-12-10 12:28:51 +01:00 |
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jaseg
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0dab3f4007
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Add lots of doc and fix segment driving
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2017-12-10 01:07:53 +01:00 |
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jaseg
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43785b2307
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Framing works now
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2017-12-09 20:52:18 +01:00 |
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jaseg
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a542e6f291
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Framing experiments
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2017-12-09 20:08:20 +01:00 |
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jaseg
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84fd070709
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UART and LEDs playing nicely
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2017-12-09 19:01:53 +01:00 |
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jaseg
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58796333b9
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Made all ISRs *fast* (<2.5us)
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2017-12-09 15:11:41 +01:00 |
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jaseg
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6b7518b29f
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Aux register loading further optimized
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2017-12-09 15:06:51 +01:00 |
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jaseg
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d2194c5ae2
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Fixed aux cycle
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2017-12-09 14:41:58 +01:00 |
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jaseg
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1c58250425
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Cycle timing is fixed again
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2017-12-09 12:08:32 +01:00 |
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jaseg
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a1eff91d77
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Basic UART working, but too slow
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2017-12-08 19:25:11 +01:00 |
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jaseg
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723995c541
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hw v0.4
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2017-09-18 11:30:25 +02:00 |
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jaseg
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a823484163
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Fix up RS485/digital power label
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2017-09-06 14:36:50 +02:00 |
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jaseg
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d4d0f850f0
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Fix up version label and one ground trace
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2017-09-06 14:30:43 +02:00 |
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jaseg
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febcb5a933
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Fixes for second prototype (v0.3)
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2017-09-06 14:03:07 +02:00 |
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jaseg
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9b52622eab
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Temperature/VCC ADC working
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2017-09-02 12:23:39 +02:00 |
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jaseg
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446dbe6412
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Now with working source extraction from firmware
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2017-09-01 20:52:34 +02:00 |
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jaseg
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5a19ab0e84
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Add missing files
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2017-09-01 20:32:15 +02:00 |
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jaseg
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e6437f975b
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UART magic seems to be working now
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2017-09-01 20:26:05 +02:00 |
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jaseg
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6b40626a1b
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DMA channel assignments redone, basic protocol stuff working
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2017-09-01 15:44:39 +02:00 |
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jaseg
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a832816d61
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Serial protocol now working including CRC
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2017-08-24 00:52:18 +02:00 |
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jaseg
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570f527a3a
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Interrupt-driven SPI1 fundamentally working
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2017-08-23 14:11:45 +02:00 |
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jaseg
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dbb03cbece
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Comms working except for TIM3/SPI1 race
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2017-08-23 13:00:07 +02:00 |
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jaseg
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abdf02426f
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Add cmsis export generator
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2017-08-23 10:50:43 +02:00 |
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jaseg
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95e1a03648
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Add transpose test
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2017-08-23 10:50:16 +02:00 |
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jaseg
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e9f79a2e99
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Add profiling script
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2017-08-22 20:13:10 +02:00 |
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jaseg
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a18b197ac4
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Benchmark code
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2017-08-15 15:57:33 +02:00 |
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jaseg
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9eb92caa6c
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working commit
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2017-08-15 14:34:34 +02:00 |
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jaseg
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952f3c03ac
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Temporary for bit shuffling
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2017-08-15 10:34:57 +02:00 |
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jaseg
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71ad806c88
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Working on uart code
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2017-08-15 10:30:35 +02:00 |
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jaseg
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369c090955
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Multiplexing is working
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2017-08-14 12:51:49 +02:00 |
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jaseg
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7a5791e976
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Board rev 0.3 working
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2017-08-13 15:48:48 +02:00 |
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jaseg
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1ae37bce5b
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Second production run, v0.3
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2017-07-21 20:01:20 +02:00 |
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jaseg
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5bb67efb4a
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Final silk art positioning
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2017-07-21 01:00:43 +02:00 |
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jaseg
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2775e1fc61
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Add missing firmware build files
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2017-07-20 16:06:33 +02:00 |
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jaseg
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16328e9723
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Second board revision
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2017-07-20 16:05:07 +02:00 |
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jaseg
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6ec97df9de
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Schematic fixed up so far
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2017-07-15 22:43:04 +02:00 |
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jaseg
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6f12a41cc6
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Add resistor calculation script
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2017-06-12 13:03:18 +02:00 |
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