Working on uart code
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jaseg
parent
369c090955
commit
71ad806c88
2 changed files with 147 additions and 35 deletions
1
fw/.gitignore
vendored
1
fw/.gitignore
vendored
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@ -6,3 +6,4 @@
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*.expand
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*.bin
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*.hex
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*.pp
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181
fw/main.c
181
fw/main.c
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@ -54,13 +54,15 @@ enum {
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struct framebuf {
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/* Multiplexing order: first Digits, then Time/bits, last Segments */
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uint32_t data[nbits*frame_size_words];
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int brightness; /* 0 or 1; controls global brighntess control */
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uint8_t brightness; /* 0 or 1; controls global brighntess control */
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};
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struct framebuf fb[2] = {0};
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struct framebuf *read_fb=fb+0, *write_fb=fb+1;
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volatile struct framebuf fb[2] = {0};
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volatile struct framebuf *read_fb=fb+0, *write_fb=fb+1;
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volatile int led_state = 0;
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volatile enum { FB_WRITE, FB_UPDATE } fb_op;
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volatile enum { FB_WRITE, FB_FORMAT, FB_UPDATE } fb_op;
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volatile uint8_t rx_buf[sizeof(struct framebuf)];
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volatile uint8_t this_addr = 0x05; /* FIXME */
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#define LED_COMM 0x0001
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#define LED_ERROR 0x0002
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@ -68,6 +70,34 @@ volatile enum { FB_WRITE, FB_UPDATE } fb_op;
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#define SR_ILED_HIGH 0x0080
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#define SR_ILED_LOW 0x0040
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void transpose_data(volatile uint8_t *rx_buf, volatile struct framebuf *out_fb) {
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memset((uint8_t *)out_fb, 0, sizeof(*out_fb));
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struct data_format {
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union {
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uint8_t high[8];
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struct { uint8_t ah, bh, ch, dh, eh, fh, gh, dph; };
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};
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union {
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uint16_t low;
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struct { uint8_t al:2, bl:2, cl:2, dl:2, el:2, fl:2, gl:2, dpl:2; };
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};
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};
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struct data_format *rxp = (struct data_format *)rx_buf;
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for (unsigned int digit=0; digit<nrows*ncols; digit++, rxp++) {
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for (int segment=0; segment<8; segment++) {
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uint32_t *outp = out_fb->data;
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for (int bit=0x80; bit; bit>>=1, outp+=frame_size_words)
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outp[segment] |= !!(rxp->high[segment] & bit) << digit;
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}
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uint16_t low = rxp->low;
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for (int segment=0; segment<8; segment++) {
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uint32_t *outp = out_fb->data;
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for (int bit=0x8000; bit; bit>>=1, outp+=frame_size_words)
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outp[segment] |= !!(rxp->high[segment] & bit) << digit;
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}
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}
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}
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void shift_aux(int global_current, int leds, int active_segment) {
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spi_send(
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(global_current ? SR_ILED_HIGH : SR_ILED_LOW)
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@ -96,7 +126,7 @@ int shift_data() {
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frame_duration = time - last_frame_sys_time;
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last_frame_sys_time = sys_time;
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if (fb_op == FB_UPDATE) {
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struct framebuf *tmp = read_fb;
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volatile struct framebuf *tmp = read_fb;
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read_fb = write_fb;
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write_fb = tmp;
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fb_op = FB_WRITE;
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@ -129,14 +159,10 @@ void cfg_timer3() {
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TIM_TypeDef *tim3 = TIM3;
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void TIM3_IRQHandler() {
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//TIM3->CR1 &= ~TIM_CR1_CEN_Msk;
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//TIM3->CR1 &= ~TIM_CR1_CEN_Msk; FIXME
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static int last_ivl;
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last_ivl = TIM3->CNT;
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/* This takes about 10us */
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int period = shift_data();
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static int ivl;
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ivl = TIM3->CNT - last_ivl;
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TIM3->CCR1 = period;
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TIM3->CNT = 0xffff; /* To not enable OC1 right away */
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@ -144,6 +170,47 @@ void TIM3_IRQHandler() {
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//TIM3->CR1 |= TIM_CR1_CEN;
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}
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enum Command {
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CMD_PING,
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CMD_SET_ADDR,
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CMD_SET_FB,
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CMD_GET_DESC,
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};
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void USART1_IRQHandler() {
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int addr = USART1->RDR;
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int cmd = addr>>5;
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addr &= 0x1F;
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/* Are we addressed? */
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if (addr != this_addr) {
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/* We are not. Mute USART until next idle condition */
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USART1->RQR |= USART_RQR_MMRQ;
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} else {
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/* We are. Switch by command. */
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switch (cmd) {
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case CMD_SET_FB:
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/* Are we ready to process new frame data? */
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if (fb_op != FB_WRITE)
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goto errout; /* Error: Not yet ready to receive new packet */
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/* Disable this RX interrupt for duration of DMA transfer */
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USART1->CR1 &= ~USART_CR1_RXNEIE_Msk;
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/* Enable DMA transfer to write buffer */
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DMA1_Channel3->CCR |= DMA_CCR_EN;
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/* Kick off formatting code in main loop outside interrupt context */
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fb_op = FB_FORMAT;
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break;
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}
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}
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errout:
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/* FIXME */
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return;
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}
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void DMA1_Channel2_3_IRQHandler() {
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/* DMA Transfer complete, re-enable receive interrupt */
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USART1->CR1 |= USART_CR1_RXNEIE;
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}
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int main(void) {
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR&RCC_CR_HSERDY));
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@ -158,12 +225,15 @@ int main(void) {
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LL_Init1msTick(SystemCoreClock);
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_DMAEN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN | RCC_APB2ENR_USART1EN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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GPIOA->MODER |=
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(2<<GPIO_MODER_MODER5_Pos) /* PA5 - SCLK */
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(2<<GPIO_MODER_MODER1_Pos) /* PA1 - RS485 DE */
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| (2<<GPIO_MODER_MODER2_Pos) /* PA2 - RS485 TX */
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| (2<<GPIO_MODER_MODER3_Pos) /* PA3 - RS485 RX */
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| (2<<GPIO_MODER_MODER5_Pos) /* PA5 - SCLK */
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| (2<<GPIO_MODER_MODER6_Pos) /* PA6 - LED !OE */
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| (2<<GPIO_MODER_MODER7_Pos) /* PA7 - MOSI */
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| (1<<GPIO_MODER_MODER9_Pos) /* PA9 - LED strobe */
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@ -171,25 +241,78 @@ int main(void) {
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/* Set shift register IO GPIO output speed */
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GPIOA->OSPEEDR |=
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(2<<GPIO_OSPEEDR_OSPEEDR5_Pos) /* SCLK FIXME maybe try 0x2 here? */
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(2<<GPIO_OSPEEDR_OSPEEDR1_Pos) /* RS485 DE */
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| (2<<GPIO_OSPEEDR_OSPEEDR2_Pos) /* TX */
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| (2<<GPIO_OSPEEDR_OSPEEDR3_Pos) /* RX */
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| (2<<GPIO_OSPEEDR_OSPEEDR5_Pos) /* SCLK */
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| (2<<GPIO_OSPEEDR_OSPEEDR6_Pos) /* LED !OE */
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| (2<<GPIO_OSPEEDR_OSPEEDR7_Pos) /* MOSI */
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| (2<<GPIO_OSPEEDR_OSPEEDR9_Pos) /* LED strobe */
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| (2<<GPIO_OSPEEDR_OSPEEDR10_Pos); /* Auxiliary strobe */
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GPIOA->AFR[0] |=
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(0<<GPIO_AFRL_AFRL5_Pos) /* SPI1_SCK */
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| (1<<GPIO_AFRL_AFRL6_Pos) /* TIM3_CH1 */
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(1<<GPIO_AFRL_AFRL1_Pos) /* USART1_RTS (DE) */
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| (1<<GPIO_AFRL_AFRL2_Pos) /* USART1_TX */
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| (1<<GPIO_AFRL_AFRL3_Pos) /* USART1_RX */
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| (0<<GPIO_AFRL_AFRL5_Pos) /* SPI1_SCK */
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| (1<<GPIO_AFRL_AFRL6_Pos) /* TIM3_CH1 */
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| (0<<GPIO_AFRL_AFRL7_Pos); /* SPI1_MOSI */
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GPIOA->PUPDR |=
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(2<<GPIO_PUPDR_PUPDR1_Pos) /* RS485 DE: Pulldown */
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| (1<<GPIO_PUPDR_PUPDR2_Pos) /* TX */
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| (1<<GPIO_PUPDR_PUPDR3_Pos); /* RX */
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/* Configure SPI controller */
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SPI1->I2SCFGR = 0;
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SPI1->CR2 &= ~SPI_CR2_DS_Msk;
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SPI1->CR2 &= ~SPI_CR2_DS_Msk;
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SPI1->CR2 |= LL_SPI_DATAWIDTH_16BIT;
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/* FIXME maybe try w/o BIDI */
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/* Configure USART1 */
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USART1->CR1 = /* 8-bit -> M1, M0 clear */
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/* RTOIE clear */
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(8 << USART_CR1_DEAT_Pos) /* 8 sample cycles/1 bit DE assertion time */
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| (8 << USART_CR1_DEDT_Pos) /* 8 sample cycles/1 bit DE assertion time */
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| USART_CR1_OVER8
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/* CMIF clear */
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| USART_CR1_MME
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/* WAKE clear */
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/* PCE, PS clear */
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| USART_CR1_RXNEIE
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/* other interrupts clear */
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| USART_CR1_TE
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| USART_CR1_RE;
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//USART1->CR2 = USART_CR2_RTOEN; /* Timeout enable */
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USART1->CR3 = USART_CR3_DEM; /* RS485 DE enable (output on RTS) */
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int usartdiv = 25;
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USART1->BRR = (usartdiv&0xFFF0) | ((usartdiv>>1) & 0x7);
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USART1->CR1 |= USART_CR1_UE;
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/* Configure DMA for USART frame data reception */
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USART1->CR3 |= USART_CR3_DMAR;
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DMA1_Channel3->CPAR = (unsigned int)&USART1->RDR;
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DMA1_Channel3->CMAR = (unsigned int)rx_buf;
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DMA1_Channel3->CNDTR = sizeof(rx_buf);
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DMA1_Channel3->CCR = (0<<DMA_CCR_PL_Pos);
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DMA1_Channel3->CCR |=
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(0<<DMA_CCR_MSIZE_Pos)
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| (0<<DMA_CCR_PSIZE_Pos)
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| DMA_CCR_MINC
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| DMA_CCR_TCIE;
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/* Baud rate PCLK/2 -> 25MHz */
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SPI1->CR1 = SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (0<<SPI_CR1_BR_Pos) | SPI_CR1_MSTR | SPI_CR1_CPOL | SPI_CR1_CPHA;
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SPI1->CR1 =
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SPI_CR1_BIDIMODE
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| SPI_CR1_BIDIOE
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| SPI_CR1_SSM
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| SPI_CR1_SSI
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| SPI_CR1_SPE
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| (0<<SPI_CR1_BR_Pos)
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| SPI_CR1_MSTR
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| SPI_CR1_CPOL
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| SPI_CR1_CPHA;
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/* FIXME maybe try w/o BIDI */
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read_fb->brightness = 1;
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for (int i=0; i<sizeof(read_fb->data)/sizeof(uint32_t); i++) {
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@ -205,24 +328,12 @@ int main(void) {
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while (42) {
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led_state = (sys_time>>8)&7;
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int ctr = sys_time>>2;
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for (int bit=0, bmask=1; bit<nbits; bit++, bmask<<=1) {
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int data = 0;
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for (uint32_t ibit = 1, j=0; ibit; ibit<<=1, j++) {
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int _100 = (1<<nbits);
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int _1ff = (2*_100-1);
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int val = (ctr + (j<<(nbits-5))) & _1ff;
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val = val&_100 ? _1ff-val : val;
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data |= val&bmask ? ibit : 0;
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}
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for (int seg=0; seg<frame_size_words; seg++)
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write_fb->data[bit*frame_size_words + seg] = data;
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if (fb_op == FB_FORMAT) {
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transpose_data(rx_buf, read_fb);
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fb_op = FB_UPDATE;
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while (fb_op == FB_UPDATE)
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;
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}
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fb_op = FB_UPDATE;
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while (fb_op == FB_UPDATE)
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;
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}
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}
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