Cycle timing is fixed again
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jaseg
parent
a1eff91d77
commit
1c58250425
1 changed files with 76 additions and 54 deletions
130
fw/main.c
130
fw/main.c
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@ -99,7 +99,7 @@ volatile unsigned int sys_time_seconds = 0;
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volatile struct framebuf fb[2] = {0};
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volatile struct framebuf *read_fb=fb+0, *write_fb=fb+1;
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volatile int led_state = 0;
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volatile enum { FB_WRITE, FB_UPDATE } fb_op = FB_WRITE;
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volatile enum { FB_WRITE, FB_FORMAT, FB_UPDATE } fb_op;
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volatile union {
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struct __attribute__((packed)) { struct framebuf fb; uint8_t end[0]; } set_fb_rq;
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struct __attribute__((packed)) { uint8_t nbits; uint8_t end[0]; } set_nbits_rq;
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@ -174,6 +174,7 @@ void cfg_spi1() {
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}
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void SPI1_IRQHandler() {
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GPIOA->BSRR = GPIO_BSRR_BS_0; // Debug
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switch (spi_state) {
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case SPI_AUX:
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strobe_aux();
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@ -190,6 +191,7 @@ void SPI1_IRQHandler() {
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break;
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}
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spi_state ++;
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GPIOA->BSRR = GPIO_BSRR_BR_0; // Debug
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}
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uint8_t segment_map[8] = {5, 7, 6, 4, 1, 3, 0, 2};
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@ -234,19 +236,62 @@ int shift_data() {
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}
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SPI1->CR2 |= SPI_CR2_TXEIE;
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return 1<<active_bit;
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return active_bit;
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}
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#define NBITS_MAX 14
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/* Bit timing base value. This is the lowes bit interval used */
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#define PERIOD_BASE 4
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/* This value is a constant offset added to every bit period to allow for the timer IRQ handler to execute. This is set
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* empirically using a debugger and a logic analyzer. */
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#define TIMER_CYCLES_FOR_SPI_TRANSMISSIONS 25
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/* Defines for brevity */
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#define A TIMER_CYCLES_FOR_SPI_TRANSMISSIONS
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#define B PERIOD_BASE
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/* This is a constant offset containing some empirically determined correction values */
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#define C (0)
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/* This lookup table maps bit positions to timer period values. This is a lookup table to allow for the compensation for
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* non-linear effects of ringing at lower bit durations.
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*/
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static uint16_t timer_period_lookup[NBITS_MAX] = {
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/* LSB here */
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A - C + (B<< 0),
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A - C + (B<< 1),
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A - C + (B<< 2),
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A - C + (B<< 3),
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A - C + (B<< 4),
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A - C + (B<< 5),
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A - C + (B<< 6),
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A - C + (B<< 7),
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A - C + (B<< 8),
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A - C + (B<< 9),
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A - C + (B<<10),
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A - C + (B<<11),
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A - C + (B<<12),
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A - C + (B<<13),
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/* MSB here */
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};
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/* Don't pollute the global namespace */
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#undef A
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#undef B
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#undef C
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void cfg_timer3() {
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/* FIXME update comment */
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/* Capture/compare channel 1 is used to generate the LED driver !OE signal. Channel 2 is used to trigger the
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* interrupt to load the next bits in to the shift registers. Channel 2 triggers simultaneously with channel 1 at
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* long !OE periods but will be delayed slightly to a fixed 32 timer periods (12.8us) to allow for SPI1 to finish
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* shifting out all frame data before asserting !OE. */
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TIM3->CCMR1 = 6<<TIM_CCMR1_OC1M_Pos; /* PWM Mode 1 */
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TIM3->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC2E | TIM_CCER_CC2P; /* Inverting output */
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TIM3->DIER = TIM_DIER_CC2IE;
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TIM3->CCR2 = 1000; /* Schedule first interrupt */
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TIM3->PSC = SystemCoreClock/5000000 * 2; /* 0.40us/tick */
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TIM3->CCMR1 = (6<<TIM_CCMR1_OC1M_Pos) | TIM_CCMR1_OC1PE; /* PWM Mode 1, enable CCR preload */
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TIM3->CCER = TIM_CCER_CC1E; /* Inverting output */
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TIM3->DIER = TIM_DIER_UIE;
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TIM3->PSC = SystemCoreClock/5000000 * 2 - 1; /* 0.20us/tick */
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TIM3->ARR = 0xffff;
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TIM3->EGR |= TIM_EGR_UG;
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TIM3->CR1 = TIM_CR1_ARPE;
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@ -256,18 +301,16 @@ void cfg_timer3() {
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}
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void TIM3_IRQHandler() {
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GPIOA->BSRR = GPIO_BSRR_BS_4; // Debug
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//TIM3->CR1 &= ~TIM_CR1_CEN_Msk; FIXME
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int period = shift_data();
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TIM3->CCR1 = period;
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if (period < 32) /* FIXME this constant */
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TIM3->CCR2 = 32;
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else
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TIM3->CCR2 = period;
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TIM3->CNT = 0xffff; /* To not enable OC1 riglt away */
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int idx = shift_data();
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TIM3->CCR1 = TIMER_CYCLES_FOR_SPI_TRANSMISSIONS;
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TIM3->ARR = timer_period_lookup[idx];
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TIM3->SR &= ~TIM_SR_CC2IF_Msk;
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TIM3->SR &= ~TIM_SR_UIF_Msk;
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//TIM3->CR1 |= TIM_CR1_CEN;
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GPIOA->BSRR = GPIO_BSRR_BR_4; // Debug
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}
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enum Command {
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@ -300,14 +343,13 @@ void uart_config(void) {
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| USART_CR1_MME
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/* WAKE clear */
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/* PCE, PS clear */
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//| USART_CR1_RXNEIE
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| USART_CR1_RXNEIE
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/* other interrupts clear */
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| USART_CR1_TE
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| USART_CR1_RE;
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//USART1->CR2 = USART_CR2_RTOEN; /* Timeout enable */
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USART1->CR3 = USART_CR3_DEM; /* RS485 DE enable (output on RTS) */
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//| USART_CR3_DMAT;
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/* Baud rate 2MBd */
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USART1->CR3 = USART_CR3_DEM /* RS485 DE enable (output on RTS) */
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| USART_CR3_DMAT;
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int usartdiv = 25;
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USART1->BRR = usartdiv;
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USART1->CR1 |= USART_CR1_UE;
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@ -380,9 +422,11 @@ int main(void) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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GPIOA->MODER |=
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(2<<GPIO_MODER_MODER1_Pos) /* PA1 - RS485 DE */
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(1<<GPIO_MODER_MODER0_Pos) /* PA0 - Debug */
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| (2<<GPIO_MODER_MODER1_Pos) /* PA1 - RS485 DE */
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| (2<<GPIO_MODER_MODER2_Pos) /* PA2 - RS485 TX */
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| (2<<GPIO_MODER_MODER3_Pos) /* PA3 - RS485 RX */
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| (1<<GPIO_MODER_MODER4_Pos) /* PA3 - Debug */
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| (2<<GPIO_MODER_MODER5_Pos) /* PA5 - SCLK */
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| (2<<GPIO_MODER_MODER6_Pos) /* PA6 - LED !OE */
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| (2<<GPIO_MODER_MODER7_Pos) /* PA7 - MOSI */
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@ -391,9 +435,11 @@ int main(void) {
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/* Set shift register IO GPIO output speed */
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GPIOA->OSPEEDR |=
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(2<<GPIO_OSPEEDR_OSPEEDR1_Pos) /* RS485 DE */
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(2<<GPIO_OSPEEDR_OSPEEDR0_Pos) /* Debug */
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| (2<<GPIO_OSPEEDR_OSPEEDR1_Pos) /* RS485 DE */
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| (2<<GPIO_OSPEEDR_OSPEEDR2_Pos) /* TX */
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| (2<<GPIO_OSPEEDR_OSPEEDR3_Pos) /* RX */
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| (2<<GPIO_OSPEEDR_OSPEEDR4_Pos) /* Debug */
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| (2<<GPIO_OSPEEDR_OSPEEDR5_Pos) /* SCLK */
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| (2<<GPIO_OSPEEDR_OSPEEDR6_Pos) /* LED !OE */
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| (2<<GPIO_OSPEEDR_OSPEEDR7_Pos) /* MOSI */
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@ -424,43 +470,19 @@ int main(void) {
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cfg_timer3();
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SysTick_Config(SystemCoreClock/1000); /* 1ms interval */
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uart_config();
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//adc_config();
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adc_config();
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int rx_idx = 0;
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int expect_framing = 1;
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uint8_t data;
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unsigned int num_overrun_errors = 0;
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/* FIXME document framing/rx state machine */
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volatile uint8_t *rxd = rx_buf.byte_data;
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while (42) {
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if (USART1->ISR & USART_ISR_ORE) {
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USART1->ICR |= USART_ICR_ORECF;
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num_overrun_errors ++;
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} else if (USART1->ISR & USART_ISR_FE) {
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USART1->ICR |= USART_ICR_FECF;
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} else if (USART1->ISR & USART_ISR_RXNE) {
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data = USART1->RDR;
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/*
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if (expect_framing) {
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if (data == 0x42) {
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expect_framing = 0;
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} else {
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rx_idx = 0;
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}
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} else {
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rx_buf.byte_data[rx_idx] = data;
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rx_idx++;
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if (rx_idx >= sizeof(rx_buf.set_fb_rq)) {
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rx_idx = 0;
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if (fb_op == FB_WRITE) {
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transpose_data(rx_buf.byte_data, write_fb);
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fb_op = FB_UPDATE;
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}
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}
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if ((rx_idx&0x1F) == 0) {
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expect_framing = 1;
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if (USART1->ISR & USART_ISR_RXNE) {
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*rxd++ = USART1->RDR;
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if (rxd >= rx_buf.set_fb_rq.end) {
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rxd = rx_buf.byte_data;
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if (fb_op == FB_FORMAT) {
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transpose_data(rx_buf.byte_data, write_fb);
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fb_op = FB_UPDATE;
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}
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}
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*/
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}
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}
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}
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