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  • f037001053 Add local changes master jaseg 2020-04-11 17:33:20 +02:00
  • bc136ef5b1 Small firmware foo jaseg 2018-04-20 14:04:16 +02:00
  • 6d5c101e2f Add global README jaseg 2018-01-05 12:32:21 +01:00
  • c2e293d976 Split project into individual source files and add license jaseg 2018-01-05 12:23:24 +01:00
  • e3094b18d4 Firmware directory reorganization jaseg 2018-01-05 11:53:52 +01:00
  • 31fc78d0e0 Add some documentation jaseg 2018-01-05 11:39:20 +01:00
  • a70ad99b36 Make status request work, fix uc-side cobs encoding bug jaseg 2017-12-10 20:17:51 +01:00
  • 75d4d0f3df Prettified the python side of things a bit jaseg 2017-12-10 16:12:12 +01:00
  • 582e6d7786 Add discovery and addressing mechanism jaseg 2017-12-10 15:59:56 +01:00
  • b315bc1e96 Prettify and document AUX LED handling jaseg 2017-12-10 13:50:54 +01:00
  • bf2c701353 Make comm and error LEDs useful jaseg 2017-12-10 13:41:24 +01:00
  • 3ec035844f ADC temperature measurement works now jaseg 2017-12-10 13:28:23 +01:00
  • 322b306bf2 ADC properly triggering now jaseg 2017-12-10 13:11:30 +01:00
  • 49c4d3ab8e Rough ADC triggering works now jaseg 2017-12-10 12:28:51 +01:00
  • 0dab3f4007 Add lots of doc and fix segment driving jaseg 2017-12-10 01:07:53 +01:00
  • 43785b2307 Framing works now jaseg 2017-12-09 20:52:18 +01:00
  • a542e6f291 Framing experiments jaseg 2017-12-09 19:54:21 +01:00
  • 84fd070709 UART and LEDs playing nicely jaseg 2017-12-09 19:01:53 +01:00
  • 58796333b9 Made all ISRs *fast* (<2.5us) jaseg 2017-12-09 15:11:41 +01:00
  • 6b7518b29f Aux register loading further optimized jaseg 2017-12-09 15:06:51 +01:00
  • d2194c5ae2 Fixed aux cycle jaseg 2017-12-09 14:41:58 +01:00
  • 1c58250425 Cycle timing is fixed again jaseg 2017-12-09 12:08:32 +01:00
  • a1eff91d77 Basic UART working, but too slow jaseg 2017-12-08 19:25:11 +01:00
  • 723995c541 hw v0.4 jaseg 2017-09-18 11:26:05 +02:00
  • a823484163 Fix up RS485/digital power label jaseg 2017-09-06 14:36:50 +02:00
  • d4d0f850f0 Fix up version label and one ground trace jaseg 2017-09-06 14:30:43 +02:00
  • febcb5a933 Fixes for second prototype (v0.3) jaseg 2017-09-06 14:03:07 +02:00
  • 9b52622eab Temperature/VCC ADC working jaseg 2017-09-02 12:23:39 +02:00
  • 446dbe6412 Now with working source extraction from firmware jaseg 2017-09-01 20:52:34 +02:00
  • 5a19ab0e84 Add missing files jaseg 2017-09-01 20:32:15 +02:00
  • e6437f975b UART magic seems to be working now jaseg 2017-09-01 20:26:05 +02:00
  • 6b40626a1b DMA channel assignments redone, basic protocol stuff working jaseg 2017-09-01 15:44:39 +02:00
  • a832816d61 Serial protocol now working including CRC jaseg 2017-08-24 00:52:18 +02:00
  • 570f527a3a Interrupt-driven SPI1 fundamentally working jaseg 2017-08-23 14:11:45 +02:00
  • dbb03cbece Comms working except for TIM3/SPI1 race jaseg 2017-08-23 13:00:07 +02:00
  • abdf02426f Add cmsis export generator jaseg 2017-08-23 10:50:43 +02:00
  • 95e1a03648 Add transpose test jaseg 2017-08-23 10:50:16 +02:00
  • e9f79a2e99 Add profiling script jaseg 2017-08-22 20:13:10 +02:00
  • a18b197ac4 Benchmark code jaseg 2017-08-15 15:57:33 +02:00
  • 9eb92caa6c working commit jaseg 2017-08-15 14:34:20 +02:00
  • 952f3c03ac Temporary for bit shuffling jaseg 2017-08-15 10:34:57 +02:00
  • 71ad806c88 Working on uart code jaseg 2017-08-15 10:30:35 +02:00
  • 369c090955 Multiplexing is working jaseg 2017-08-14 12:51:49 +02:00
  • 7a5791e976 Board rev 0.3 working jaseg 2017-08-13 15:48:48 +02:00
  • 1ae37bce5b Second production run, v0.3 jaseg 2017-07-21 20:01:20 +02:00
  • 5bb67efb4a Final silk art positioning jaseg 2017-07-21 01:00:43 +02:00
  • 2775e1fc61 Add missing firmware build files jaseg 2017-07-20 16:06:33 +02:00
  • 16328e9723 Second board revision jaseg 2017-07-20 16:05:07 +02:00
  • 6ec97df9de Schematic fixed up so far jaseg 2017-07-15 22:43:04 +02:00
  • 6f12a41cc6 Add resistor calculation script jaseg 2017-06-12 13:03:18 +02:00
  • 6301aad169 Test program working jaseg 2017-06-11 21:30:02 +02:00
  • 84de029e74 fw working commit jaseg 2017-06-10 19:14:18 +02:00
  • 4dbd135d68 foo jaseg 2017-06-10 19:13:42 +02:00
  • 0f52be1e7a Release v0.2 jaseg 2017-05-17 11:25:17 +02:00
  • 7d34875369 Design mostly done jaseg 2017-05-04 13:47:53 +02:00
  • 91f22c5435 Layout mostly done jaseg 2017-05-02 16:05:05 +02:00
  • cb2ca6e9c9 Foo jaseg 2017-04-30 15:58:28 +02:00
  • cdc0c4fa07 Pre safety fixup jaseg 2017-04-29 20:56:06 +02:00
  • b5bf5670b6 Added protection stuff jaseg 2017-04-28 21:29:58 +02:00
  • 9af9f5768b Initial commit jaseg 2017-04-26 11:57:45 +02:00