Temperature/VCC ADC working
This commit is contained in:
jaseg
parent
446dbe6412
commit
9b52622eab
2 changed files with 95 additions and 21 deletions
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@ -11,13 +11,13 @@ OBJCOPY := arm-none-eabi-objcopy
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OBJDUMP := arm-none-eabi-objdump
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SIZE := arm-none-eabi-size
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CFLAGS = -g -Wall -std=gnu11 -O2 -fdump-rtl-expand -DBUS_ADDR=$(BUS_ADDR)
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CFLAGS = -g -Wall -std=gnu11 -O0 -fdump-rtl-expand -DBUS_ADDR=$(BUS_ADDR)
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CFLAGS += -mlittle-endian -mcpu=cortex-m0 -march=armv6-m -mthumb
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#CFLAGS += -ffunction-sections -fdata-sections
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LDFLAGS = -nostartfiles
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#LDFLAGS += -specs=rdimon.specs -DSEMIHOSTING
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LDFLAGS += -Wl,-Map=main.map -nostdlib
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LDFLAGS += -Wl,--gc-sections
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#LDFLAGS += -Wl,--gc-sections
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LIBS = -lgcc
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#LIBS += -lrdimon
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112
fw/main.c
112
fw/main.c
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@ -46,8 +46,13 @@ void strobe_leds(void) {
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#define FIRMWARE_VERSION 1
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#define HARDWARE_VERSION 1
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volatile uint16_t adc_vcc_mv = 0;
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volatile uint16_t adc_temp_tenth_celsius = 0;
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#define TS_CAL1 (*(uint16_t *)0x1FFFF7B8)
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#define VREFINT_CAL (*(uint16_t *)0x1FFFF7BA)
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volatile int16_t adc_vcc_mv = 0;
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volatile int16_t adc_temp_tenth_celsius = 0;
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volatile uint16_t adc_buf[2];
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volatile unsigned int sys_time = 0;
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volatile unsigned int sys_time_seconds = 0;
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@ -71,7 +76,7 @@ volatile union {
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digit_cols;
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uint32_t uptime;
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uint32_t millifps;
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uint16_t vcc_mv,
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int16_t vcc_mv,
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temp_tenth_celsius;
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uint8_t nbits;
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} desc_reply;
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@ -85,15 +90,15 @@ extern uint8_t bus_addr;
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#define SR_ILED_HIGH 0x0080
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#define SR_ILED_LOW 0x0040
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inline unsigned int stk_start() {
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unsigned int stk_start(void) {
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return SysTick->VAL;
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}
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inline unsigned int stk_end(unsigned int start) {
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unsigned int stk_end(unsigned int start) {
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return (start - SysTick->VAL) & 0xffffff;
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}
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inline unsigned int stk_microseconds() {
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unsigned int stk_microseconds(void) {
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return sys_time*1000 + (1000 - (SysTick->VAL / (SystemCoreClock/1000000)));
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}
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@ -235,13 +240,17 @@ enum Command {
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};
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enum {
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PROT_ADDR,
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PROT_ADDR_IDLE,
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PROT_ADDR_ERR,
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PROT_ADDR_COMPLETE,
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PROT_ADDR_CRC,
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PROT_ADDR_INIT,
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PROT_CMD,
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PROT_CRC,
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PROT_COMPLETE,
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PROT_INVALID,
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N_PROT_STATES
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} protocol_state = PROT_ADDR;
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} protocol_state = PROT_ADDR_INIT;
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void crc_reset(void) {
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CRC->CR |= CRC_CR_RESET;
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@ -282,35 +291,44 @@ int crc_error_count = 0;
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static volatile uint32_t rx_crc;
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static volatile enum Command rx_cmd;
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void USART1_IRQHandler() {
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uint8_t data = USART1->RDR;
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int isr = USART1->ISR;
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USART1->RQR |= USART_RQR_RXFRQ;
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/* Overrun detected? */
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if (isr & USART_ISR_ORE) {
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USART1->ICR |= USART_ICR_ORECF;
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asm("bkpt");
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goto errout;
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}
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if (isr & USART_ISR_IDLE) {
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USART1->ICR |= USART_ICR_IDLECF;
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USART1->CR3 &= ~USART_CR3_DMAR_Msk;
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DMA1_Channel3->CCR &= ~DMA_CCR_EN_Msk;
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protocol_state = PROT_ADDR;
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DMA1->IFCR |= DMA_IFCR_CGIF3;
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protocol_state = PROT_ADDR_IDLE;
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USART1->RQR |= USART_RQR_RXFRQ;
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USART1->CR1 |= USART_CR1_RXNEIE;
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return;
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}
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switch(protocol_state) {
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case PROT_ADDR:
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if (data == bus_addr) /* Are we addressed? */
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case PROT_ADDR_IDLE:
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case PROT_ADDR_ERR:
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case PROT_ADDR_COMPLETE:
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case PROT_ADDR_CRC:
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case PROT_ADDR_INIT:
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if (data == bus_addr) { /* Are we addressed? */
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protocol_state = PROT_CMD;
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else /* We are not. Mute USART until next idle condition */
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} else { /* We are not. Mute USART until next idle condition */
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asm("bkpt");
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goto errout;
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}
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break;
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case PROT_CMD:
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if (data > N_CMDS)
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if (data > N_CMDS) {
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asm("bkpt");
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goto errout;
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}
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rx_cmd = data;
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crc_reset();
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@ -319,8 +337,9 @@ void USART1_IRQHandler() {
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size_t payload_len = cmd_payload_len[data];
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if (payload_len) {
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/* Is rx_buf currently occupied by the main loop formatting frame data? */
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if (fb_op != FB_WRITE)
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/* if (fb_op != FB_WRITE) FIXME DEBUG put this back
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goto errout;
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*/
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kickoff_uart_rx_dma(&rx_buf, payload_len);
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DMA1_Channel5->CNDTR = payload_len;
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protocol_state = PROT_CRC;
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@ -336,8 +355,12 @@ void USART1_IRQHandler() {
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return;
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errout:
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protocol_state = PROT_ADDR;
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USART1->CR3 &= ~USART_CR3_DMAR_Msk;
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DMA1_Channel3->CCR &= ~DMA_CCR_EN_Msk;
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DMA1->IFCR |= DMA_IFCR_CGIF3;
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protocol_state = PROT_ADDR_ERR;
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USART1->RQR |= USART_RQR_MMRQ;
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asm("bkpt");
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}
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void DMA1_Channel2_3_IRQHandler() {
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@ -360,7 +383,7 @@ void DMA1_Channel2_3_IRQHandler() {
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if (rx_crc != CRC->DR) {
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crc_error_count++;
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protocol_state = PROT_ADDR;
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protocol_state = PROT_ADDR_CRC;
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/* re-enable receive interrupt */
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USART1->RQR |= USART_RQR_RXFRQ;
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USART1->RQR |= USART_RQR_MMRQ;
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@ -368,7 +391,7 @@ void DMA1_Channel2_3_IRQHandler() {
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break;
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}
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protocol_state = PROT_ADDR;
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protocol_state = PROT_ADDR_COMPLETE;
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switch(rx_cmd) {
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case CMD_PING:
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@ -477,6 +500,56 @@ void uart_config(void) {
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NVIC_SetPriority(DMA1_Channel4_5_IRQn, 5);
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}
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#define ADC_OVERSAMPLING 12
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uint32_t vsense;
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void DMA1_Channel1_IRQHandler(void) {
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static int count = 0;
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static uint32_t adc_aggregate[2] = {0, 0};
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DMA1->IFCR |= DMA_IFCR_CGIF1;
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adc_aggregate[0] += adc_buf[0];
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adc_aggregate[1] += adc_buf[1];
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if (count++ == (1<<ADC_OVERSAMPLING)) {
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adc_vcc_mv = (3300 * VREFINT_CAL)/(adc_aggregate[0]>>ADC_OVERSAMPLING);
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vsense = ((adc_aggregate[1]>>ADC_OVERSAMPLING) * adc_vcc_mv)/4095 ;
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adc_temp_tenth_celsius = 300 - (((TS_CAL1*adc_vcc_mv/4095) - vsense)*100)/43;
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count = 0;
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adc_aggregate[0] = 0;
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adc_aggregate[1] = 0;
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}
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}
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void adc_config(void) {
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ADC1->CFGR1 = ADC_CFGR1_CONT | ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG;
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ADC1->CFGR2 = 2<<ADC_CFGR2_CKMODE_Pos;
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ADC1->SMPR = 7<<ADC_SMPR_SMP_Pos;
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ADC1->CHSELR = ADC_CHSELR_CHSEL16 | ADC_CHSELR_CHSEL17;
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ADC->CCR = ADC_CCR_TSEN | ADC_CCR_VREFEN;
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ADC1->CR |= ADC_CR_ADCAL;
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while (ADC1->CR & ADC_CR_ADCAL)
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;
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ADC1->CR |= ADC_CR_ADEN;
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ADC1->CR |= ADC_CR_ADSTART;
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/* FIXME handle adc overrun */
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DMA1_Channel1->CPAR = (unsigned int)&ADC1->DR;
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DMA1_Channel1->CMAR = (unsigned int)&adc_buf;
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DMA1_Channel1->CNDTR = sizeof(adc_buf)/sizeof(adc_buf[0]);
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DMA1_Channel1->CCR = (0<<DMA_CCR_PL_Pos);
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DMA1_Channel1->CCR |=
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DMA_CCR_CIRC
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| (1<<DMA_CCR_MSIZE_Pos) /* 16 bit */
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| (1<<DMA_CCR_PSIZE_Pos) /* 16 bit */
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| DMA_CCR_MINC
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| DMA_CCR_TCIE;
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DMA1_Channel1->CCR |= DMA_CCR_EN;
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NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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NVIC_SetPriority(DMA1_Channel1_IRQn, 6);
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}
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int main(void) {
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR&RCC_CR_HSERDY));
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@ -490,7 +563,7 @@ int main(void) {
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SystemCoreClockUpdate();
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_DMAEN | RCC_AHBENR_CRCEN | RCC_AHBENR_FLITFEN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_SYSCFGEN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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GPIOA->MODER |=
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@ -538,6 +611,7 @@ int main(void) {
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cfg_timer3();
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SysTick_Config(SystemCoreClock/1000); /* 1ms interval */
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uart_config();
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adc_config();
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while (42) {
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if (fb_op == FB_FORMAT) {
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