UART magic seems to be working now
This commit is contained in:
jaseg
parent
6b40626a1b
commit
e6437f975b
4 changed files with 216 additions and 121 deletions
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@ -47,8 +47,14 @@ cmsis_exports.c: $(CMSIS_DEV_PATH)/Include/stm32f030x6.h $(CMSIS_PATH)/Include/c
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%.dot: %.elf
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r2 -a arm -qc 'aa;agC' $< 2>/dev/null >$@
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sources.tar.xz: main.c transpose.c transpose.h
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tar -caf $@ $^
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main.elf: main.o startup_stm32f030x6.o system_stm32f0xx.o $(HAL_PATH)/Src/stm32f0xx_ll_utils.o base.o cmsis_exports.o transpose.o
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sources.c: sources.tar.xz
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xxd -i $< > $@
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main.elf: main.o startup_stm32f030x6.o system_stm32f0xx.o $(HAL_PATH)/Src/stm32f0xx_ll_utils.o base.o cmsis_exports.o transpose.o bus_addr.o
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$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS)
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$(OBJCOPY) -O ihex $@ $(@:.elf=.hex)
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$(OBJCOPY) -O binary $@ $(@:.elf=.bin)
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303
fw/main.c
303
fw/main.c
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@ -43,47 +43,41 @@ void strobe_leds(void) {
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GPIOA->BSRR = GPIO_BSRR_BR_9;
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}
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#define FIRMWARE_VERSION 1
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#define HARDWARE_VERSION 1
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volatile uint16_t adc_vcc_mv = 0;
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volatile uint16_t adc_temp_tenth_celsius = 0;
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volatile unsigned int sys_time = 0;
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volatile unsigned int sys_time_seconds = 0;
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volatile struct framebuf fb[2] = {0};
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volatile struct framebuf *read_fb=fb+0, *write_fb=fb+1;
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volatile int led_state = 0;
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volatile enum { FB_WRITE, FB_FORMAT, FB_UPDATE } fb_op;
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volatile uint8_t rx_buf[sizeof(struct framebuf) + 4 /* crc */];
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volatile union {
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struct {
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struct __attribute__((packed)) { struct framebuf fb; } set_fb_rq;
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struct __attribute__((packed)) { uint8_t nbits; } set_nbits_rq;
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uint8_t byte_data[0];
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} rx_buf;
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volatile union {
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struct { uint32_t magic; } ping_reply;
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struct __attribute__((packed)) {
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uint8_t firmware_version,
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hardware_version,
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digit_rows,
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digit_cols;
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uint32_t uptime;
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uint32_t millifps;
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} fps_reply;
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uint16_t vcc_mv,
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temp_tenth_celsius;
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uint8_t nbits;
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} desc_reply;
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} tx_buf;
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volatile uint8_t this_addr = 0x05; /* FIXME */
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union {
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struct {
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uint8_t device_id __attribute__((aligned(2)));
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};
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uint16_t flash_data[0];
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} flash_data __attribute__((section ("configflash")));
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void write_config(void *target, uint16_t value) {
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FLASH->KEYR = 0x45670123;
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FLASH->KEYR = 0xCDEF89AB;
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FLASH->CR = FLASH_CR_PG;
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*(uint16_t *)target = value;
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while (FLASH->SR & FLASH_SR_BSY)
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;
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FLASH->CR = FLASH_CR_LOCK;
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}
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void erase_config() {
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FLASH->KEYR = 0x45670123;
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FLASH->KEYR = 0xCDEF89AB;
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FLASH->CR = FLASH_CR_PER;
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FLASH->AR = (uint32_t)&flash_data;
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FLASH->CR = FLASH_CR_STRT;
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while (FLASH->SR & FLASH_SR_BSY)
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;
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FLASH->CR = FLASH_CR_LOCK;
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}
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extern uint8_t bus_addr;
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#define LED_COMM 0x0001
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#define LED_ERROR 0x0002
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@ -157,6 +151,7 @@ void SPI1_IRQHandler() {
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uint8_t segment_map[8] = {5, 7, 6, 4, 1, 3, 0, 2};
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static volatile int frame_duration_us;
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volatile int nbits = MAX_BITS;
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/* returns new bit time in cycles */
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int shift_data() {
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static int active_segment = 0;
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@ -165,11 +160,11 @@ int shift_data() {
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/* Note: On boot, multiplexing will start with bit 1 due to the next few lines. This is perfectly ok. */
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active_bit++;
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if (active_bit == nbits) {
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if (active_bit >= nbits) {
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active_bit = 0;
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active_segment++;
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if (active_segment == nsegments) {
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if (active_segment == NSEGMENTS) {
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active_segment = 0;
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int time = stk_microseconds();
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@ -183,13 +178,13 @@ int shift_data() {
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}
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}
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spi_word = read_fb->data[active_bit*frame_size_words + active_segment];
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spi_word = read_fb->data[active_bit*FRAME_SIZE_WORDS + active_segment];
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spi_state = SPI_AUX;
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SPI1->DR = (read_fb->brightness ? SR_ILED_HIGH : SR_ILED_LOW)
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| (led_state<<1)
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| (0xff00 ^ (0x100<<segment_map[active_segment]));
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} else {
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spi_word = read_fb->data[active_bit*frame_size_words + active_segment];
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spi_word = read_fb->data[active_bit*FRAME_SIZE_WORDS + active_segment];
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spi_state = SPI_WORD0;
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SPI1->DR = spi_word>>16;
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}
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@ -233,81 +228,184 @@ void TIM3_IRQHandler() {
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enum Command {
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CMD_PING,
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CMD_SET_ADDR,
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CMD_SET_FB,
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CMD_SET_NBITS,
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CMD_GET_DESC,
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CMD_GET_FRAMERATE,
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CMD_ERASE_CONFIG,
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N_CMDS
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};
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enum {
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PROT_ADDR,
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PROT_CMD,
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PROT_
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PROT_CRC,
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PROT_COMPLETE,
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PROT_INVALID,
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N_PROT_STATES
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} protocol_state = PROT_ADDR;
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int gaddr;
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void crc_reset(void) {
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CRC->CR |= CRC_CR_RESET;
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while (CRC->CR&CRC_CR_RESET)
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;
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}
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void crc_feed(uint8_t data) {
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*(uint8_t *)&CRC->DR = data;
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}
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void kickoff_uart_rx_dma(volatile void *target, size_t len) {
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DMA1_Channel3->CMAR = (unsigned int)target;
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DMA1_Channel3->CNDTR = len;
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/* Disable RX interrupt for duration of DMA transfer */
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USART1->CR1 &= ~USART_CR1_RXNEIE_Msk;
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/* Enable DMA transfer to write buffer */
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DMA1->IFCR |= DMA_IFCR_CGIF3;
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DMA1_Channel3->CCR |= DMA_CCR_EN;
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USART1->CR3 |= USART_CR3_DMAR;
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}
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void kickoff_uart_tx_dma(size_t len) {
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DMA1_Channel4->CNDTR = len;
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USART1->ICR |= USART_ICR_TCCF; /* FIXME: (1) is this necessary? (2) where should this be done? */
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DMA1_Channel4->CCR |= DMA_CCR_EN;
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USART1->RQR |= USART_RQR_MMRQ;
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}
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static size_t cmd_payload_len[N_CMDS] = {
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[CMD_PING] = 0,
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[CMD_SET_FB] = sizeof(rx_buf.set_fb_rq),
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[CMD_SET_NBITS] = sizeof(rx_buf.set_nbits_rq),
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[CMD_GET_DESC] = 0,
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};
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int crc_error_count = 0;
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static volatile uint32_t rx_crc;
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static volatile enum Command rx_cmd;
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void USART1_IRQHandler() {
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gaddr = USART1->RDR;
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uint8_t data = USART1->RDR;
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int isr = USART1->ISR;
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USART1->RQR |= USART_RQR_RXFRQ;
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int addr = gaddr; /* FIXME DEBUG */
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int cmd = addr>>5;
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addr &= 0x1F;
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/* Overrun detected? */
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if (USART1->ISR & USART_ISR_ORE) {
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if (isr & USART_ISR_ORE) {
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USART1->ICR |= USART_ICR_ORECF;
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USART1->RQR |= USART_RQR_MMRQ;
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goto errout;
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}
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/* Are we addressed? */
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if (addr != this_addr) {
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asm("bkpt");
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/* We are not. Mute USART until next idle condition */
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USART1->RQR |= USART_RQR_MMRQ;
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} else {
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/* We are. Switch by command. */
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switch (cmd) {
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case CMD_PING:
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USART1->TDR = 42;
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USART1->RQR |= USART_RQR_MMRQ;
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break;
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case CMD_SET_FB:
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/* Are we ready to process new frame data? */
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if (fb_op != FB_WRITE) {
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//asm("bkpt"); /* FIXME DEBUG */
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goto errout; /* Error: Not yet ready to receive new packet */
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}
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/* Disable this RX interrupt for duration of DMA transfer */
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USART1->CR1 &= ~USART_CR1_RXNEIE_Msk;
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/* Enable DMA transfer to write buffer */
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DMA1->IFCR |= DMA_IFCR_CGIF3;
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DMA1_Channel3->CCR |= DMA_CCR_EN;
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USART1->CR3 |= USART_CR3_DMAR;
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break;
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case CMD_GET_FRAMERATE:
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tx_buf.fps_reply.millifps = frame_duration_us > 0 ? 1000000000 / frame_duration_us : 0;
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DMA1_Channel4->CNDTR = sizeof(tx_buf.fps_reply);
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USART1->ICR |= USART_ICR_TCCF; /* FIXME: (1) is this necessary? (2) where should this be done? */
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DMA1_Channel4->CCR |= DMA_CCR_EN;
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USART1->RQR |= USART_RQR_MMRQ;
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break;
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if (isr & USART_ISR_IDLE) {
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USART1->ICR |= USART_ICR_IDLECF;
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USART1->CR3 &= ~USART_CR3_DMAR_Msk;
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DMA1_Channel3->CCR &= ~DMA_CCR_EN_Msk;
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protocol_state = PROT_ADDR;
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USART1->RQR |= USART_RQR_RXFRQ;
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USART1->CR1 |= USART_CR1_RXNEIE;
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return;
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}
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switch(protocol_state) {
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case PROT_ADDR:
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if (data == bus_addr) /* Are we addressed? */
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protocol_state = PROT_CMD;
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else /* We are not. Mute USART until next idle condition */
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goto errout;
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break;
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case PROT_CMD:
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if (data > N_CMDS)
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goto errout;
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rx_cmd = data;
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crc_reset();
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crc_feed(data);
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size_t payload_len = cmd_payload_len[data];
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if (payload_len) {
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/* Is rx_buf currently occupied by the main loop formatting frame data? */
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if (fb_op != FB_WRITE)
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goto errout;
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kickoff_uart_rx_dma(&rx_buf, payload_len);
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DMA1_Channel5->CNDTR = payload_len;
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protocol_state = PROT_CRC;
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} else {
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kickoff_uart_rx_dma(&rx_crc, sizeof(rx_crc));
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protocol_state = PROT_COMPLETE;
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}
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break;
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default:
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/* can/must not happen */
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asm("bkpt");
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}
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return;
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errout:
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/* FIXME */
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return;
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protocol_state = PROT_ADDR;
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USART1->RQR |= USART_RQR_MMRQ;
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}
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void DMA1_Channel2_3_IRQHandler() {
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/* DMA Transfer complete */
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/* ...and disable this DMA channel */
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/* Disable this DMA channel */
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USART1->CR3 &= ~USART_CR3_DMAR_Msk;
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DMA1_Channel3->CCR &= ~DMA_CCR_EN_Msk;
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/* Kick off formatting code in main loop outside interrupt context */
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fb_op = FB_FORMAT;
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DMA1->IFCR |= DMA_IFCR_CGIF3;
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/* re-enable receive interrupt */
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USART1->RQR |= USART_RQR_RXFRQ;
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USART1->CR1 |= USART_CR1_RXNEIE;
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switch(protocol_state) {
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case PROT_CRC:
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kickoff_uart_rx_dma(&rx_crc, sizeof(rx_crc));
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protocol_state = PROT_COMPLETE;
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DMA1_Channel5->CCR |= DMA_CCR_EN;
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break;
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case PROT_COMPLETE:
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DMA1_Channel5->CCR &= ~DMA_CCR_EN_Msk;
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DMA1->IFCR |= DMA_IFCR_CGIF5;
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if (rx_crc != CRC->DR) {
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crc_error_count++;
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protocol_state = PROT_ADDR;
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/* re-enable receive interrupt */
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USART1->RQR |= USART_RQR_RXFRQ;
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USART1->RQR |= USART_RQR_MMRQ;
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USART1->CR1 |= USART_CR1_RXNEIE;
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break;
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}
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protocol_state = PROT_ADDR;
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switch(rx_cmd) {
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case CMD_PING:
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tx_buf.ping_reply.magic = 0x39404142;
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kickoff_uart_tx_dma(sizeof(tx_buf.ping_reply));
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break;;
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case CMD_SET_FB:
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fb_op = FB_UPDATE;
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break;
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case CMD_SET_NBITS:
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nbits = rx_buf.set_nbits_rq.nbits;
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break;
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case CMD_GET_DESC:
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tx_buf.desc_reply.firmware_version = FIRMWARE_VERSION;
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tx_buf.desc_reply.hardware_version = HARDWARE_VERSION;
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tx_buf.desc_reply.digit_rows = NROWS;
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tx_buf.desc_reply.digit_cols = NCOLS;
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tx_buf.desc_reply.uptime = sys_time_seconds;
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tx_buf.desc_reply.vcc_mv = adc_vcc_mv;
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tx_buf.desc_reply.temp_tenth_celsius = adc_temp_tenth_celsius;
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tx_buf.desc_reply.nbits = nbits;
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tx_buf.desc_reply.millifps = frame_duration_us > 0 ? 1000000000 / frame_duration_us : 0;
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kickoff_uart_tx_dma(sizeof(tx_buf.desc_reply));
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break;
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default:
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/* can/must not happen */
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asm("bkpt");
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}
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/* re-enable receive interrupt */
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USART1->RQR |= USART_RQR_RXFRQ;
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USART1->CR1 |= USART_CR1_RXNEIE;
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break;
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default:
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/* can/must not happen */
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asm("bkpt");
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}
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}
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void DMA1_Channel4_5_IRQHandler() {
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@ -326,6 +424,7 @@ void uart_config(void) {
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/* WAKE clear */
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/* PCE, PS clear */
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| USART_CR1_RXNEIE
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| USART_CR1_IDLEIE
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/* other interrupts clear */
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| USART_CR1_TE
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| USART_CR1_RE;
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@ -338,8 +437,6 @@ void uart_config(void) {
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/* Configure DMA 1 / Channel 3 for USART frame data reception: USART1->RDR -> rx_buf */
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DMA1_Channel3->CPAR = (unsigned int)&USART1->RDR;
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DMA1_Channel3->CMAR = (unsigned int)rx_buf;
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DMA1_Channel3->CNDTR = sizeof(rx_buf);
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DMA1_Channel3->CCR = (1<<DMA_CCR_PL_Pos);
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DMA1_Channel3->CCR |=
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(0<<DMA_CCR_MSIZE_Pos) /* 8 bit */
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@ -350,7 +447,7 @@ void uart_config(void) {
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/* Configure DMA 1 / Channel 5 for USART frame data CRC check: rx_buf -> CRC->DR */
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DMA1_Channel5->CPAR = (unsigned int)&CRC->DR;
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DMA1_Channel5->CMAR = (unsigned int)rx_buf;
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DMA1_Channel5->CMAR = (unsigned int)&rx_buf;
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DMA1_Channel5->CCR = (0<<DMA_CCR_PL_Pos);
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DMA1_Channel5->CCR |=
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DMA_CCR_MEM2MEM /* Software trigger (precludes CIRC) */
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@ -380,7 +477,6 @@ void uart_config(void) {
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NVIC_SetPriority(DMA1_Channel4_5_IRQn, 5);
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}
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int errcnt = 0;
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int main(void) {
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR&RCC_CR_HSERDY));
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@ -393,7 +489,7 @@ int main(void) {
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RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
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SystemCoreClockUpdate();
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_DMAEN | RCC_AHBENR_CRCEN;
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_DMAEN | RCC_AHBENR_CRCEN | RCC_AHBENR_FLITFEN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_SYSCFGEN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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@ -445,25 +541,11 @@ int main(void) {
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while (42) {
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if (fb_op == FB_FORMAT) {
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CRC->CR |= CRC_CR_RESET;
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DMA1_Channel5->CNDTR = sizeof(struct framebuf);
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DMA1_Channel5->CCR |= DMA_CCR_EN;
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transpose_data(rx_buf.byte_data, write_fb);
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transpose_data(rx_buf, write_fb);
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while (!(DMA1->ISR & DMA_ISR_TCIF4))
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fb_op = FB_UPDATE;
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while (fb_op == FB_UPDATE)
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;
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DMA1->IFCR |= DMA_IFCR_CGIF4;
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||||
DMA1_Channel5->CCR &= ~DMA_CCR_EN_Msk;
|
||||
|
||||
if (CRC->DR != *(uint32_t *)(rx_buf+sizeof(struct framebuf))) {
|
||||
fb_op = FB_WRITE;
|
||||
errcnt++;
|
||||
} else {
|
||||
fb_op = FB_UPDATE;
|
||||
while (fb_op == FB_UPDATE)
|
||||
;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -484,6 +566,11 @@ void PendSV_Handler(void) {
|
|||
}
|
||||
|
||||
void SysTick_Handler(void) {
|
||||
static int n = 0;
|
||||
sys_time++;
|
||||
if (n++ == 1000) {
|
||||
n = 0;
|
||||
sys_time_seconds++;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
ENTRY(Reset_Handler)
|
||||
|
||||
MEMORY {
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 14K
|
||||
CONFIGFLASH (rw): ORIGIN = 0x08003800, LENGTH = 2K
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 0x3C00
|
||||
CONFIGFLASH (rw): ORIGIN = 0x08003C00, LENGTH = 0x400
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 4K
|
||||
}
|
||||
|
||||
|
|
@ -39,11 +39,13 @@ SECTIONS {
|
|||
_sidata = _etext;
|
||||
} >FLASH
|
||||
|
||||
/*
|
||||
.configflash : {
|
||||
. = ALIGN(2048);
|
||||
. = ALIGN(0x400);
|
||||
*(.configdata)
|
||||
_econfig = .;
|
||||
} >CONFIGFLASH
|
||||
} >FLASH
|
||||
*/
|
||||
|
||||
/* This is the initialized data section
|
||||
The program executes knowing that the data is in the RAM
|
||||
|
|
|
|||
|
|
@ -3,25 +3,25 @@
|
|||
|
||||
#include <stdint.h>
|
||||
|
||||
enum Segment { SegA, SegB, SegC, SegD, SegE, SegF, SegG, SegDP, nsegments };
|
||||
enum Segment { SegA, SegB, SegC, SegD, SegE, SegF, SegG, SegDP, NSEGMENTS };
|
||||
enum {
|
||||
nrows = 4,
|
||||
ncols = 8,
|
||||
nbits = 10,
|
||||
NROWS = 4,
|
||||
NCOLS = 8,
|
||||
MAX_BITS = 10,
|
||||
};
|
||||
|
||||
enum {
|
||||
frame_size_words = nrows*ncols*nsegments/32,
|
||||
FRAME_SIZE_WORDS = NROWS*NCOLS*NSEGMENTS/32,
|
||||
};
|
||||
|
||||
struct framebuf {
|
||||
/* Multiplexing order: first Digits, then Time/bits, last Segments */
|
||||
union {
|
||||
uint32_t data[nbits*frame_size_words];
|
||||
uint32_t data[MAX_BITS*FRAME_SIZE_WORDS];
|
||||
struct {
|
||||
struct {
|
||||
uint32_t data[frame_size_words];
|
||||
} frame[nbits];
|
||||
uint32_t data[FRAME_SIZE_WORDS];
|
||||
} frame[MAX_BITS];
|
||||
};
|
||||
};
|
||||
uint8_t brightness; /* 0 or 1; controls global brighntess control */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue