ADC properly triggering now
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jaseg
parent
49c4d3ab8e
commit
322b306bf2
2 changed files with 63 additions and 21 deletions
83
fw/main.c
83
fw/main.c
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@ -162,8 +162,11 @@ void cfg_spi1() {
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/* FIXME maybe try w/o BIDI */
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}
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/* This is a lookup table mapping segments to present a standard segment order on the UART interface. This is converted
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* into an internal representation once on startup in main(). The data type must be at least uint16. */
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uint32_t segment_map[8] = {5, 7, 6, 4, 1, 3, 0, 2};
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/* The value to be written into the aux register. This encompasses LED state as well as the current setting bits. */
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static volatile uint32_t aux_reg = 0;
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static volatile int frame_duration_us;
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volatile int nbits = MAX_BITS;
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@ -171,17 +174,34 @@ volatile int nbits = MAX_BITS;
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static unsigned int active_bit = 0;
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static int active_segment = 0;
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/* Bit timing base value. This is the lowes bit interval used */
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/* Bit timing base value. This is the lowes bit interval used in TIM1/TIM3 timer counts. */
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#define PERIOD_BASE 4
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/* This value is a constant offset added to every bit period to allow for the timer IRQ handler to execute. This is set
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* empirically using a debugger and a logic analyzer. */
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* empirically using a debugger and a logic analyzer.
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*
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* This value is in TIM1/TIM3 timer counts. */
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#define TIMER_CYCLES_FOR_SPI_TRANSMISSIONS 9
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/* This value sets the point when the LED strobe is asserted after the begin of the current bit cycle and IRQ
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* processing. This must be less than TIMER_CYCLES_FOR_SPI_TRANSMISSIONS but must be large enough to allow for the SPI
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* transmission to reliably finish.
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*
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* This value is in TIM1/TIM3 timer counts. */
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#define TIMER_CYCLES_BEFORE_LED_STROBE 8
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#define AUX_SPI_PRETRIGGER 64
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#define ADC_PRETRIGGER 64
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/* This value sets how long the TIM1 CC IRQ used for AUX register setting etc. is triggered before the end of the
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* longest cycle. This value should not be larger than PERIOD_BASE<<MIN_BITS to make sure the TIM1 CC IRQ does only
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* trigger in the longest cycle no matter what nbits is set to.
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*
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* This value is in TIM1/TIM3 timer counts. */
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#define AUX_SPI_PRETRIGGER 64 /* trigger with about 24us margin to the end of cycle/next TIM3 IRQ */
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/* This value sets how long a batch of ADC conversions used for temperature measurement is started before the end of the
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* longest cycle. Here too the above caveats apply.
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*
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* This value is in TIM1/TIM3 timer counts. */
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#define ADC_PRETRIGGER 150 /* trigger with about 12us margin to TIM1 CC IRQ */
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/* Defines for brevity */
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#define A TIMER_CYCLES_FOR_SPI_TRANSMISSIONS
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@ -230,7 +250,6 @@ void cfg_timers_led() {
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* * Compare unit 1 triggers the interrupt handler only in the longest bit cycle. The IRQ handler
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* * transmits the data to the auxiliary shift registers and
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* * swaps the frame buffers if pending
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* * kicks off the ADC for (oversampled) temperature measurement
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* * Compare unit 2 generates the led drivers' STROBE signal
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*
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* The AUX_STROBE signal for the two auxiliary shift registers that deal with segment selection, current setting and
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@ -261,10 +280,12 @@ void cfg_timers_led() {
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/* Setup CC1 and CC2. CC2 generates the LED drivers' STROBE, CC1 triggers the IRQ handler */
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TIM1->BDTR = TIM_BDTR_MOE;
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TIM1->CCMR1 = (6<<TIM_CCMR1_OC2M_Pos) | TIM_CCMR1_OC2PE; /* PWM Mode 1, enable CCR preload for AUX_STROBE */
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TIM1->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E;
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TIM1->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 */
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TIM1->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC4E;
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TIM1->CCR2 = TIMER_CYCLES_BEFORE_LED_STROBE;
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/* Trigger at the end of the longest bit cycle. This means this does not trigger in shorter bit cycles. */
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TIM1->CCR1 = timer_period_lookup[nbits-1] - AUX_SPI_PRETRIGGER;
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TIM1->CCR4 = timer_period_lookup[nbits-1] - ADC_PRETRIGGER;
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TIM1->DIER = TIM_DIER_CC1IE;
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TIM1->ARR = 0xffff; /* This is as large as possible since TIM1 is reset by TIM3. */
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@ -284,6 +305,7 @@ void cfg_timers_led() {
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void TIM1_CC_IRQHandler() {
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/* This handler takes about 1.5us */
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GPIOA->BSRR = GPIO_BSRR_BS_0; // Debug
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/* Set SPI baudrate to 12.5MBd for slow-ish 74HC(T)595. This is reset again in TIM3's IRQ handler.*/
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SPI1->CR1 |= (2<<SPI_CR1_BR_Pos);
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@ -312,15 +334,16 @@ void TIM1_CC_IRQHandler() {
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GPIOA->BSRR = GPIO_BSRR_BR_10;
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/* Send AUX register data */
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SPI1->DR = aux_reg | segment_map[active_segment];
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/* Kick off ADC for (oversampled) temperature measurement */
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ADC1->CR |= ADC_CR_ADSTART;
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/* Clear interrupt flag */
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TIM1->SR &= ~TIM_SR_CC1IF_Msk;
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GPIOA->BSRR = GPIO_BSRR_BR_0; // Debug
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}
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void TIM3_IRQHandler() {
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/* This handler takes about 2.1us */
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GPIOA->BSRR = GPIO_BSRR_BS_0; // Debug
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/* Reset SPI baudrate to 25MBd for fast MBI5026. Every couple of cycles, TIM1's ISR will set this to a slower value
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* for the slower AUX registers.*/
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@ -344,6 +367,8 @@ void TIM3_IRQHandler() {
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/* Clear interrupt flag */
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TIM3->SR &= ~TIM_SR_UIF_Msk;
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GPIOA->BSRR = GPIO_BSRR_BR_0; // Debug
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}
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enum Command {
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@ -476,8 +501,6 @@ void USART1_IRQHandler(void) {
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/* COBS skip counter. During payload processing this contains the remaining non-null payload bytes */
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static int cobs_count = 0;
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GPIOA->BSRR = GPIO_BSRR_BS_0; // Debug
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if (USART1->ISR & USART_ISR_ORE) { /* Overrun handling */
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overruns++;
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/* Reset and re-synchronize. Retry next frame. */
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@ -516,26 +539,30 @@ void USART1_IRQHandler(void) {
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}
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}
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}
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GPIOA->BSRR = GPIO_BSRR_BR_0; // Debug
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}
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#define ADC_OVERSAMPLING 4
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uint32_t vsense;
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void DMA1_Channel1_IRQHandler(void) {
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/* This interrupt takes either 1.2us or 13us. It can be pre-empted by the more timing-critical UART and LED timer
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* interrupts. */
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GPIOA->BSRR = GPIO_BSRR_BS_4; // Debug
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static int count = 0;
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static uint32_t adc_aggregate[2] = {0, 0};
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static int count = 0; /* oversampling accumulator sample count */
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static uint32_t adc_aggregate[2] = {0, 0}; /* oversampling accumulator */
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/* Clear the interrupt flag */
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DMA1->IFCR |= DMA_IFCR_CGIF1;
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adc_aggregate[0] += adc_buf[0];
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adc_aggregate[1] += adc_buf[1];
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if (count++ == (1<<ADC_OVERSAMPLING)) {
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/* This has been cobbled together from online tutorials and ST documentation. The datasheet is pretty poor on
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* this. */
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adc_vcc_mv = (3300 * VREFINT_CAL)/(adc_aggregate[0]>>ADC_OVERSAMPLING);
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vsense = ((adc_aggregate[1]>>ADC_OVERSAMPLING) * adc_vcc_mv)/4095 ;
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adc_temp_tenth_celsius = 300 - (((TS_CAL1*adc_vcc_mv/4095) - vsense)*100)/43;
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/* Reset oversampling state */
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count = 0;
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adc_aggregate[0] = 0;
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adc_aggregate[1] = 0;
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@ -544,29 +571,43 @@ void DMA1_Channel1_IRQHandler(void) {
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}
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void adc_config(void) {
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ADC1->CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG;
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ADC1->CFGR2 = (1<<ADC_CFGR2_CKMODE_Pos);
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ADC1->SMPR = (7<<ADC_SMPR_SMP_Pos);
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/* The ADC is used for temperature measurement. To compute the temperature from an ADC reading of the internal
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* temperature sensor, the supply voltage must also be measured. Thus we are using two channels.
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*
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* The ADC is triggered by compare channel 4 of timer 1. The trigger is set to falling edge to trigger on compare
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* match, not overflow.
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*/
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ADC1->CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | (2<<ADC_CFGR1_EXTEN_Pos) | (1<<ADC_CFGR1_EXTSEL_Pos);
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/* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */
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ADC1->CFGR2 = (2<<ADC_CFGR2_CKMODE_Pos);
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/* Use the slowest available sample rate */
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ADC1->SMPR = (7<<ADC_SMPR_SMP_Pos);
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/* Internal VCC and temperature sensor channels */
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ADC1->CHSELR = ADC_CHSELR_CHSEL16 | ADC_CHSELR_CHSEL17;
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/* Enable internal voltage reference and temperature sensor */
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ADC->CCR = ADC_CCR_TSEN | ADC_CCR_VREFEN;
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/* Perform ADC calibration */
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ADC1->CR |= ADC_CR_ADCAL;
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while (ADC1->CR & ADC_CR_ADCAL)
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;
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/* Enable ADC */
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ADC1->CR |= ADC_CR_ADEN;
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/* FIXME handle adc overrun */
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ADC1->CR |= ADC_CR_ADSTART;
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/* Configure DMA 1 Channel 1 to get rid of all the data */
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DMA1_Channel1->CPAR = (unsigned int)&ADC1->DR;
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DMA1_Channel1->CMAR = (unsigned int)&adc_buf;
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DMA1_Channel1->CNDTR = sizeof(adc_buf)/sizeof(adc_buf[0]);
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DMA1_Channel1->CCR = (0<<DMA_CCR_PL_Pos);
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DMA1_Channel1->CCR |=
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DMA_CCR_CIRC
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DMA_CCR_CIRC /* circular mode so we can leave it running indefinitely */
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| (1<<DMA_CCR_MSIZE_Pos) /* 16 bit */
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| (1<<DMA_CCR_PSIZE_Pos) /* 16 bit */
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| DMA_CCR_MINC
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| DMA_CCR_TCIE;
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DMA1_Channel1->CCR |= DMA_CCR_EN;
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| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
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DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */
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/* triggered on transfer completion. We use this to process the ADC data */
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NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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NVIC_SetPriority(DMA1_Channel1_IRQn, 3);
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}
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@ -8,6 +8,7 @@ enum {
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NROWS = 4,
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NCOLS = 8,
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MAX_BITS = 10,
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MIN_BITS = 6,
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};
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enum {
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