DMA channel assignments redone, basic protocol stuff working
This commit is contained in:
jaseg
parent
a832816d61
commit
6b40626a1b
3 changed files with 121 additions and 34 deletions
134
fw/main.c
134
fw/main.c
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@ -43,15 +43,48 @@ void strobe_leds(void) {
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GPIOA->BSRR = GPIO_BSRR_BR_9;
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}
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static volatile unsigned int sys_time = 0;
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volatile unsigned int sys_time = 0;
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volatile struct framebuf fb[2] = {0};
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volatile struct framebuf *read_fb=fb+0, *write_fb=fb+1;
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volatile int led_state = 0;
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volatile enum { FB_WRITE, FB_FORMAT, FB_UPDATE } fb_op;
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volatile uint8_t rx_buf[sizeof(struct framebuf) + 4 /* crc */];
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volatile union {
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struct {
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uint32_t millifps;
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} fps_reply;
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} tx_buf;
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volatile uint8_t this_addr = 0x05; /* FIXME */
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union {
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struct {
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uint8_t device_id __attribute__((aligned(2)));
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};
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uint16_t flash_data[0];
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} flash_data __attribute__((section ("configflash")));
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void write_config(void *target, uint16_t value) {
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FLASH->KEYR = 0x45670123;
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FLASH->KEYR = 0xCDEF89AB;
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FLASH->CR = FLASH_CR_PG;
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*(uint16_t *)target = value;
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while (FLASH->SR & FLASH_SR_BSY)
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;
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FLASH->CR = FLASH_CR_LOCK;
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}
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void erase_config() {
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FLASH->KEYR = 0x45670123;
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FLASH->KEYR = 0xCDEF89AB;
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FLASH->CR = FLASH_CR_PER;
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FLASH->AR = (uint32_t)&flash_data;
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FLASH->CR = FLASH_CR_STRT;
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while (FLASH->SR & FLASH_SR_BSY)
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;
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FLASH->CR = FLASH_CR_LOCK;
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}
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#define LED_COMM 0x0001
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#define LED_ERROR 0x0002
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#define LED_ID 0x0004
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@ -66,6 +99,10 @@ inline unsigned int stk_end(unsigned int start) {
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return (start - SysTick->VAL) & 0xffffff;
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}
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inline unsigned int stk_microseconds() {
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return sys_time*1000 + (1000 - (SysTick->VAL / (SystemCoreClock/1000000)));
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}
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enum {
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SPI_AUX,
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SPI_WORD0,
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@ -117,15 +154,16 @@ void SPI1_IRQHandler() {
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spi_state ++;
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}
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static volatile int frame_duration;
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uint8_t segment_map[8] = {5, 7, 6, 4, 1, 3, 0, 2};
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static volatile int frame_duration_us;
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/* returns new bit time in cycles */
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int shift_data() {
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static int active_segment = 0;
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static unsigned int active_bit = 0;
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static int last_frame_sys_time;
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static unsigned int last_frame_time;
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/* Note: On boot, multiplexing will start with bit 1 due to the next few lines. This is perfectly ok. */
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int rv = 1<<active_bit;
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active_bit++;
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if (active_bit == nbits) {
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active_bit = 0;
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@ -134,9 +172,9 @@ int shift_data() {
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if (active_segment == nsegments) {
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active_segment = 0;
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int time = sys_time;
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frame_duration = time - last_frame_sys_time;
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last_frame_sys_time = sys_time;
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int time = stk_microseconds();
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frame_duration_us = time - last_frame_time;
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last_frame_time = time;
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if (fb_op == FB_UPDATE) {
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volatile struct framebuf *tmp = read_fb;
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read_fb = write_fb;
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@ -149,7 +187,7 @@ int shift_data() {
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spi_state = SPI_AUX;
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SPI1->DR = (read_fb->brightness ? SR_ILED_HIGH : SR_ILED_LOW)
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| (led_state<<1)
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| (0xff00 ^ (0x100<<active_segment));
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| (0xff00 ^ (0x100<<segment_map[active_segment]));
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} else {
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spi_word = read_fb->data[active_bit*frame_size_words + active_segment];
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spi_state = SPI_WORD0;
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@ -157,7 +195,7 @@ int shift_data() {
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}
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SPI1->CR2 |= SPI_CR2_TXEIE;
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return rv;
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return 1<<active_bit;
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}
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void cfg_timer3() {
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@ -198,8 +236,16 @@ enum Command {
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CMD_SET_ADDR,
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CMD_SET_FB,
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CMD_GET_DESC,
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CMD_GET_FRAMERATE,
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CMD_ERASE_CONFIG,
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};
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enum {
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PROT_ADDR,
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PROT_CMD,
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PROT_
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} protocol_state = PROT_ADDR;
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int gaddr;
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void USART1_IRQHandler() {
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gaddr = USART1->RDR;
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@ -214,11 +260,16 @@ void USART1_IRQHandler() {
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}
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/* Are we addressed? */
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if (addr != this_addr) {
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asm("bkpt");
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/* We are not. Mute USART until next idle condition */
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USART1->RQR |= USART_RQR_MMRQ;
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} else {
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/* We are. Switch by command. */
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switch (cmd) {
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case CMD_PING:
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USART1->TDR = 42;
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USART1->RQR |= USART_RQR_MMRQ;
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break;
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case CMD_SET_FB:
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/* Are we ready to process new frame data? */
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if (fb_op != FB_WRITE) {
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@ -232,6 +283,13 @@ void USART1_IRQHandler() {
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DMA1_Channel3->CCR |= DMA_CCR_EN;
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USART1->CR3 |= USART_CR3_DMAR;
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break;
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case CMD_GET_FRAMERATE:
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tx_buf.fps_reply.millifps = frame_duration_us > 0 ? 1000000000 / frame_duration_us : 0;
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DMA1_Channel4->CNDTR = sizeof(tx_buf.fps_reply);
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USART1->ICR |= USART_ICR_TCCF; /* FIXME: (1) is this necessary? (2) where should this be done? */
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DMA1_Channel4->CCR |= DMA_CCR_EN;
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USART1->RQR |= USART_RQR_MMRQ;
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break;
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}
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}
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errout:
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@ -252,6 +310,11 @@ void DMA1_Channel2_3_IRQHandler() {
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USART1->CR1 |= USART_CR1_RXNEIE;
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}
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void DMA1_Channel4_5_IRQHandler() {
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DMA1->IFCR |= DMA_IFCR_CGIF4;
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DMA1_Channel4->CCR &= ~DMA_CCR_EN_Msk;
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}
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void uart_config(void) {
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USART1->CR1 = /* 8-bit -> M1, M0 clear */
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/* RTOIE clear */
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@ -267,16 +330,17 @@ void uart_config(void) {
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| USART_CR1_TE
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| USART_CR1_RE;
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//USART1->CR2 = USART_CR2_RTOEN; /* Timeout enable */
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USART1->CR3 = USART_CR3_DEM; /* RS485 DE enable (output on RTS) */
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USART1->CR3 = USART_CR3_DEM /* RS485 DE enable (output on RTS) */
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| USART_CR3_DMAT;
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int usartdiv = 25;
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USART1->BRR = usartdiv;
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USART1->CR1 |= USART_CR1_UE;
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/* Configure DMA for USART frame data reception */
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/* Configure DMA 1 / Channel 3 for USART frame data reception: USART1->RDR -> rx_buf */
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DMA1_Channel3->CPAR = (unsigned int)&USART1->RDR;
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DMA1_Channel3->CMAR = (unsigned int)rx_buf;
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DMA1_Channel3->CNDTR = sizeof(rx_buf);
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DMA1_Channel3->CCR = (0<<DMA_CCR_PL_Pos);
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DMA1_Channel3->CCR = (1<<DMA_CCR_PL_Pos);
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DMA1_Channel3->CCR |=
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(0<<DMA_CCR_MSIZE_Pos) /* 8 bit */
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| (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
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@ -284,20 +348,36 @@ void uart_config(void) {
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| DMA_CCR_TCIE
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| DMA_CCR_CIRC;
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DMA1_Channel4->CPAR = (unsigned int)&CRC->DR;
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DMA1_Channel4->CMAR = (unsigned int)rx_buf;
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DMA1_Channel4->CCR = (0<<DMA_CCR_PL_Pos);
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DMA1_Channel4->CCR |=
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/* Configure DMA 1 / Channel 5 for USART frame data CRC check: rx_buf -> CRC->DR */
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DMA1_Channel5->CPAR = (unsigned int)&CRC->DR;
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DMA1_Channel5->CMAR = (unsigned int)rx_buf;
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DMA1_Channel5->CCR = (0<<DMA_CCR_PL_Pos);
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DMA1_Channel5->CCR |=
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DMA_CCR_MEM2MEM /* Software trigger (precludes CIRC) */
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| DMA_CCR_DIR /* Read from memory */
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| (0<<DMA_CCR_MSIZE_Pos) /* 8 bit */
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| (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
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| DMA_CCR_MINC;
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/* Configure DMA 1 / Channel 4 for USART reply transmission */
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DMA1_Channel4->CPAR = (unsigned int)&USART1->TDR;
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DMA1_Channel4->CMAR = (unsigned int)&tx_buf;
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DMA1_Channel4->CCR = (0<<DMA_CCR_PL_Pos);
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DMA1_Channel4->CCR |=
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DMA_CCR_DIR /* Read from memory */
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| (0<<DMA_CCR_MSIZE_Pos) /* 8 bit */
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| (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
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| DMA_CCR_MINC
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| DMA_CCR_TCIE;
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SYSCFG->CFGR1 |= SYSCFG_CFGR1_USART1TX_DMA_RMP;
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NVIC_EnableIRQ(USART1_IRQn);
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NVIC_SetPriority(USART1_IRQn, 4);
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NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
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NVIC_SetPriority(DMA1_Channel2_3_IRQn, 3);
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NVIC_EnableIRQ(DMA1_Channel4_5_IRQn);
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NVIC_SetPriority(DMA1_Channel4_5_IRQn, 5);
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}
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int errcnt = 0;
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@ -313,10 +393,8 @@ int main(void) {
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RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
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SystemCoreClockUpdate();
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LL_Init1msTick(SystemCoreClock);
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_DMAEN | RCC_AHBENR_CRCEN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN | RCC_APB2ENR_USART1EN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_SYSCFGEN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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GPIOA->MODER |=
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@ -365,31 +443,27 @@ int main(void) {
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SysTick_Config(SystemCoreClock/1000); /* 1ms interval */
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uart_config();
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uint8_t i=0;
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int last_sys_time=0;
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while (42) {
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led_state = (sys_time>>8)&7;
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last_sys_time = sys_time;
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if (fb_op == FB_FORMAT) {
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CRC->CR |= CRC_CR_RESET;
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DMA1_Channel4->CNDTR = sizeof(struct framebuf);
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DMA1_Channel4->CCR |= DMA_CCR_EN;
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DMA1_Channel5->CNDTR = sizeof(struct framebuf);
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DMA1_Channel5->CCR |= DMA_CCR_EN;
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transpose_data(rx_buf, write_fb);
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while (!(DMA1->ISR & DMA_ISR_TCIF4))
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;
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DMA1->IFCR |= DMA_IFCR_CGIF4;
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DMA1_Channel4->CCR &= ~DMA_CCR_EN_Msk;
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DMA1_Channel5->CCR &= ~DMA_CCR_EN_Msk;
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if (CRC->DR != *(uint32_t *)(rx_buf+sizeof(struct framebuf))) {
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fb_op = FB_WRITE;
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errcnt++;
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} else {
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fb_op = FB_UPDATE;
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while (fb_op == FB_UPDATE)
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;
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}
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fb_op = FB_UPDATE;
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while (fb_op == FB_UPDATE)
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;
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}
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}
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}
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@ -2,7 +2,8 @@
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ENTRY(Reset_Handler)
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MEMORY {
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FLASH (rx): ORIGIN = 0x08000000, LENGTH = 16K
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FLASH (rx): ORIGIN = 0x08000000, LENGTH = 14K
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CONFIGFLASH (rw): ORIGIN = 0x08003800, LENGTH = 2K
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RAM (xrw): ORIGIN = 0x20000000, LENGTH = 4K
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}
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@ -31,12 +32,18 @@ SECTIONS {
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/* Necessary KEEP sections (see http://sourceware.org/ml/newlib/2005/msg00255.html) */
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .;
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/* This is used by the startup in order to initialize the .data section */
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_sidata = _etext;
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} >FLASH
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.configflash : {
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. = ALIGN(2048);
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*(.configdata)
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_econfig = .;
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} >CONFIGFLASH
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/* This is the initialized data section
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The program executes knowing that the data is in the RAM
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@ -4,6 +4,12 @@
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#include "transpose.h"
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uint8_t digit_map[33] = {
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0, 1, 2, 3, 28,29,30,31,
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4, 5, 6, 7, 24,25,26,27,
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8, 9,10,11, 20,21,22,23,
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12,13,14,15, 16,17,18,19
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};
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void transpose_data(volatile uint8_t *rx_buf, volatile struct framebuf *out_fb) {
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memset((uint8_t *)out_fb, 0, sizeof(*out_fb));
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struct data_format *rxp = (struct data_format *)rx_buf;
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@ -15,7 +21,7 @@ void transpose_data(volatile uint8_t *rx_buf, volatile struct framebuf *out_fb)
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uint32_t acc = 0;
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uint8_t *inp = start_inp++;
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for (int digit=0; digit<32; digit++) {
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acc |= (*inp & bit_mask) >> bit << digit;
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acc |= (*inp & bit_mask) >> bit << digit_map[digit];
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inp += sizeof(struct data_format);
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}
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*outp = acc;
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@ -28,7 +34,7 @@ void transpose_data(volatile uint8_t *rx_buf, volatile struct framebuf *out_fb)
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uint32_t mask = 1 << bit << (seg*2);
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uint32_t acc = 0;
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for (int digit=0; digit<32; digit++) {
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acc |= (*inp & mask) >> bit >> seg << digit;
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acc |= (*inp & mask) >> bit >> (seg*2) << digit_map[digit];
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inp += sizeof(struct data_format)/sizeof(uint16_t);
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}
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frame_data[seg] = acc;
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