fw working commit
This commit is contained in:
jaseg
parent
4dbd135d68
commit
84de029e74
8 changed files with 802 additions and 0 deletions
60
fw/Makefile
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60
fw/Makefile
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# put your *.o targets here, make should handle the rest!
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CMSIS_PATH ?= STM32Cube/Drivers/CMSIS
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CMSIS_DEV_PATH ?= $(CMSIS_PATH)/Device/ST/STM32F0xx
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HAL_PATH ?= STM32Cube/Drivers/STM32F0xx_HAL_Driver
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CC := arm-none-eabi-gcc
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LD := arm-none-eabi-ld
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OBJCOPY := arm-none-eabi-objcopy
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OBJDUMP := arm-none-eabi-objdump
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SIZE := arm-none-eabi-size
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CFLAGS = -Wall -std=gnu11 -Os -fdump-rtl-expand
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CFLAGS += -mlittle-endian -mcpu=cortex-m0 -march=armv6-m -mthumb
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CFLAGS += -ffunction-sections -fdata-sections
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LDFLAGS = -nostartfiles
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#LDFLAGS += -specs=rdimon.specs -DSEMIHOSTING
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LDFLAGS += -Wl,-Map=main.map -nostdlib
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LDFLAGS += -Wl,--gc-sections
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LIBS = -lgcc
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#LIBS += -lrdimon
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# Technically we're using an STM32F030F4, but apart from the TSSOP20 package that one is largely identical to the
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# STM32F030*6 and there is no separate device header provided for it, so we're faking a *6 device here. This is
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# even documented in stm32f0xx.h. Thanks ST!
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CFLAGS += -DSTM32F030x6
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LDFLAGS += -Tstm32_flash.ld
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CFLAGS += -I$(CMSIS_DEV_PATH)/Include -I$(CMSIS_PATH)/Include -I$(HAL_PATH)/Inc -Iconfig
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LDFLAGS += -L$(CMSIS_PATH)/Lib/GCC -larm_cortexM0l_math
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###################################################
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.PHONY: program clean
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all: main.elf main.pdf
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%.o: %.c
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$(CC) -c $(CFLAGS) -o $@ $^
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%.o: %.s
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$(CC) -c $(CFLAGS) -o $@ $^
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%.dot: %.elf
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r2 -a arm -qc 'aa;agC' $< 2>/dev/null >$@
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main.elf: main.o startup_stm32f030x6.o system_stm32f0xx.o $(HAL_PATH)/Src/stm32f0xx_ll_utils.o base.o semihosting.o
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$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS)
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$(OBJCOPY) -O ihex $@ $(@:.elf=.hex)
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$(OBJCOPY) -O binary $@ $(@:.elf=.bin)
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$(OBJDUMP) -St $@ >$(@:.elf=.lst)
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$(SIZE) $@
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program: main.elf openocd.cfg
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openocd -f openocd.cfg -c "program $< verify reset exit"
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clean:
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rm -f **.o
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rm -f main.elf main.hex main.bin main.map main.lst
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rm -f **.expand
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20
fw/base.c
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20
fw/base.c
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@ -0,0 +1,20 @@
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#include <unistd.h>
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int __errno = 0;
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void *_impure_ptr = NULL;
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void __sinit(void) {
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}
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void memset(void *s, int c, size_t n) {
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char *end = (char *)s + n;
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for (char *p = (char *)s; p < end; p++)
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*p = (char)c;
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}
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size_t strlen(const char *s) {
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const char *start = s;
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while (*s++);
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return s - start - 1;
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}
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98
fw/main.c
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98
fw/main.c
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@ -0,0 +1,98 @@
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#include <stm32f0xx.h>
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#include <stdint.h>
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#include <system_stm32f0xx.h>
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#include <stm32f0xx_ll_utils.h>
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#include <string.h>
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#include <unistd.h>
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/*
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* Part number: STM32F030F4C6
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*/
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void tick(void) {
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for(int i=0; i<50; i++)
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__asm__("nop");
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}
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int main(void) {
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR&RCC_CR_HSERDY));
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RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk;
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RCC->CFGR |= (2<<RCC_CFGR_PLLMUL_Pos) | RCC_CFGR_PLLSRC_HSE_PREDIV; /* PLL x4 */
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RCC->CFGR2 &= ~RCC_CFGR2_PREDIV_Msk; /* PREDIV=0 */
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR&RCC_CR_PLLRDY));
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RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
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SystemCoreClockUpdate();
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LL_Init1msTick(SystemCoreClock);
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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GPIOA->MODER |=
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(2<<GPIO_MODER_MODER5_Pos) /* PA5 - SCLK */
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| (2<<GPIO_MODER_MODER7_Pos) /* PA7 - MOSI */
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| (1<<GPIO_MODER_MODER9_Pos) /* PA9 - LED strobe */
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| (1<<GPIO_MODER_MODER10_Pos);/* PA10 - Auxiliary strobe */
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/* Set shift register IO GPIO output speed */
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GPIOA->OSPEEDR |=
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(3<<GPIO_OSPEEDR_OSPEEDR5_Pos) /* SCLK */
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| (3<<GPIO_OSPEEDR_OSPEEDR7_Pos) /* MOSI */
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| (3<<GPIO_OSPEEDR_OSPEEDR9_Pos) /* LED strobe */
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| (3<<GPIO_OSPEEDR_OSPEEDR10_Pos); /* Auxiliary strobe */
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GPIOA->AFR[0] |=
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(0<<GPIO_AFRL_AFRL5_Pos) /* SPI1_SCK */
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| (0<<GPIO_AFRL_AFRL7_Pos); /* SPI1_MOSI */
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/* Configure SPI controller */
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SPI1->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (7<<SPI_CR1_BR_Pos) | SPI_CR1_MSTR;
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SPI1->CR2 = (7<<SPI_CR2_DS_Pos);
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int pos1 = 0;
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int pos2 = 0;
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while (42) {
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for (int i=0; i<6; i++) {
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if (pos1 == i) {
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SPI1->DR = 1<<pos2;
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} else {
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SPI1->DR = 0;
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}
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while (SPI1->SR & SPI_SR_BSY);
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tick();
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}
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pos2 += 1;
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if (pos2 == 8) {
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pos2 = 0;
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pos1 += 1;
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if (pos1 == 6)
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pos1 = 0;
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}
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/* Strobe both LED drivers and aux regs */
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GPIOA->BSRR = GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10;
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tick();
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GPIOA->BSRR = GPIO_BSRR_BR_9 | GPIO_BSRR_BR_10;
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LL_mDelay(1);
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}
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}
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void NMI_Handler(void) {
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}
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void HardFault_Handler(void) {
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for(;;);
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}
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void SVC_Handler(void) {
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}
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void PendSV_Handler(void) {
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}
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void SysTick_Handler(void) {
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}
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129
fw/mapparse.py
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129
fw/mapparse.py
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@ -0,0 +1,129 @@
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import re
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from collections import defaultdict, namedtuple
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Section = namedtuple('Section', ['name', 'offset', 'objects'])
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ObjectEntry = namedtuple('ObjectEntry', ['filename', 'object', 'offset', 'size'])
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FileEntry = namedtuple('FileEntry', ['section', 'object', 'offset', 'length'])
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class Memory:
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def __init__(self, name, origin, length, attrs=''):
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self.name, self.origin, self.length, self.attrs = name, origin, length, attrs
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self.sections = {}
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self.files = defaultdict(lambda: [])
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self.totals = defaultdict(lambda: 0)
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def add_toplevel(self, name, offx, length):
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self.sections[name] = Section(offx, length, [])
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def add_obj(self, name, offx, length, fn, obj):
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base_section, sep, subsec = name[1:].partition('.')
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base_section = '.'+base_section
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if base_section in self.sections:
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sec = secname, secoffx, secobjs = self.sections[base_section]
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secobjs.append(ObjectEntry(fn, obj, offx, length))
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else:
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sec = None
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self.files[fn].append(FileEntry(sec, obj, offx, length))
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self.totals[fn] += length
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class MapFile:
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def __init__(self, s):
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self._lines = s.splitlines()
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self.memcfg = {}
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self.defaultmem = Memory('default', 0, 0xffffffffffffffff)
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self._parse()
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def __getitem__(self, offx_or_name):
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''' Lookup a memory area by name or address '''
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if offx_or_name in self.memcfg:
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return self.memcfg[offx_or_name]
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elif isinstance(offx_or_name, int):
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for mem in self.memcfg.values():
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if mem.origin <= offx_or_name < mem.origin+mem.length:
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return mem
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else:
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return self.defaultmem
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raise ValueError('Invalid argument type for indexing')
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def _skip(self, regex):
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matcher = re.compile(regex)
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for l in self:
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if matcher.match(l):
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break
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def __iter__(self):
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while self._lines:
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yield self._lines.pop(0)
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def _parse(self):
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self._skip('^Memory Configuration')
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# Parse memory segmentation info
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self._skip('^Name')
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for l in self:
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if not l:
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break
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name, origin, length, *attrs = l.split()
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if not name.startswith('*'):
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self.memcfg[name] = Memory(name, int(origin, 16), int(length, 16), attrs[0] if attrs else '')
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# Parse section information
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toplevel_m = re.compile('^(\.[a-zA-Z0-9_.]+)\s+(0x[0-9a-fA-F]+)\s+(0x[0-9a-fA-F]+)')
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secondlevel_m = re.compile('^ (\.[a-zA-Z0-9_.]+)\s+(0x[0-9a-fA-F]+)\s+(0x[0-9a-fA-F]+)\s+(.*)$')
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secondlevel_linebreak_m = re.compile('^ (\.[a-zA-Z0-9_.]+)\n')
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filelike = re.compile('^(/?[^()]*\.[a-zA-Z0-9-_]+)(\(.*\))?')
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linebreak_section = None
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for l in self:
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# Toplevel section
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match = toplevel_m.match(l)
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if match:
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name, offx, length = match.groups()
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offx, length = int(offx, 16), int(length, 16)
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self[offx].add_toplevel(name, offx, length)
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match = secondlevel_linebreak_m.match(l)
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if match:
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linebreak_section, = match.groups()
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continue
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if linebreak_section:
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l = ' {} {}'.format(linebreak_section, l)
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linebreak_section = None
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# Second-level section
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match = secondlevel_m.match(l)
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if match:
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name, offx, length, misc = match.groups()
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match = filelike.match(misc)
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if match:
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fn, obj = match.groups()
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obj = obj.strip('()') if obj else None
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offx, length = int(offx, 16), int(length, 16)
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self[offx].add_obj(name, offx, length, fn, obj)
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if __name__ == '__main__':
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import argparse
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parser = argparse.ArgumentParser(description='Parser GCC map file')
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parser.add_argument('mapfile', type=argparse.FileType('r'), help='The GCC .map file to parse')
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parser.add_argument('-m', '--memory', type=str, help='The memory segments to print, comma-separated')
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args = parser.parse_args()
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mf = MapFile(args.mapfile.read())
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args.mapfile.close()
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mems = args.memory.split(',') if args.memory else mf.memcfg.keys()
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for name in mems:
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mem = mf.memcfg[name]
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print('Symbols by file for memory', name)
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for tot, fn in reversed(sorted( (tot, fn) for fn, tot in mem.totals.items() )):
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print(' {:>8} {}'.format(tot, fn))
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for length, offx, sec, obj in reversed(sorted(( (length, offx, sec, obj) for sec, obj, offx, length in
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mem.files[fn] ), key=lambda e: e[0] )):
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name = sec.name if sec else None
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print(' {:>8} {:>#08x} {}'.format(length, offx, obj))
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#print('{:>16} 0x{:016x} 0x{:016x} ({:>24}) {}'.format(name, origin, length, length, attrs))
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25
fw/mapvis.py
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25
fw/mapvis.py
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#!/usr/bin/env python3
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from matplotlib import pyplot as plt
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f, ax = plt.subplots(1, figsize=(3, 8))
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bar_width = 1
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ax.bar([-bar_width/2], top, bottom=bottom, width=bar_width, label='foo')
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ax.set_xticks([0], [filename])
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ax.set_ylabel('Memory usage (B)')
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ax.set_xlabel('')
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ax.set_xlim([-bar_width/2, bar_width/2])
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ax.set_ylim([0, mem_max])
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if __name__ == '__main__':
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import argparse
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import mapparse
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parser = argparse.ArgumentParser(description='Visualize program memory usage using GCC map file')
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parser.add_argument('mapfile', type=argparse.FileType('r'), description='Input GCC .map file')
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args = parser.parse_args()
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mapping = mapparse.MapFile(args.mapfile.read())
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mapping.
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10
fw/semihosting.c
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10
fw/semihosting.c
Normal file
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#define SYS_WRITE0 0x04
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void write0(const char *c) __attribute__((naked));
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void write0(const char *c) {
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__asm__("mov r1, %0" : : "r" (c));
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__asm__("mov r0, %0" : : "I" (SYS_WRITE0));
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__asm__("bkpt 0xab");
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__asm__("bx lr");
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}
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124
fw/stm32_flash.ld
Normal file
124
fw/stm32_flash.ld
Normal file
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@ -0,0 +1,124 @@
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ENTRY(Reset_Handler)
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MEMORY {
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FLASH (rx): ORIGIN = 0x08000000, LENGTH = 16K
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RAM (xrw): ORIGIN = 0x20000000, LENGTH = 4K
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}
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/* highest address of the user mode stack */
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_estack = 0x20001000;
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SECTIONS {
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/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
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.isr_vector : {
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. = ALIGN(4);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} >FLASH
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/* the program code is stored in the .text section, which goes to Flash */
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.text : {
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. = ALIGN(4);
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*(.text) /* normal code */
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*(.text.*) /* -ffunction-sections code */
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*(.rodata) /* read-only data (constants) */
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*(.rodata*) /* -fdata-sections read only data */
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*(.glue_7) /* TBD - needed ? */
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*(.glue_7t) /* TBD - needed ? */
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/* Necessary KEEP sections (see http://sourceware.org/ml/newlib/2005/msg00255.html) */
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .;
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/* This is used by the startup in order to initialize the .data section */
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_sidata = _etext;
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} >FLASH
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/* This is the initialized data section
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The program executes knowing that the data is in the RAM
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but the loader puts the initial values in the FLASH (inidata).
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It is one task of the startup to copy the initial values from FLASH to RAM. */
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.data : AT ( _sidata ) {
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_sdata = . ;
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_data = . ;
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*(.data)
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*(.data.*)
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*(.RAMtext)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_edata = . ;
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} >RAM
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/* This is the uninitialized data section */
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.bss : {
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
|
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_sbss = .;
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_bss = .;
|
||||
|
||||
*(.bss)
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*(.bss.*) /* patched by elias - allows the use of -fdata-sections */
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*(COMMON)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_ebss = . ;
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} >RAM
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||||
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||||
PROVIDE ( end = _ebss);
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PROVIDE (_end = _ebss);
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|
||||
__exidx_start = .;
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__exidx_end = .;
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||||
|
||||
/* after that it's only debugging information. */
|
||||
|
||||
/* remove the debugging information from the standard libraries */
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||||
/* /DISCARD/ : {
|
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libc.a ( * )
|
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libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}*/
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
336
fw/system_stm32f0xx.c
Normal file
336
fw/system_stm32f0xx.c
Normal file
|
|
@ -0,0 +1,336 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f0xx.c
|
||||
* copied from: STM32Cube/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.1
|
||||
* @date 04-November-2016
|
||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f0xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* Supported STM32F0xx device
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | HSI
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 8000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 8000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f0xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
|
||||
This value can be provided and adapted by the user application. */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
|
||||
This value can be provided and adapted by the user application. */
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
#if !defined (HSI48_VALUE)
|
||||
#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
|
||||
This value can be provided and adapted by the user application. */
|
||||
#endif /* HSI48_VALUE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock there is no need to
|
||||
call the 2 first functions listed above, since SystemCoreClock variable is
|
||||
updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 8000000;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001U;
|
||||
|
||||
#if defined (STM32F051x8) || defined (STM32F058x8)
|
||||
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
|
||||
RCC->CFGR &= (uint32_t)0xF8FFB80CU;
|
||||
#else
|
||||
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
|
||||
RCC->CFGR &= (uint32_t)0x08FFB80CU;
|
||||
#endif /* STM32F051x8 or STM32F058x8 */
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFFU;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFFU;
|
||||
|
||||
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
|
||||
RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
|
||||
|
||||
/* Reset PREDIV[3:0] bits */
|
||||
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
|
||||
|
||||
#if defined (STM32F072xB) || defined (STM32F078xx)
|
||||
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
|
||||
#elif defined (STM32F071xB)
|
||||
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
|
||||
#elif defined (STM32F091xC) || defined (STM32F098xx)
|
||||
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
|
||||
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
|
||||
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
|
||||
#elif defined (STM32F051x8) || defined (STM32F058xx)
|
||||
/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
|
||||
#elif defined (STM32F042x6) || defined (STM32F048xx)
|
||||
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
|
||||
#elif defined (STM32F070x6) || defined (STM32F070xB)
|
||||
/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
|
||||
/* Set default USB clock to PLLCLK, since there is no HSI48 */
|
||||
RCC->CFGR3 |= (uint32_t)0x00000080U;
|
||||
#else
|
||||
#warning "No target selected"
|
||||
#endif
|
||||
|
||||
/* Reset HSI14 bit */
|
||||
RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000U;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
|
||||
* 8 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
|
||||
|
||||
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
|
||||
{
|
||||
/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
|
||||
SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
|
||||
}
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
|
||||
else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
|
||||
{
|
||||
/* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
|
||||
SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
|
||||
}
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
|
||||
else
|
||||
{
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
|
||||
|| defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
|
||||
|| defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
|
||||
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
|
||||
#else
|
||||
/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
|
||||
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
|
||||
STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
}
|
||||
break;
|
||||
default: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency ----------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue