jaseg
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a1eff91d77
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Basic UART working, but too slow
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2017-12-08 19:25:11 +01:00 |
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jaseg
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723995c541
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hw v0.4
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2017-09-18 11:30:25 +02:00 |
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jaseg
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a823484163
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Fix up RS485/digital power label
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2017-09-06 14:36:50 +02:00 |
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jaseg
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d4d0f850f0
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Fix up version label and one ground trace
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2017-09-06 14:30:43 +02:00 |
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jaseg
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febcb5a933
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Fixes for second prototype (v0.3)
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2017-09-06 14:03:07 +02:00 |
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jaseg
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9b52622eab
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Temperature/VCC ADC working
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2017-09-02 12:23:39 +02:00 |
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jaseg
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446dbe6412
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Now with working source extraction from firmware
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2017-09-01 20:52:34 +02:00 |
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jaseg
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5a19ab0e84
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Add missing files
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2017-09-01 20:32:15 +02:00 |
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jaseg
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e6437f975b
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UART magic seems to be working now
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2017-09-01 20:26:05 +02:00 |
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jaseg
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6b40626a1b
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DMA channel assignments redone, basic protocol stuff working
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2017-09-01 15:44:39 +02:00 |
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jaseg
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a832816d61
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Serial protocol now working including CRC
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2017-08-24 00:52:18 +02:00 |
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jaseg
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570f527a3a
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Interrupt-driven SPI1 fundamentally working
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2017-08-23 14:11:45 +02:00 |
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jaseg
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dbb03cbece
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Comms working except for TIM3/SPI1 race
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2017-08-23 13:00:07 +02:00 |
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jaseg
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abdf02426f
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Add cmsis export generator
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2017-08-23 10:50:43 +02:00 |
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jaseg
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95e1a03648
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Add transpose test
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2017-08-23 10:50:16 +02:00 |
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jaseg
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e9f79a2e99
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Add profiling script
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2017-08-22 20:13:10 +02:00 |
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jaseg
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a18b197ac4
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Benchmark code
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2017-08-15 15:57:33 +02:00 |
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jaseg
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9eb92caa6c
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working commit
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2017-08-15 14:34:34 +02:00 |
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jaseg
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952f3c03ac
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Temporary for bit shuffling
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2017-08-15 10:34:57 +02:00 |
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jaseg
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71ad806c88
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Working on uart code
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2017-08-15 10:30:35 +02:00 |
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jaseg
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369c090955
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Multiplexing is working
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2017-08-14 12:51:49 +02:00 |
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jaseg
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7a5791e976
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Board rev 0.3 working
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2017-08-13 15:48:48 +02:00 |
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jaseg
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1ae37bce5b
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Second production run, v0.3
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2017-07-21 20:01:20 +02:00 |
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jaseg
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5bb67efb4a
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Final silk art positioning
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2017-07-21 01:00:43 +02:00 |
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jaseg
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2775e1fc61
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Add missing firmware build files
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2017-07-20 16:06:33 +02:00 |
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jaseg
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16328e9723
|
Second board revision
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2017-07-20 16:05:07 +02:00 |
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jaseg
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6ec97df9de
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Schematic fixed up so far
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2017-07-15 22:43:04 +02:00 |
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jaseg
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6f12a41cc6
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Add resistor calculation script
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2017-06-12 13:03:18 +02:00 |
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jaseg
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6301aad169
|
Test program working
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2017-06-11 21:30:02 +02:00 |
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jaseg
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84de029e74
|
fw working commit
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2017-06-10 19:14:18 +02:00 |
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jaseg
|
4dbd135d68
|
foo
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2017-06-10 19:13:42 +02:00 |
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jaseg
|
0f52be1e7a
|
Release v0.2
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2017-05-17 11:25:17 +02:00 |
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jaseg
|
7d34875369
|
Design mostly done
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2017-05-04 13:47:53 +02:00 |
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jaseg
|
91f22c5435
|
Layout mostly done
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2017-05-02 16:05:05 +02:00 |
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jaseg
|
cb2ca6e9c9
|
Foo
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2017-04-30 15:58:28 +02:00 |
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jaseg
|
cdc0c4fa07
|
Pre safety fixup
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2017-04-29 20:56:06 +02:00 |
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jaseg
|
b5bf5670b6
|
Added protection stuff
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2017-04-28 21:29:58 +02:00 |
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jaseg
|
9af9f5768b
|
Initial commit
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2017-04-26 11:57:45 +02:00 |
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