Commit graph

31 commits

Author SHA1 Message Date
jaseg
f7fbcb0016 Add makefile, update mech foo 2020-10-29 12:21:31 +01:00
jaseg
f977fc4f66 tech-report: update bibliography 2020-10-27 23:52:13 +01:00
jaseg
16d5cd27c9 Update tech report 2020-10-27 16:19:05 +01:00
jaseg
1530b958c3 update tech report 2020-10-22 23:06:54 +02:00
jaseg
db20782ff9 Fix up freecad model and add gerber export 2020-10-14 13:28:44 +02:00
jaseg
42dd46be06 Fix up ALL the edge connectors 2020-10-13 18:58:05 +02:00
jaseg
ec656022ae Export bearing mount gerbers 2020-10-13 14:22:48 +02:00
jaseg
e42427fd1e Export raspi holder vertical strut pcb 2020-10-13 14:20:56 +02:00
jaseg
c43fba7aa6 Export stator top PCB 2020-10-13 14:14:36 +02:00
jaseg
f22ae506a8 Update footprint library tables 2020-10-13 14:09:44 +02:00
jaseg
f7d5209ad8 finish stator base pcb 2020-10-13 14:05:05 +02:00
jaseg
ee98b3b218 Rotor base pcb: add debug connector 2020-10-13 13:19:13 +02:00
jaseg
35ea3e2299 Push new edge connector board outline to rotor base 2020-10-13 12:19:05 +02:00
jaseg
3766779cb8 rotor base dbg connect WIP 2020-10-13 12:12:33 +02:00
jaseg
426bca9ac3 Fix rotor_base NRST and testpoint situation 2020-10-13 11:31:13 +02:00
jaseg
872ac8e309 Add meshes to PCBs 2020-10-09 18:06:31 +02:00
jaseg
cf913a1eab Layout more board, add proto areas to rotor base 2020-10-09 15:10:46 +02:00
jaseg
7c2ac33a89 Merge remote-tracking branch 'wendelstein/master' 2020-10-08 19:40:19 +02:00
jaseg
3f96477311 Route rotor base PCB 2020-10-08 19:33:59 +02:00
jaseg
c0c2d91a9f TCC scenario performance: WIP 2020-10-08 13:13:40 +02:00
jaseg
e387d4eeca Merge HW dev and orga repos 2020-10-07 11:47:06 +02:00
jaseg
65400d123e Add missing docs 2020-10-07 10:02:24 +02:00
jaseg
5de91842ed base schematic done, PCB WIP 2020-10-02 13:29:56 +02:00
jaseg
e246e55c7a schematic WIP 2020-10-02 09:28:56 +02:00
jaseg
e5b62db5e8 Add images, translate FC -> KiCAD 2020-10-01 12:36:05 +02:00
jaseg
91fa7d5f63 Initial FC mech -> KiCAD PCB edge export 2020-09-30 14:15:23 +02:00
jaseg
1432efc06d Initial commit 2020-09-30 13:59:10 +02:00
jaseg
869a304aad Finish first rough draft 2020-09-18 12:59:08 +02:00
jaseg
b3a6b004be Add prior art and engineering constraints 2020-09-18 11:14:26 +02:00
jaseg
704bdcfe3b Add contributions section 2020-09-17 13:08:19 +02:00
jaseg
5af08604d7 Initial commit 2020-09-16 13:08:38 +02:00