Commit graph

29 commits

Author SHA1 Message Date
jaseg
6b40626a1b DMA channel assignments redone, basic protocol stuff working 2017-09-01 15:44:39 +02:00
jaseg
a832816d61 Serial protocol now working including CRC 2017-08-24 00:52:18 +02:00
jaseg
570f527a3a Interrupt-driven SPI1 fundamentally working 2017-08-23 14:11:45 +02:00
jaseg
dbb03cbece Comms working except for TIM3/SPI1 race 2017-08-23 13:00:07 +02:00
jaseg
abdf02426f Add cmsis export generator 2017-08-23 10:50:43 +02:00
jaseg
95e1a03648 Add transpose test 2017-08-23 10:50:16 +02:00
jaseg
e9f79a2e99 Add profiling script 2017-08-22 20:13:10 +02:00
jaseg
a18b197ac4 Benchmark code 2017-08-15 15:57:33 +02:00
jaseg
9eb92caa6c working commit 2017-08-15 14:34:34 +02:00
jaseg
952f3c03ac Temporary for bit shuffling 2017-08-15 10:34:57 +02:00
jaseg
71ad806c88 Working on uart code 2017-08-15 10:30:35 +02:00
jaseg
369c090955 Multiplexing is working 2017-08-14 12:51:49 +02:00
jaseg
7a5791e976 Board rev 0.3 working 2017-08-13 15:48:48 +02:00
jaseg
1ae37bce5b Second production run, v0.3 2017-07-21 20:01:20 +02:00
jaseg
5bb67efb4a Final silk art positioning 2017-07-21 01:00:43 +02:00
jaseg
2775e1fc61 Add missing firmware build files 2017-07-20 16:06:33 +02:00
jaseg
16328e9723 Second board revision 2017-07-20 16:05:07 +02:00
jaseg
6ec97df9de Schematic fixed up so far 2017-07-15 22:43:04 +02:00
jaseg
6f12a41cc6 Add resistor calculation script 2017-06-12 13:03:18 +02:00
jaseg
6301aad169 Test program working 2017-06-11 21:30:02 +02:00
jaseg
84de029e74 fw working commit 2017-06-10 19:14:18 +02:00
jaseg
4dbd135d68 foo 2017-06-10 19:13:42 +02:00
jaseg
0f52be1e7a Release v0.2 2017-05-17 11:25:17 +02:00
jaseg
7d34875369 Design mostly done 2017-05-04 13:47:53 +02:00
jaseg
91f22c5435 Layout mostly done 2017-05-02 16:05:05 +02:00
jaseg
cb2ca6e9c9 Foo 2017-04-30 15:58:28 +02:00
jaseg
cdc0c4fa07 Pre safety fixup 2017-04-29 20:56:06 +02:00
jaseg
b5bf5670b6 Added protection stuff 2017-04-28 21:29:58 +02:00
jaseg
9af9f5768b Initial commit 2017-04-26 11:57:45 +02:00