Commit graph

219 commits

Author SHA1 Message Date
jaseg
20446874b6 Update spectral analysis, increase test fw gen frequency 2025-04-03 17:06:55 +02:00
jaseg
95a68e62bd Update trace plot alignment 2025-04-03 17:04:35 +02:00
jaseg
b5f685e308 Add new spectrum measurements 2025-04-03 11:16:11 +02:00
jaseg
7dd66b86b3 Fix legends not showing up in some plots 2025-04-02 19:58:30 +02:00
jaseg
f335d96c4f Enable spectrum measurement mode
Revert "Undo temporary spectrum measurement changes"

This reverts commit a2d95a324a.
2025-04-02 19:52:57 +02:00
jaseg
5e45553d5a Add speed of light calculation 2025-04-02 19:04:37 +02:00
jaseg
d11dd4c9ba Run exports 2025-04-02 17:47:13 +02:00
jaseg
2974c6f250 Add mesh length calculation and visualization tool 2025-04-02 17:46:46 +02:00
jaseg
e8e0b976e6 Fix javascript data corruption issue and re-do manipulation measurements 2025-04-02 17:41:12 +02:00
jaseg
e25522b24e Add new manipulation experiments 2025-04-02 16:37:35 +02:00
jaseg
41befda8ee Fix 74LVC length plot offset 2025-04-02 14:20:40 +02:00
jaseg
1aa8b035ac Re-do length measurements with cliplines 2025-04-02 14:16:21 +02:00
jaseg
bb5d784299 Paper WIP 2025-03-31 18:26:44 +02:00
jaseg
e78319c20f Paper WIP 2025-03-31 16:58:56 +02:00
jaseg
f87fc2668b Update probe plot 2025-03-31 14:47:20 +02:00
jaseg
35f3b70249 Improve probe shape plots 2025-03-31 14:47:20 +02:00
jaseg
4603e55dc1 Paper WIP 2025-03-31 14:19:24 +02:00
jaseg
b120545558 Add more plots 2025-03-28 18:37:56 +01:00
jaseg
0b0ae3691a Update paper 2025-03-28 15:37:19 +01:00
jaseg
34749fbeaf Update risetime plots with thresholds 2025-03-28 12:53:22 +01:00
jaseg
c583a88e82 Add exported risetime graph 2025-03-28 12:49:10 +01:00
jaseg
059f1d9348 Improve plots 2025-03-27 19:56:53 +01:00
jaseg
503d224234 Add risetime notebook 2025-03-27 19:09:02 +01:00
jaseg
98a5629e7e Add repeated measurements for broken board and for risetime tuning 2025-03-27 19:08:41 +01:00
jaseg
7c9ab078b2 Add capture data for all chips except ONET 2025-03-27 17:52:58 +01:00
jaseg
919d018641 Fix build 2025-03-11 20:07:25 +01:00
jaseg
a8e9e325f7 Paper WIP 2025-03-11 20:06:43 +01:00
jaseg
f27afeecbb paper: Text on mesh related work and circuit design 2025-03-10 20:41:34 +01:00
jaseg
d0bab63ec0 Paper WIP 2025-03-10 17:37:34 +01:00
jaseg
2703e67004 fw: Fix aliasing issue, improve web IF 2025-02-07 18:18:07 +01:00
jaseg
d5ab91648d Update fw/interface to add variance data 2025-02-07 12:56:00 +01:00
jaseg
a2d95a324a Undo temporary spectrum measurement changes 2025-02-07 11:45:06 +01:00
jaseg
3f9a52e1b0 Add second risetime calculation 2025-01-29 16:28:07 +01:00
jaseg
b4aa5db722 Finished preliminary bandwidth analysis. 2025-01-29 16:20:51 +01:00
jaseg
fef6b17aed Initial analysis of measurements 2025-01-29 12:47:42 +01:00
jaseg
15cd939e9c Add spectrum measurement results 2025-01-29 11:50:21 +01:00
jaseg
0805760010 Add input clamping diodes 2025-01-28 15:37:13 +01:00
jaseg
3c54e54e5c Paper WIP 2025-01-15 09:54:42 +01:00
jaseg
992b4dc434 Paper WIP 2024-12-14 22:19:57 +01:00
jaseg
e09904ce16 Add paper scaffold 2024-12-11 18:01:54 +01:00
jaseg
aa4839aed3 Make oversampling configurable 2024-12-02 16:39:55 +01:00
jaseg
65a626f6c8 Properly tuned double-edge sampling 2024-12-02 14:20:58 +01:00
jaseg
440922f10c re-enable oversampling 2024-11-26 17:20:42 +01:00
jaseg
e2a074c114 It's roughly doing what it's supposed to do now.
We have mystery oscillations.
2024-11-26 16:45:11 +01:00
jaseg
78a0e8ae31 WIP 2024-11-26 16:34:37 +01:00
jaseg
c229fbdde8 make sampling phase and width remotely configurable 2024-11-25 21:31:42 +01:00
jaseg
3fce64ae3e Extend remote control both ways 2024-11-25 20:56:27 +01:00
jaseg
7fb1311a85 Something weird is happening with the hrtim master period
This new value gives much cleaner curves. I suspect that either we have
some issue with ADC sampling not being precise due to clock domain
crossings, or this is just interference and the new period hits a sweet
spot that is coherent with this interference.
2024-11-23 15:21:34 +01:00
jaseg
1f37d9221b Decrease oversampling to increase update rate 2024-11-23 14:29:55 +01:00
jaseg
b32c4d9d61 Move stimulus instead of sampling pulse, eliminates ADC alignment issue
The ADC can only trigger on whole clock pulses, so when we move the
sampling pulse in fractional increments, the relative alignment of the
ADC's sampling phase w.r.t. sampling pulse moves around +/-0.5 clock
periods. Since our opamps ring a bit, that leads to an artifact in the
measurements with a period of 32 samples (one whole clock pulse). Moving
the stimulus pulse instead fixes this issue, as now the alignment
between the sampling pulse and the ADC's sampling is constant.
2024-11-23 14:24:09 +01:00