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Something weird is happening with the hrtim master period

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This new value gives much cleaner curves. I suspect that either we have
some issue with ADC sampling not being precise due to clock domain
crossings, or this is just interference and the new period hits a sweet
spot that is coherent with this interference.
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jaseg 2024-11-23 15:21:34 +01:00
parent 1f37d9221b
commit 7fb1311a85
1 changed files with 1 additions and 1 deletions
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2
fw/src/main.c
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@ -209,7 +209,7 @@ int main(void) {
DAC2->DHR12R1 = 0xfff; /* VBIAS_DAC */
HRTIM1->sMasterRegs.MCR = HRTIM_MCR_CONT;
HRTIM1->sMasterRegs.MPER = 168 * 0x20; /* We have to translate all counter values to the 32x oversampled high-resolution clock */
HRTIM1->sMasterRegs.MPER = 180 * 0x20; /* We have to translate all counter values to the 32x oversampled high-resolution clock */
/* The master period should now be 168 HRTIM bus clock cycles, which at 168 MHz corresponds to 1.00 µs.
* Note that the HRTIM doc is very unclear if we should set the register to 168 or 167 for that, let's just see.
*/