Commit graph

29 commits

Author SHA1 Message Date
jaseg
f564294fd2 Add initial driver schematic draft 2019-01-15 15:01:11 +09:00
jaseg
0f206f09bf TIM3 working stably now 2019-01-13 15:34:01 +09:00
jaseg
7b5ca8102b Basic timer-based blanking working 2019-01-13 01:35:03 +09:00
jaseg
6006b360d1 Make protocol unit tester count test cases 2019-01-12 22:47:05 +09:00
jaseg
7461b22bfa Protocol unit test working 2019-01-12 22:44:25 +09:00
jaseg
2d392fe60a bulk cmd test works 2019-01-12 22:38:23 +09:00
jaseg
43f64f0e1f Split receiver into logical parts 2019-01-12 12:54:29 +09:00
jaseg
c6547c6e6f Basic command comm works 2019-01-11 22:02:14 +09:00
jaseg
528d653bde Decoding and comma triggering works 2019-01-10 14:31:20 +09:00
jaseg
0161d6665c Debug scope works nicely 2019-01-10 13:35:15 +09:00
jaseg
5da6e46739 Fix up scope mode 2019-01-09 22:57:11 +09:00
jaseg
d3edf27c89 Initial detector logic draft 2018-12-24 20:24:53 +09:00
jaseg
c339384cbe Pimp ADC measurements with voltage means 2018-12-24 19:55:28 +09:00
jaseg
f5d7b0428d Add untested ADC mode switching code 2018-12-24 19:09:46 +09:00
jaseg
0029ed768e Make center ADC work in "scope mode" 2018-12-24 18:08:01 +09:00
jaseg
62389e00fe ADC working 2018-12-23 12:57:40 +09:00
jaseg
468fe59d97 First AC/mux test working 2018-12-22 14:38:07 +09:00
jaseg
132fd4f9c0 8b10b encoder and decoder working
Tested on all 24-bit inputs after sync and on ~500M of random input
with and without intermediate sync
2018-12-20 22:42:17 +09:00
jaseg
90038f4378 Add initial center firmware 2018-12-20 18:54:41 +09:00
jaseg
111b7a6bf3 center: Add BOM 2018-11-27 17:15:13 +09:00
jaseg
ad292924fc Make geber zip filenames more descriptive 2018-11-27 11:03:05 +09:00
jaseg
6af42b0c5a Add corner gerber exports 2018-11-27 11:01:29 +09:00
jaseg
d699a6cb30 Add center artwork 2018-11-27 10:54:33 +09:00
jaseg
46b2427524 Add prettified gerber output 2018-11-27 10:50:48 +09:00
jaseg
2fd3a80211 Fix AO3400 pinout 2018-11-27 10:49:46 +09:00
jaseg
7027d01ad0 center: improve silk 2018-11-26 14:40:14 +09:00
jaseg
7e1d100f1b PCB designs R01 finished (not reviewed yet) 2018-11-26 14:28:04 +09:00
jaseg
260b611fc3 center: initial schematic 2018-11-25 13:11:59 +09:00
jaseg
c36fa6263b Initial commit 2018-11-24 12:52:01 +09:00