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TIM3 working stably now

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This commit is contained in:
jaseg 2019-01-13 15:34:01 +09:00
parent 7b5ca8102b
commit 0f206f09bf
4 changed files with 872 additions and 35 deletions
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2
driver_fw/main.c
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@ -70,7 +70,7 @@ int main(void) {
TIM1->BDTR = TIM_BDTR_MOE | (0xc0 | (63-32))<<TIM_BDTR_DTG_Pos; /* Enable MOE on next update event, i.e. on initial timer load.
Set dead-time to 100us. */
TIM1->CR1 |= TIM_CR1_CEN;
TIM1->ARR = 1000-1; /* Set f=1.0kHz/T=1.0ms */
TIM1->ARR = 400-1; /* Set f=2.5kHz/T=0.4ms */
xfr_8b10b_encode_reset(&txstate.st);
txstate.current_symbol = txstate.next_symbol = xfr_8b10b_encode(&txstate.st, K28_1) | 1<<10;

820
fw/Scope.ipynb
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File diff suppressed because one or more lines are too long

11
fw/adc.c
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@ -180,9 +180,12 @@ void receive_bit(struct bit_detector_st *st, int bit) {
st->sync = 0;
/* Fall through so we also pass the error to receive_symbol */
GPIOA->BSRR = 1<<9;
receive_symbol(&st->rx_st, symbol);
GPIOA->BRR = 1<<9;
/* Debug scope logic */
/*
static int debug_buf_pos = 0;
if (st->sync) {
if (debug_buf_pos < NCH) {
@ -199,6 +202,7 @@ void receive_bit(struct bit_detector_st *st, int bit) {
}
}
}
*/
}
void bit_detector(struct bit_detector_st *st, int a) {
@ -216,7 +220,6 @@ void bit_detector(struct bit_detector_st *st, int a) {
st->last_bit = new_bit;
st->len_ctr = 0;
st->committed_len_ctr = st->base_interval_cycles>>1;
unblank(new_bit);
} else if (st->len_ctr >= st->committed_len_ctr) {
st->committed_len_ctr += st->base_interval_cycles;
@ -225,8 +228,9 @@ void bit_detector(struct bit_detector_st *st, int a) {
}
void DMA1_Channel1_IRQHandler(void) {
GPIOA->BSRR = 1<<5;
/* ISR timing measurement for debugging */
int start = SysTick->VAL;
//int start = SysTick->VAL;
/* Clear the interrupt flag */
DMA1->IFCR |= DMA_IFCR_CGIF1;
@ -255,10 +259,13 @@ void DMA1_Channel1_IRQHandler(void) {
bit_detector((struct bit_detector_st *)&st.det_st, a);
/* ISR timing measurement for debugging */
/*
int end = SysTick->VAL;
int tdiff = start - end;
if (tdiff < 0)
tdiff += SysTick->LOAD;
st.dma_isr_duration = tdiff;
*/
GPIOA->BRR = 1<<5;
}

74
fw/main.c
View file

@ -71,40 +71,28 @@ void blank(void) {
set_drv_gpios(0);
}
int bit; /* FIXME */
volatile int bit; /* FIXME */
void unblank_low(void) {
if (bit)
set_drv_gpios(out_state & 0xf);
else
set_drv_gpios(out_state >> 4);
}
void unblank(int new_bit) {
bit = new_bit;
NVIC_EnableIRQ(TIM3_IRQn);
NVIC_SetPriority(TIM3_IRQn, 3<<5);
TIM3->DIER &= (~TIM_DIER_UIE) & (~TIM_DIER_CC4IE);
TIM3->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */
TIM3->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */
TIM3->CCR4 = 50; /* Trigger towards start of timer cycle */
TIM3->PSC = 48-1;
TIM3->ARR = 400-1;
TIM3->EGR |= TIM_EGR_UG;
TIM3->CR1 = TIM_CR1_ARPE | TIM_CR1_OPM;
TIM3->SR &= (~TIM_SR_UIF) & (~TIM_SR_CC4IF);
TIM3->DIER |= TIM_DIER_UIE | TIM_DIER_CC4IE;
TIM3->CR1 |= TIM_CR1_CEN;
unblank_low();
}
void TIM3_IRQHandler(void) {
if (TIM3->SR & TIM_SR_UIF) {
GPIOA->BSRR = 1<<10;
if (TIM3->SR & TIM_SR_UIF)
unblank_low();
else
blank();
} else {
if (bit)
set_drv_gpios(out_state & 0xf);
else
set_drv_gpios(out_state >> 4);
}
TIM3->SR = 0;
GPIOA->BRR = 1<<10;
}
void handle_command(int command, uint8_t *args) {
@ -133,24 +121,38 @@ int main(void) {
while (!(RCC->CR&RCC_CR_PLLRDY));
RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
SystemCoreClockUpdate();
SysTick_Config(SystemCoreClock/1000); /* 1ms interval */
//SysTick_Config(SystemCoreClock/1000); /* 1ms interval */
/* Turn on lots of neat things */
RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_FLITFEN;
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN| RCC_APB2ENR_DBGMCUEN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM1EN;;
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
/* TIM3 foo */
TIM3->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */
TIM3->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */
TIM3->PSC = 48-1;
TIM3->CCR4 = 170-1;
TIM3->ARR = 200-1;
TIM3->DIER |= TIM_DIER_UIE | TIM_DIER_CC4IE;
TIM3->CR1 |= TIM_CR1_CEN;
NVIC_EnableIRQ(TIM3_IRQn);
NVIC_SetPriority(TIM3_IRQn, 3<<5);
GPIOA->MODER |=
(0<<GPIO_MODER_MODER0_Pos) /* PA0 - Vmeas_A to ADC */
| (0<<GPIO_MODER_MODER1_Pos) /* PA1 - Vmeas_B to ADC */
| (1<<GPIO_MODER_MODER2_Pos) /* PA2 - LOAD */
| (1<<GPIO_MODER_MODER3_Pos) /* PA3 - CH0 */
| (1<<GPIO_MODER_MODER4_Pos) /* PA4 - CH3 */
| (0<<GPIO_MODER_MODER5_Pos) /* PA5 - TP1 */
| (1<<GPIO_MODER_MODER5_Pos) /* PA5 - TP1 */
| (1<<GPIO_MODER_MODER6_Pos) /* PA6 - CH2 */
| (1<<GPIO_MODER_MODER7_Pos) /* PA7 - CH1 */
| (0<<GPIO_MODER_MODER9_Pos) /* PA9 - TP2 */
| (0<<GPIO_MODER_MODER10_Pos);/* PA10 - TP3 */
| (1<<GPIO_MODER_MODER9_Pos) /* PA9 - TP2 */
| (1<<GPIO_MODER_MODER10_Pos);/* PA10 - TP3 */
/* Set shift register IO GPIO output speed */
GPIOA->OSPEEDR |=
@ -162,14 +164,22 @@ int main(void) {
set_drv_gpios(0);
adc_configure_monitor_mode(&cmd_if.cmd_if, 50 /*us*/);
adc_configure_monitor_mode(&cmd_if.cmd_if, 20 /*us*/);
int old = 0;
while (42) {
int new = GPIOA->IDR & (1<<0);
if (new != old) {
unblank(new);
TIM3->EGR |= TIM_EGR_UG;
old = new;
}
/* idle */
}
}
void NMI_Handler(void) {
asm volatile ("bkpt");
}
void HardFault_Handler(void) __attribute__((naked));
@ -178,10 +188,12 @@ void HardFault_Handler() {
}
void SVC_Handler(void) {
asm volatile ("bkpt");
}
void PendSV_Handler(void) {
asm volatile ("bkpt");
}
void SysTick_Handler(void) {