7seg/fw
2017-09-02 12:23:39 +02:00
..
.gitignore Now with working source extraction from firmware 2017-09-01 20:52:34 +02:00
base.c working commit 2017-08-15 14:34:34 +02:00
bus_addr.c Now with working source extraction from firmware 2017-09-01 20:52:34 +02:00
crc.c Add missing files 2017-09-01 20:32:15 +02:00
crc.py Add missing files 2017-09-01 20:32:15 +02:00
gen_cmsis_exports.py Add cmsis export generator 2017-08-23 10:50:43 +02:00
main.c Temperature/VCC ADC working 2017-09-02 12:23:39 +02:00
Makefile Temperature/VCC ADC working 2017-09-02 12:23:39 +02:00
mapparse.py fw working commit 2017-06-10 19:14:18 +02:00
mapvis.py fw working commit 2017-06-10 19:14:18 +02:00
MatrixTransform.ipynb Add missing files 2017-09-01 20:32:15 +02:00
measure_transpose_performance.gdb Benchmark code 2017-08-15 15:57:33 +02:00
openocd.cfg Add missing firmware build files 2017-07-20 16:06:33 +02:00
profile.gdb Add profiling script 2017-08-22 20:13:10 +02:00
profile.sh Add profiling script 2017-08-22 20:13:10 +02:00
semihosting.c fw working commit 2017-06-10 19:14:18 +02:00
startup_stm32f030x6.s Add missing firmware build files 2017-07-20 16:06:33 +02:00
stm32_flash.ld Now with working source extraction from firmware 2017-09-01 20:52:34 +02:00
system_stm32f0xx.c fw working commit 2017-06-10 19:14:18 +02:00
transpose.c DMA channel assignments redone, basic protocol stuff working 2017-09-01 15:44:39 +02:00
transpose.h UART magic seems to be working now 2017-09-01 20:26:05 +02:00
transpose_main.c Add transpose test 2017-08-23 10:50:16 +02:00