jaseg
2703e67004
fw: Fix aliasing issue, improve web IF
2025-02-07 18:18:07 +01:00
jaseg
d5ab91648d
Update fw/interface to add variance data
2025-02-07 12:56:00 +01:00
jaseg
a2d95a324a
Undo temporary spectrum measurement changes
2025-02-07 11:45:06 +01:00
jaseg
3f9a52e1b0
Add second risetime calculation
2025-01-29 16:28:07 +01:00
jaseg
b4aa5db722
Finished preliminary bandwidth analysis.
2025-01-29 16:20:51 +01:00
jaseg
fef6b17aed
Initial analysis of measurements
2025-01-29 12:47:42 +01:00
jaseg
15cd939e9c
Add spectrum measurement results
2025-01-29 11:50:21 +01:00
jaseg
0805760010
Add input clamping diodes
2025-01-28 15:37:13 +01:00
jaseg
3c54e54e5c
Paper WIP
2025-01-15 09:54:42 +01:00
jaseg
992b4dc434
Paper WIP
2024-12-14 22:19:57 +01:00
jaseg
e09904ce16
Add paper scaffold
2024-12-11 18:01:54 +01:00
jaseg
aa4839aed3
Make oversampling configurable
2024-12-02 16:39:55 +01:00
jaseg
65a626f6c8
Properly tuned double-edge sampling
2024-12-02 14:20:58 +01:00
jaseg
440922f10c
re-enable oversampling
2024-11-26 17:20:42 +01:00
jaseg
e2a074c114
It's roughly doing what it's supposed to do now.
...
We have mystery oscillations.
2024-11-26 16:45:11 +01:00
jaseg
78a0e8ae31
WIP
2024-11-26 16:34:37 +01:00
jaseg
c229fbdde8
make sampling phase and width remotely configurable
2024-11-25 21:31:42 +01:00
jaseg
3fce64ae3e
Extend remote control both ways
2024-11-25 20:56:27 +01:00
jaseg
7fb1311a85
Something weird is happening with the hrtim master period
...
This new value gives much cleaner curves. I suspect that either we have
some issue with ADC sampling not being precise due to clock domain
crossings, or this is just interference and the new period hits a sweet
spot that is coherent with this interference.
2024-11-23 15:21:34 +01:00
jaseg
1f37d9221b
Decrease oversampling to increase update rate
2024-11-23 14:29:55 +01:00
jaseg
b32c4d9d61
Move stimulus instead of sampling pulse, eliminates ADC alignment issue
...
The ADC can only trigger on whole clock pulses, so when we move the
sampling pulse in fractional increments, the relative alignment of the
ADC's sampling phase w.r.t. sampling pulse moves around +/-0.5 clock
periods. Since our opamps ring a bit, that leads to an artifact in the
measurements with a period of 32 samples (one whole clock pulse). Moving
the stimulus pulse instead fixes this issue, as now the alignment
between the sampling pulse and the ADC's sampling is constant.
2024-11-23 14:24:09 +01:00
jaseg
54ccc277c2
Add todos to board schematic
2024-11-23 13:59:24 +01:00
jaseg
e28c6e37e5
I2C wasn't working, with pin-strapped driver config we now get some *very* spicy edges it seems
...
This commit also scales the web UI plots' X axis in ns and Y axis in V.
2024-11-22 17:29:05 +01:00
jaseg
b17f86f7a1
Improved channel 1 sampling
2024-11-22 15:51:26 +01:00
jaseg
959ec55440
straighten out HRTIM triggering
2024-11-22 15:24:27 +01:00
jaseg
02ead3d52d
Speed up display
2024-11-20 20:24:20 +01:00
jaseg
4311efe728
We get first, very rough sampled measurements
2024-11-20 19:43:07 +01:00
jaseg
3bd163f806
Add clock documentation
2024-11-20 15:34:05 +01:00
jaseg
1589ece3a0
Add live measurement plot
2024-11-19 17:46:23 +01:00
jaseg
0bd266da0c
Get the ADCs converting
2024-11-18 19:53:00 +01:00
jaseg
f222741450
redriver bringup WIP
2024-07-22 17:51:02 +02:00
jaseg
d955c05ad0
Add fw skeleton
2024-07-22 13:52:18 +02:00
jaseg
df8312d266
meshes WIP
2024-04-25 16:09:16 +02:00
jaseg
d6d6a2758c
Mesh test board WIP
2024-04-25 15:53:14 +02:00
jaseg
5a60deca36
uut/mesh: Add mesh uut
2024-04-24 19:26:08 +02:00
jaseg
8719f5c93f
uut/cal kit: Add version number
2024-04-24 19:08:10 +02:00
jaseg
306c4a3262
Add cal kit UUT
2024-04-24 19:06:41 +02:00
jaseg
3fad16ba4b
Reannotate reference designators by PCB location
2024-04-24 18:31:12 +02:00
jaseg
d0823b23b8
PCB almost finished
2024-04-24 18:28:31 +02:00
jaseg
19eeb9a4ea
Initial commmit
2024-04-24 12:40:14 +02:00
