491 lines
16 KiB
C
491 lines
16 KiB
C
/* MPU6050 device I2C library code for ARM STM32F103xx is placed under the MIT license
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Copyright (c) 2012 Harinadha Reddy Chintalapalli
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#ifndef __MPU6050_H
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#define __MPU6050_H
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#include "global.h"
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#ifndef MPU_I2C_PERIPH
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#define MPU_I2C_PERIPH I2C1
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#endif
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enum mpu_i2c_addr {
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MPU_ADDRESS_AD0_LOW = 0xd0, // address pin low (GND), default for InvenSense evaluation board
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MPU_ADDRESS_AD0_HIGH = 0xd1, // address pin high (VCC)
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MPU_DEFAULT_ADDRESS = MPU_ADDRESS_AD0_LOW
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};
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enum mpu_reg_addr {
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MPU_RA_XG_OFFS_TC = 0x00, //[7] PWR_MODE, [6:1] XG_OFFS_TC, [0] OTP_BNK_VLD
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MPU_RA_YG_OFFS_TC = 0x01, //[7] PWR_MODE, [6:1] YG_OFFS_TC, [0] OTP_BNK_VLD
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MPU_RA_ZG_OFFS_TC = 0x02, //[7] PWR_MODE, [6:1] ZG_OFFS_TC, [0] OTP_BNK_VLD
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MPU_RA_X_FINE_GAIN = 0x03, //[7:0] X_FINE_GAIN
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MPU_RA_Y_FINE_GAIN = 0x04, //[7:0] Y_FINE_GAIN
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MPU_RA_Z_FINE_GAIN = 0x05, //[7:0] Z_FINE_GAIN
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MPU_RA_XA_OFFS_H = 0x06, //[15:0] XA_OFFS
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MPU_RA_XA_OFFS_L_TC = 0x07,
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MPU_RA_YA_OFFS_H = 0x08, //[15:0] YA_OFFS
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MPU_RA_YA_OFFS_L_TC = 0x09,
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MPU_RA_ZA_OFFS_H = 0x0A, //[15:0] ZA_OFFS
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MPU_RA_ZA_OFFS_L_TC = 0x0B,
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MPU_RA_XG_OFFS_USRH = 0x13, //[15:0] XG_OFFS_USR
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MPU_RA_XG_OFFS_USRL = 0x14,
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MPU_RA_YG_OFFS_USRH = 0x15, //[15:0] YG_OFFS_USR
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MPU_RA_YG_OFFS_USRL = 0x16,
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MPU_RA_ZG_OFFS_USRH = 0x17, //[15:0] ZG_OFFS_USR
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MPU_RA_ZG_OFFS_USRL = 0x18,
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MPU_RA_SMPLRT_DIV = 0x19,
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MPU_RA_CONFIG = 0x1A,
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MPU_RA_GYRO_CONFIG = 0x1B,
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MPU_RA_ACCEL_CONFIG = 0x1C,
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MPU_RA_FF_THR = 0x1D,
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MPU_RA_FF_DUR = 0x1E,
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MPU_RA_MOT_THR = 0x1F,
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MPU_RA_MOT_DUR = 0x20,
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MPU_RA_ZRMOT_THR = 0x21,
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MPU_RA_ZRMOT_DUR = 0x22,
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MPU_RA_FIFO_EN = 0x23,
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MPU_RA_I2C_MST_CTRL = 0x24,
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MPU_RA_I2C_SLV0_ADDR = 0x25,
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MPU_RA_I2C_SLV0_REG = 0x26,
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MPU_RA_I2C_SLV0_CTRL = 0x27,
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MPU_RA_I2C_SLV1_ADDR = 0x28,
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MPU_RA_I2C_SLV1_REG = 0x29,
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MPU_RA_I2C_SLV1_CTRL = 0x2A,
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MPU_RA_I2C_SLV2_ADDR = 0x2B,
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MPU_RA_I2C_SLV2_REG = 0x2C,
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MPU_RA_I2C_SLV2_CTRL = 0x2D,
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MPU_RA_I2C_SLV3_ADDR = 0x2E,
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MPU_RA_I2C_SLV3_REG = 0x2F,
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MPU_RA_I2C_SLV3_CTRL = 0x30,
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MPU_RA_I2C_SLV4_ADDR = 0x31,
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MPU_RA_I2C_SLV4_REG = 0x32,
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MPU_RA_I2C_SLV4_DO = 0x33,
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MPU_RA_I2C_SLV4_CTRL = 0x34,
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MPU_RA_I2C_SLV4_DI = 0x35,
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MPU_RA_I2C_MST_STATUS = 0x36,
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MPU_RA_INT_PIN_CFG = 0x37,
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MPU_RA_INT_ENABLE = 0x38,
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MPU_RA_DMP_INT_STATUS = 0x39,
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MPU_RA_INT_STATUS = 0x3A,
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MPU_RA_ACCEL_XOUT_H = 0x3B,
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MPU_RA_ACCEL_XOUT_L = 0x3C,
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MPU_RA_ACCEL_YOUT_H = 0x3D,
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MPU_RA_ACCEL_YOUT_L = 0x3E,
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MPU_RA_ACCEL_ZOUT_H = 0x3F,
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MPU_RA_ACCEL_ZOUT_L = 0x40,
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MPU_RA_TEMP_OUT_H = 0x41,
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MPU_RA_TEMP_OUT_L = 0x42,
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MPU_RA_GYRO_XOUT_H = 0x43,
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MPU_RA_GYRO_XOUT_L = 0x44,
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MPU_RA_GYRO_YOUT_H = 0x45,
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MPU_RA_GYRO_YOUT_L = 0x46,
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MPU_RA_GYRO_ZOUT_H = 0x47,
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MPU_RA_GYRO_ZOUT_L = 0x48,
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MPU_RA_EXT_SENS_DATA_00 = 0x49,
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MPU_RA_EXT_SENS_DATA_01 = 0x4A,
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MPU_RA_EXT_SENS_DATA_02 = 0x4B,
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MPU_RA_EXT_SENS_DATA_03 = 0x4C,
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MPU_RA_EXT_SENS_DATA_04 = 0x4D,
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MPU_RA_EXT_SENS_DATA_05 = 0x4E,
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MPU_RA_EXT_SENS_DATA_06 = 0x4F,
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MPU_RA_EXT_SENS_DATA_07 = 0x50,
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MPU_RA_EXT_SENS_DATA_08 = 0x51,
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MPU_RA_EXT_SENS_DATA_09 = 0x52,
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MPU_RA_EXT_SENS_DATA_10 = 0x53,
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MPU_RA_EXT_SENS_DATA_11 = 0x54,
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MPU_RA_EXT_SENS_DATA_12 = 0x55,
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MPU_RA_EXT_SENS_DATA_13 = 0x56,
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MPU_RA_EXT_SENS_DATA_14 = 0x57,
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MPU_RA_EXT_SENS_DATA_15 = 0x58,
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MPU_RA_EXT_SENS_DATA_16 = 0x59,
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MPU_RA_EXT_SENS_DATA_17 = 0x5A,
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MPU_RA_EXT_SENS_DATA_18 = 0x5B,
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MPU_RA_EXT_SENS_DATA_19 = 0x5C,
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MPU_RA_EXT_SENS_DATA_20 = 0x5D,
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MPU_RA_EXT_SENS_DATA_21 = 0x5E,
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MPU_RA_EXT_SENS_DATA_22 = 0x5F,
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MPU_RA_EXT_SENS_DATA_23 = 0x60,
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MPU_RA_MOT_DETECT_STATUS = 0x61,
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MPU_RA_I2C_SLV0_DO = 0x63,
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MPU_RA_I2C_SLV1_DO = 0x64,
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MPU_RA_I2C_SLV2_DO = 0x65,
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MPU_RA_I2C_SLV3_DO = 0x66,
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MPU_RA_I2C_MST_DELAY_CTRL = 0x67,
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MPU_RA_SIGNAL_PATH_RESET = 0x68,
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MPU_RA_MOT_DETECT_CTRL = 0x69,
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MPU_RA_USER_CTRL = 0x6A,
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MPU_RA_PWR_MGMT1 = 0x6B,
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MPU_RA_PWR_MGMT2 = 0x6C,
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MPU_RA_BANK_SEL = 0x6D,
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MPU_RA_MEM_START_ADDR = 0x6E,
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MPU_RA_MEM_R_W = 0x6F,
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MPU_RA_DMP_CFG1 = 0x70,
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MPU_RA_DMP_CFG2 = 0x71,
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MPU_RA_FIFO_COUNTH = 0x72,
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MPU_RA_FIFO_COUNTL = 0x73,
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MPU_RA_FIFO_R_W = 0x74,
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MPU_RA_WHO_AM_I = 0x75,
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};
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enum mpu_tc {
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MPU_TC_PWR_MODE_BIT = 7,
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MPU_TC_OFFSET_BIT = 6,
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MPU_TC_OFFSET_LENGTH = 6,
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MPU_TC_OTP_BNK_VLD_BIT = 0,
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};
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enum mpu_vddio {
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MPU_VDDIO_LEVEL_VLOGIC = 0,
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MPU_VDDIO_LEVEL_VDD = 1,
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};
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enum mpu_cfg {
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MPU_CFG_EXT_SYNC_SET_BIT = 5,
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MPU_CFG_EXT_SYNC_SET_LENGTH = 3,
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MPU_CFG_DLPF_CFG_BIT = 2,
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MPU_CFG_DLPF_CFG_LENGTH = 3,
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};
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enum mpu_ext {
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MPU_EXT_SYNC_DISABLED = 0x0,
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MPU_EXT_SYNC_TEMP_OUT_L = 0x1,
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MPU_EXT_SYNC_GYRO_XOUT_L = 0x2,
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MPU_EXT_SYNC_GYRO_YOUT_L = 0x3,
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MPU_EXT_SYNC_GYRO_ZOUT_L = 0x4,
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MPU_EXT_SYNC_ACCEL_XOUT_L = 0x5,
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MPU_EXT_SYNC_ACCEL_YOUT_L = 0x6,
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MPU_EXT_SYNC_ACCEL_ZOUT_L = 0x7,
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};
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enum mpu_dlpf {
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MPU_DLPF_BW_256 = 0x00,
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MPU_DLPF_BW_188 = 0x01,
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MPU_DLPF_BW_98 = 0x02,
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MPU_DLPF_BW_42 = 0x03,
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MPU_DLPF_BW_20 = 0x04,
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MPU_DLPF_BW_10 = 0x05,
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MPU_DLPF_BW_5 = 0x06,
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};
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enum mpu_gyro_config {
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/* self test */
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MPU_GYRO_XG_ST = 1<<7,
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MPU_GYRO_YG_ST = 1<<6,
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MPU_GYRO_ZG_ST = 1<<5,
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/* full scale */
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MPU_GYRO_FS_SEL_Pos = 3,
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MPU_GYRO_FS_SEL_Msk = 3<<3,
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MPU_GYRO_FS_250 = 0<<3,
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MPU_GYRO_FS_500 = 1<<3,
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MPU_GYRO_FS_1000 = 2<<3,
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MPU_GYRO_FS_2000 = 3<<3,
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/* dlpf config, default 0b00 */
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MPU_GYRO_FCHOICE_B_Pos = 0,
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MPU_GYRO_FCHOICE_B_Msk = 3<<0,
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};
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enum mpu_accel_config {
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/* self test */
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MPU_ACCEL_CONFIG_XA_ST = 1<<7,
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MPU_ACCEL_CONFIG_YA_ST = 1<<6,
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MPU_ACCEL_CONFIG_ZA_ST = 1<<5,
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/* full scale */
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MPU_ACCEL_CONFIG_FS_SEL_Pos = 3,
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MPU_ACCEL_CONFIG_FS_SEL_Msk = 3<<3,
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MPU_ACCEL_FS_2 = 0x00,
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MPU_ACCEL_FS_4 = 0x01,
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MPU_ACCEL_FS_8 = 0x02,
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MPU_ACCEL_FS_16 = 0x03,
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};
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enum mpu_en {
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MPU_TEMP_FIFO_EN_BIT = 7,
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MPU_XG_FIFO_EN_BIT = 6,
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MPU_YG_FIFO_EN_BIT = 5,
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MPU_ZG_FIFO_EN_BIT = 4,
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MPU_ACCEL_FIFO_EN_BIT = 3,
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MPU_SLV2_FIFO_EN_BIT = 2,
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MPU_SLV1_FIFO_EN_BIT = 1,
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MPU_SLV0_FIFO_EN_BIT = 0,
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MPU_MULT_MST_EN_BIT = 7,
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MPU_WAIT_FOR_ES_BIT = 6,
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MPU_SLV_3_FIFO_EN_BIT = 5,
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MPU_I2C_MST_P_NSR_BIT = 4,
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MPU_I2C_MST_CLK_BIT = 3,
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MPU_I2C_MST_CLK_LENGTH = 4,
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};
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enum mpu_clkdiv {
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MPU_CLOCK_DIV_348 = 0x0,
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MPU_CLOCK_DIV_333 = 0x1,
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MPU_CLOCK_DIV_320 = 0x2,
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MPU_CLOCK_DIV_308 = 0x3,
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MPU_CLOCK_DIV_296 = 0x4,
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MPU_CLOCK_DIV_286 = 0x5,
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MPU_CLOCK_DIV_276 = 0x6,
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MPU_CLOCK_DIV_267 = 0x7,
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MPU_CLOCK_DIV_258 = 0x8,
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MPU_CLOCK_DIV_500 = 0x9,
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MPU_CLOCK_DIV_471 = 0xA,
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MPU_CLOCK_DIV_444 = 0xB,
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MPU_CLOCK_DIV_421 = 0xC,
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MPU_CLOCK_DIV_400 = 0xD,
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MPU_CLOCK_DIV_381 = 0xE,
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MPU_CLOCK_DIV_364 = 0xF,
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};
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enum mpu_i2c_slv {
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MPU_I2C_SLV_RW_BIT = 7,
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MPU_I2C_SLV_ADDR_BIT = 6,
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MPU_I2C_SLV_ADDR_LENGTH = 7,
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MPU_I2C_SLV_EN_BIT = 7,
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MPU_I2C_SLV_BYTE_SW_BIT = 6,
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MPU_I2C_SLV_REG_DIS_BIT = 5,
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MPU_I2C_SLV_GRP_BIT = 4,
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MPU_I2C_SLV_LEN_BIT = 3,
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MPU_I2C_SLV_LEN_LENGTH = 4,
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};
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enum mpu_i2c_slv4 {
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MPU_I2C_SLV4_RW_BIT = 7,
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MPU_I2C_SLV4_ADDR_BIT = 6,
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MPU_I2C_SLV4_ADDR_LENGTH = 7,
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MPU_I2C_SLV4_EN_BIT = 7,
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MPU_I2C_SLV4_INT_EN_BIT = 6,
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MPU_I2C_SLV4_REG_DIS_BIT = 5,
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MPU_I2C_SLV4_MST_DLY_BIT = 4,
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MPU_I2C_SLV4_MST_DLY_LENGTH = 5,
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};
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enum mpu_mst {
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MPU_MST_PASS_THROUGH_BIT = 7,
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MPU_MST_I2C_SLV4_DONE_BIT = 6,
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MPU_MST_I2C_LOST_ARB_BIT = 5,
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MPU_MST_I2C_SLV4_NACK_BIT = 4,
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MPU_MST_I2C_SLV3_NACK_BIT = 3,
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MPU_MST_I2C_SLV2_NACK_BIT = 2,
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MPU_MST_I2C_SLV1_NACK_BIT = 1,
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MPU_MST_I2C_SLV0_NACK_BIT = 0,
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};
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enum mpu_intcfg {
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MPU_INT_PIN_CFG_INT_LEVEL = 1<<7,
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MPU_INTMODE_ACTIVEHIGH = 0,
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MPU_INTMODE_ACTIVELOW = 1<<7,
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MPU_INT_PIN_CFG_INT_OPEN = 1<<6,
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MPU_INTDRV_PUSHPULL = 0,
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MPU_INTDRV_OPENDRAIN = 1<<6,
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MPU_INT_PIN_CFG_LATCH_INT_EN = 1<<5,
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MPU_INTLATCH_50USPULSE = 0,
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MPU_INTLATCH_WAITCLEAR = 1<<5,
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MPU_INT_PIN_CFG_RD_CLEAR = 1<<4,
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MPU_INTCLEAR_STATUSREAD = 0,
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MPU_INTCLEAR_ANYREAD = 1<<4,
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MPU_INT_PIN_CFG_FSYNC_INT_LEVEL = 1<<3,
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MPU_INT_PIN_CFG_FSYNC_INT_EN = 1<<2,
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MPU_INT_PIN_CFG_I2C_BYPASS_EN = 1<<1,
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MPU_INT_PIN_CFG_CLKOUT_EN = 1<<0,
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};
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enum mpu_int_enable {
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MPU_INT_ENABLE_FIFO_OFLOW = 1<<4,
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MPU_INT_ENABLE_I2C_MST_INT = 1<<3,
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MPU_INT_ENABLE_DATA_RDY = 1<<0,
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};
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// TODO: Need to work on DMP related things
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enum mpu_dmpint {
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MPU_DMPINT_5_BIT = 5,
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MPU_DMPINT_4_BIT = 4,
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MPU_DMPINT_3_BIT = 3,
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MPU_DMPINT_2_BIT = 2,
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MPU_DMPINT_1_BIT = 1,
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MPU_DMPINT_0_BIT = 0,
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};
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enum mpu_motion {
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MPU_MOTION_MOT_XNEG_BIT = 7,
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MPU_MOTION_MOT_XPOS_BIT = 6,
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MPU_MOTION_MOT_YNEG_BIT = 5,
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MPU_MOTION_MOT_YPOS_BIT = 4,
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MPU_MOTION_MOT_ZNEG_BIT = 3,
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MPU_MOTION_MOT_ZPOS_BIT = 2,
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MPU_MOTION_MOT_ZRMOT_BIT = 0,
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};
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enum mpu_delayctrl {
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MPU_DELAYCTRL_DELAY_ES_SHADOW_BIT = 7,
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MPU_DELAYCTRL_I2C_SLV4_DLY_EN_BIT = 4,
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MPU_DELAYCTRL_I2C_SLV3_DLY_EN_BIT = 3,
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MPU_DELAYCTRL_I2C_SLV2_DLY_EN_BIT = 2,
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MPU_DELAYCTRL_I2C_SLV1_DLY_EN_BIT = 1,
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MPU_DELAYCTRL_I2C_SLV0_DLY_EN_BIT = 0,
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};
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enum mpu_pathreset {
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MPU_PATHRESET_GYRO_RESET_BIT = 2,
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MPU_PATHRESET_ACCEL_RESET_BIT = 1,
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MPU_PATHRESET_TEMP_RESET_BIT = 0,
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};
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enum mpu_detect {
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MPU_DETECT_ACCEL_ON_DELAY_BIT = 5,
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MPU_DETECT_ACCEL_ON_DELAY_LENGTH = 2,
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MPU_DETECT_FF_COUNT_BIT = 3,
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MPU_DETECT_FF_COUNT_LENGTH = 2,
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MPU_DETECT_MOT_COUNT_BIT = 1,
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MPU_DETECT_MOT_COUNT_LENGTH = 2,
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MPU_DETECT_DECREMENT_RESET = 0x0,
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MPU_DETECT_DECREMENT_1 = 0x1,
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MPU_DETECT_DECREMENT_2 = 0x2,
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MPU_DETECT_DECREMENT_4 = 0x3,
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};
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enum mpu_userctrl {
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MPU_USERCTRL_DMP_EN_BIT = 7,
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MPU_USERCTRL_FIFO_EN_BIT = 6,
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MPU_USERCTRL_I2C_MST_EN_BIT = 5,
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MPU_USERCTRL_I2C_IF_DIS_BIT = 4,
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MPU_USERCTRL_DMP_RESET_BIT = 3,
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MPU_USERCTRL_FIFO_RESET_BIT = 2,
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MPU_USERCTRL_I2C_MST_RESET_BIT = 1,
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MPU_USERCTRL_SIG_COND_RESET_BIT = 0,
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};
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enum mpu_pwr_mgmt1 {
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MPU_PWR_MGMT1_DEVICE_RESET = 1<<7,
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/* Low power sleep mode */
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MPU_PWR_MGMT1_SLEEP = 1<<6,
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/* Low power auto wakeup/cycle mode */
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MPU_PWR_MGMT1_CYCLE = 1<<5,
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/* Temperature sensor disable */
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MPU_PWR_MGMT1_TEMP_DIS = 1<<3,
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/* Clock source selection */
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MPU_PWR_MGMT1_CLKSEL_Msk = 0x7,
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MPU_PWR_MGMT1_CLKSEL_Pos = 0,
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MPU_CLOCK_INTERNAL = 0,
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MPU_CLOCK_PLL_XGYRO = 1,
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MPU_CLOCK_PLL_YGYRO = 2,
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MPU_CLOCK_PLL_ZGYRO = 3,
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MPU_CLOCK_PLL_EXT32K = 4,
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MPU_CLOCK_PLL_EXT19M = 5,
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MPU_CLOCK_KEEP_RESET = 7,
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|
};
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|
|
|
enum mpu_pwr_mgmt2 {
|
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/* low-power cyclic auto wakeup */
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MPU_PWR_MGMT2_LP_WAKE_CTRL_Pos = 6,
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|
MPU_PWR_MGMT2_LP_WAKE_CTRL_Msk = 3<<6,
|
|
MPU_WAKE_FREQ_1P25 = 0<<6,
|
|
MPU_WAKE_FREQ_5 = 1<<6,
|
|
MPU_WAKE_FREQ_20 = 2<<6,
|
|
MPU_WAKE_FREQ_40 = 3<<6,
|
|
/* axis standby bits */
|
|
MPU_PWR_MGMT2_STBY_XA = 1<<5,
|
|
MPU_PWR_MGMT2_STBY_YA = 1<<4,
|
|
MPU_PWR_MGMT2_STBY_ZA = 1<<3,
|
|
MPU_PWR_MGMT2_STBY_XG = 1<<2,
|
|
MPU_PWR_MGMT2_STBY_YG = 1<<1,
|
|
MPU_PWR_MGMT2_STBY_ZG = 1<<0,
|
|
};
|
|
|
|
enum mpu_banksel {
|
|
MPU_BANKSEL_PRFTCH_EN_BIT = 6,
|
|
MPU_BANKSEL_CFG_USER_BANK_BIT = 5,
|
|
MPU_BANKSEL_MEM_SEL_BIT = 4,
|
|
MPU_BANKSEL_MEM_SEL_LENGTH = 5,
|
|
};
|
|
|
|
enum mpu_whoami {
|
|
MPU_WHO_AM_I_Pos = 1,
|
|
MPU_WHO_AM_I_Msk = 0x3f<<1,
|
|
MPU_DEVICE_ID = 0x34,
|
|
};
|
|
|
|
enum mpu_dmp_mem {
|
|
MPU_DMP_MEMORY_BANKS = 8,
|
|
MPU_DMP_MEMORY_BANK_SIZE = 256,
|
|
MPU_DMP_MEMORY_CHUNK_SIZE = 16,
|
|
};
|
|
|
|
|
|
struct __attribute__((packed)) mpu_accel_data {
|
|
union {
|
|
struct { int16_t x, y, z; };
|
|
int16_t channels[3];
|
|
};
|
|
};
|
|
|
|
struct __attribute__((packed)) mpu_gyro_data {
|
|
union {
|
|
struct { int16_t x, y, z; };
|
|
int16_t channels[3];
|
|
};
|
|
};
|
|
|
|
struct __attribute__((packed)) mpu_raw_data {
|
|
union {
|
|
struct {
|
|
struct mpu_accel_data accel;
|
|
int16_t temp;
|
|
struct mpu_gyro_data gyro;
|
|
};
|
|
int16_t channels[7];
|
|
};
|
|
};
|
|
|
|
|
|
void mpu_init();
|
|
void mpu_init_low_power(uint8_t wake_freq, bool enable_interrupt);
|
|
bool mpu_test_connection();
|
|
|
|
uint8_t mpu_get_gyro_fs();
|
|
void mpu_set_gyro_fs(uint8_t range);
|
|
|
|
uint8_t mpu_get_accel_fs();
|
|
void mpu_set_accel_fs(uint8_t range);
|
|
|
|
// PWR_MGMT_1 register
|
|
bool mpu_get_sleep_mode();
|
|
void mpu_set_sleep_mode(bool val);
|
|
// WHO_AM_I register
|
|
uint8_t mpu_device_id();
|
|
|
|
void mpu_read_accel_gyro(struct mpu_raw_data *out);
|
|
int16_t mpu_read_temp();
|
|
void mpu_read_accel(struct mpu_accel_data *out);
|
|
void mpu_read_gyro(struct mpu_gyro_data *out);
|
|
|
|
void mpu_reg_write(uint8_t reg, uint8_t val);
|
|
void mpu_reg_read_multiple(uint8_t addr, uint8_t* buf, size_t len);
|
|
uint8_t mpu_reg_read(uint8_t addr);
|
|
|
|
#endif /* __MPU6050_H */
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