Added interlace video mode detection.
This commit is contained in:
Mike Field
parent
3006625c0f
commit
ffd9761e89
7 changed files with 193 additions and 19 deletions
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@ -1,9 +1,9 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2014.4 (64-bit) -->
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<!-- Product Version: Vivado v2015.2 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="2" Path="C:/repos/Artix-7-HDMI-processing/Artix-7-HDMI-processing.xpr">
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<Project Version="7" Minor="5" Path="C:/repos/Artix-7-HDMI-processing/Artix-7-HDMI-processing.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="487e6670b2224898a3f8937139078585"/>
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@ -12,6 +12,8 @@
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<Option Name="BoardPart" Val=""/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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<Option Name="EnableCoreContainerForIPI" Val="FALSE"/>
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</Configuration>
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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@ -52,6 +54,12 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/src/detect_interlace.vhd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/src/extract_video_infopacket_data.vhd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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@ -183,12 +191,14 @@
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</File>
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<File Path="$PPRDIR/test_bench/tb_convert_yCbCr_to_RGB.vhd">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/test_bench/tb_audio_to_db.vhd">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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@ -208,7 +218,10 @@
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<Option Name="CompiledLib" Val="0"/>
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</Simulator>
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<Simulator Name="ModelSim">
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<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
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<Option Name="Description" Val="ModelSim Simulator"/>
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</Simulator>
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<Simulator Name="Questa">
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<Option Name="Description" Val="Questa Advanced Simulator"/>
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</Simulator>
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<Simulator Name="IES">
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<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
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@ -216,6 +229,12 @@
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<Simulator Name="VCS">
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<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
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</Simulator>
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<Simulator Name="Riviera">
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<Option Name="Description" Val="Riviera-PRO Simulator"/>
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</Simulator>
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<Simulator Name="ActiveHDL">
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<Option Name="Description" Val="Active-HDL Simulator"/>
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</Simulator>
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</Simulators>
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<Runs Version="1" Minor="9">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
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@ -61,6 +61,8 @@ entity audio_meters is
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in_red : in std_logic_vector(7 downto 0);
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in_green : in std_logic_vector(7 downto 0);
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in_blue : in std_logic_vector(7 downto 0);
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is_interlaced : in std_logic;
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is_second_field : in std_logic;
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-----------------------------------
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-- VGA data to be converted to HDMI
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118
src/detect_interlace.vhd
Normal file
118
src/detect_interlace.vhd
Normal file
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@ -0,0 +1,118 @@
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----------------------------------------------------------------------------------
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-- Engineer: Mike Field <hamster@snap.net.nz>
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--
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-- Module Name: detect_interlace - Behavioral
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--
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-- Description: Detect if the source is interlaced, and report what field is
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-- being processed
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--
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-- Will need to make allowances for interlaced sources!
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------------------------------------------------------------------------------------
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-- The MIT License (MIT)
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--
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-- Copyright (c) 2015 Michael Alan Field
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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------------------------------------------------------------------------------------
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----- Want to say thanks? ----------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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-- This design has taken many hours - with the industry metric of 30 lines
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-- per day, it is equivalent to about 6 months of work. I'm more than happy
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-- to share it if you can make use of it. It is released under the MIT license,
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-- so you are not under any onus to say thanks, but....
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--
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-- If you what to say thanks for this design how about trying PayPal?
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-- Educational use - Enough for a beer
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-- Hobbyist use - Enough for a pizza
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-- Research use - Enough to take the family out to dinner
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-- Commercial use - A weeks pay for an engineer (I wish!)
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity detect_interlace is
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Port ( clk : in STD_LOGIC;
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hsync : in std_logic;
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vsync : in std_logic;
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is_interlaced : out std_logic;
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is_second_field : out std_logic);
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end entity;
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architecture Behavioral of detect_interlace is
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signal last_vsync : std_logic := '0';
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signal last_hsync : std_logic := '0';
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signal first_quarter : unsigned(11 downto 0) := (others => '0');
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signal last_quarter : unsigned(11 downto 0) := (others => '0');
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signal hcount : unsigned(11 downto 0) := (others => '0');
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signal last_vsync_pos : unsigned(11 downto 0) := (others => '0');
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signal second_field : std_logic := '0';
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begin
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clk_proc: process(clk)
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begin
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if rising_edge(clk) then
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if last_vsync = '0' and vsync = '1' then
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is_second_field <= '0';
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if hcount > first_quarter and hcount < last_quarter then
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-- The second field of an interlaced
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-- frame is indicated when the vsync is
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-- asserted in the middle of the scan line.
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--
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-- Also add a little check for a misbehaving source
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if last_vsync_pos /= hcount then
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is_interlaced <= '1';
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is_second_field <= '1';
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second_field <= '1';
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else
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is_interlaced <= '1';
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is_second_field <= '1';
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second_field <= '1';
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end if;
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else
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-- If we see two 'field 1's in a row we
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-- switch back to indicating an
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-- uninterlaced source
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if second_field = '0' then
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is_interlaced <= '0';
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end if;
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is_second_field <= '0';
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second_field <= '0';
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end if;
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last_vsync_pos <= hcount;
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else
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end if;
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if last_hsync = '0' and hsync = '1' then
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hcount <= (others => '0');
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first_quarter <= "00" & hcount(11 downto 2);
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last_quarter <= hcount+1-hcount(11 downto 2);
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else
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hcount <= hcount +1;
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end if;
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last_vsync <= vsync;
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last_hsync <= hsync;
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end if;
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end process;
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end architecture;
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@ -84,7 +84,7 @@ process(clk)
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-- Move the incoming bits into a shift register
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-----------------------------------------------
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header_bits <= adp_header_bit & header_bits(header_bits'high downto 1);
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frame_bits <= adp_frame_bit & frame_bits(frame_bits'high downto 1);
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frame_bits <= adp_frame_bit & frame_bits(frame_bits'high downto 1);
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subpacket0_bits <= adp_subpacket0_bits & subpacket0_bits(subpacket0_bits'high downto 2);
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updated <= '1';
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end if;
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@ -123,12 +123,14 @@ architecture Behavioral of hdmi_design is
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-- VGA data recovered from HDMI
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-------------------------------
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in_hdmi_detected : out std_logic;
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in_blank : out std_logic;
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in_hsync : out std_logic;
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in_vsync : out std_logic;
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in_red : out std_logic_vector(7 downto 0);
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in_green : out std_logic_vector(7 downto 0);
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in_blue : out std_logic_vector(7 downto 0);
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in_blank : out std_logic;
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in_hsync : out std_logic;
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in_vsync : out std_logic;
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in_red : out std_logic_vector(7 downto 0);
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in_green : out std_logic_vector(7 downto 0);
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in_blue : out std_logic_vector(7 downto 0);
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is_interlaced : out std_logic;
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is_second_field : out std_logic;
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-------------------------------------
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-- Audio Levels
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@ -160,6 +162,8 @@ architecture Behavioral of hdmi_design is
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in_red : in std_logic_vector(7 downto 0);
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in_green : in std_logic_vector(7 downto 0);
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in_blue : in std_logic_vector(7 downto 0);
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is_interlaced : in std_logic;
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is_second_field : in std_logic;
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-------------------
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-- Processed pixels
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@ -187,6 +191,8 @@ architecture Behavioral of hdmi_design is
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signal in_red : std_logic_vector(7 downto 0);
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signal in_green : std_logic_vector(7 downto 0);
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signal in_blue : std_logic_vector(7 downto 0);
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signal is_interlaced : std_logic;
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signal is_second_field : std_logic;
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signal out_blank : std_logic;
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signal out_hsync : std_logic;
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signal out_vsync : std_logic;
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@ -274,7 +280,8 @@ i_processing: pixel_processing Port map (
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in_red => in_red,
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in_green => in_green,
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in_blue => in_blue,
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is_interlaced => is_interlaced,
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is_second_field => is_second_field,
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audio_channel => audio_channel,
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audio_de => audio_de,
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audio_sample => audio_sample,
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@ -95,6 +95,8 @@ entity hdmi_io is
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in_red : out std_logic_vector(7 downto 0);
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in_green : out std_logic_vector(7 downto 0);
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in_blue : out std_logic_vector(7 downto 0);
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is_interlaced : out std_logic;
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is_second_field : out std_logic;
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-----------------------------------
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-- VGA data to be converted to HDMI
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@ -160,7 +162,7 @@ architecture Behavioral of hdmi_io is
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adp_subpacket3_bits : out std_logic_vector(1 downto 0)
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);
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end component;
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-----------------------------------------------------
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-- This is a half-baked solution to extracting data
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-- from ADP packets - just pipe the data thorugh and
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@ -192,6 +194,8 @@ architecture Behavioral of hdmi_io is
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signal adp_subpacket1_bits : std_logic_vector(1 downto 0);
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signal adp_subpacket2_bits : std_logic_vector(1 downto 0);
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signal adp_subpacket3_bits : std_logic_vector(1 downto 0);
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signal is_interlaced_i : std_logic;
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signal is_second_field_i : std_logic;
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component extract_audio_samples is
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Port ( clk : in STD_LOGIC;
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@ -219,6 +223,14 @@ architecture Behavioral of hdmi_io is
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signal raw_ch1 : std_logic_vector(7 downto 0); -- G or Y
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signal raw_ch0 : std_logic_vector(7 downto 0); -- R or Cr
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component detect_interlace is
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Port ( clk : in STD_LOGIC;
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hsync : in std_logic;
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vsync : in std_logic;
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is_interlaced : out std_logic;
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is_second_field : out std_logic);
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end component;
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component expand_422_to_444 is
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Port ( clk : in STD_LOGIC;
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input_is_422 : in std_logic;
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@ -324,16 +336,17 @@ begin
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hdmi_rx_txen <= '1';
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hdmi_rx_cec <= 'Z';
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debug(7) <= input_is_YCbCr;
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debug(6) <= input_is_422;
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debug(5) <= input_is_sRGB;
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debug(4 downto 3) <= (others => '0');
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debug(7) <= raw_hsync;
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debug(6) <= raw_vsync;
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debug(5) <= is_second_field_i;
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debug(4) <= is_interlaced_i;
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debug(3 downto 0) <= (others => '0');
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i_edid_rom: edid_rom port map (
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clk => clk100,
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sclk_raw => hdmi_rx_scl,
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sdat_raw => hdmi_rx_sda,
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edid_debug => debug(2 downto 0));
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edid_debug => open);
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---------------------
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-- Input buffers
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@ -411,6 +424,15 @@ i_expand_422_to_444: expand_422_to_444 Port map (
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out_W => fourfourfour_W
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);
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is_interlaced <= is_interlaced_i;
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is_second_field <= is_second_field_i;
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i_detect_interlace: detect_interlace Port map (
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clk => pixel_clk_i,
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hsync => raw_hsync,
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vsync => raw_vsync,
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is_interlaced => is_interlaced_i,
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is_second_field => is_second_field_i);
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i_conversion_to_RGB: conversion_to_RGB
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port map (
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clk => pixel_clk_i,
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@ -59,6 +59,8 @@ entity pixel_processing is
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in_red : in std_logic_vector(7 downto 0);
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in_green : in std_logic_vector(7 downto 0);
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in_blue : in std_logic_vector(7 downto 0);
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is_interlaced : in std_logic;
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is_second_field : in std_logic;
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-----------------------------------
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-- VGA data to be converted to HDMI
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-----------------------------------
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@ -104,6 +106,8 @@ architecture Behavioral of pixel_processing is
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in_red : in std_logic_vector(7 downto 0);
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in_green : in std_logic_vector(7 downto 0);
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in_blue : in std_logic_vector(7 downto 0);
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is_interlaced : in std_logic;
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is_second_field : in std_logic;
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-----------------------------------
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-- VGA data to be converted to HDMI
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@ -146,7 +150,9 @@ i_audio_meters: audio_meters Port map (
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in_red => in_red,
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in_green => in_green,
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in_blue => in_blue,
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is_interlaced => is_interlaced,
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is_second_field => is_second_field,
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out_blank => out_blank,
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out_hsync => out_hsync,
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out_vsync => out_vsync,
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