From ffd9761e89f8cd1d93dda6af81531d3c5c4c363d Mon Sep 17 00:00:00 2001
From: Mike Field <hamster@snap.net.nz>
Date: Thu, 6 Aug 2015 15:43:11 +1200
Subject: [PATCH] Added interlace video mode detection.

---
 Artix-7-HDMI-processing.xpr           |  27 +++++-
 src/audio_meters.vhd                  |   2 +
 src/detect_interlace.vhd              | 118 ++++++++++++++++++++++++++
 src/extract_video_infopacket_data.vhd |   2 +-
 src/hdmi_design.vhd                   |  21 +++--
 src/hdmi_io.vhd                       |  34 ++++++--
 src/pixel_processing.vhd              |   8 +-
 7 files changed, 193 insertions(+), 19 deletions(-)
 create mode 100644 src/detect_interlace.vhd

diff --git a/Artix-7-HDMI-processing.xpr b/Artix-7-HDMI-processing.xpr
index d981340..bf15b88 100644
--- a/Artix-7-HDMI-processing.xpr
+++ b/Artix-7-HDMI-processing.xpr
@@ -1,9 +1,9 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2014.4 (64-bit)              -->
+<!-- Product Version: Vivado v2015.2 (64-bit)              -->
 <!--                                                         -->
-<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.   -->
 
-<Project Version="7" Minor="2" Path="C:/repos/Artix-7-HDMI-processing/Artix-7-HDMI-processing.xpr">
+<Project Version="7" Minor="5" Path="C:/repos/Artix-7-HDMI-processing/Artix-7-HDMI-processing.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
     <Option Name="Id" Val="487e6670b2224898a3f8937139078585"/>
@@ -12,6 +12,8 @@
     <Option Name="BoardPart" Val=""/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableCoreContainerForIPI" Val="FALSE"/>
   </Configuration>
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
@@ -52,6 +54,12 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/src/detect_interlace.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/src/extract_video_infopacket_data.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -183,12 +191,14 @@
       </File>
       <File Path="$PPRDIR/test_bench/tb_convert_yCbCr_to_RGB.vhd">
         <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
       <File Path="$PPRDIR/test_bench/tb_audio_to_db.vhd">
         <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
@@ -208,7 +218,10 @@
       <Option Name="CompiledLib" Val="0"/>
     </Simulator>
     <Simulator Name="ModelSim">
-      <Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
     </Simulator>
     <Simulator Name="IES">
       <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
@@ -216,6 +229,12 @@
     <Simulator Name="VCS">
       <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
     </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
   </Simulators>
   <Runs Version="1" Minor="9">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
diff --git a/src/audio_meters.vhd b/src/audio_meters.vhd
index a5c5588..c935057 100644
--- a/src/audio_meters.vhd
+++ b/src/audio_meters.vhd
@@ -61,6 +61,8 @@ entity audio_meters is
            in_red    : in std_logic_vector(7 downto 0);
            in_green  : in std_logic_vector(7 downto 0);
            in_blue   : in std_logic_vector(7 downto 0);
+           is_interlaced   : in std_logic;
+           is_second_field : in std_logic;
             
            -----------------------------------
            -- VGA data to be converted to HDMI
diff --git a/src/detect_interlace.vhd b/src/detect_interlace.vhd
new file mode 100644
index 0000000..45fdb44
--- /dev/null
+++ b/src/detect_interlace.vhd
@@ -0,0 +1,118 @@
+----------------------------------------------------------------------------------
+-- Engineer: Mike Field <hamster@snap.net.nz> 
+-- 
+-- Module Name: detect_interlace - Behavioral
+--
+-- Description: Detect if the source is interlaced, and report what field is 
+--              being processed
+-- 
+-- Will need to make allowances for interlaced sources!
+------------------------------------------------------------------------------------
+-- The MIT License (MIT)
+-- 
+-- Copyright (c) 2015 Michael Alan Field
+-- 
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+-- 
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+-- 
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+------------------------------------------------------------------------------------
+----- Want to say thanks? ----------------------------------------------------------
+------------------------------------------------------------------------------------
+--
+-- This design has taken many hours - with the industry metric of 30 lines
+-- per day, it is equivalent to about 6 months of work. I'm more than happy
+-- to share it if you can make use of it. It is released under the MIT license,
+-- so you are not under any onus to say thanks, but....
+-- 
+-- If you what to say thanks for this design how about trying PayPal?
+--  Educational use - Enough for a beer
+--  Hobbyist use    - Enough for a pizza
+--  Research use    - Enough to take the family out to dinner
+--  Commercial use  - A weeks pay for an engineer (I wish!)
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity detect_interlace is
+    Port ( clk             : in STD_LOGIC;
+           hsync           : in std_logic;
+           vsync           : in std_logic;
+    	   is_interlaced   : out std_logic;
+	   	   is_second_field : out std_logic);
+end entity;
+
+architecture Behavioral of detect_interlace is
+	signal last_vsync     : std_logic := '0';
+	signal last_hsync     : std_logic := '0';
+	signal first_quarter  : unsigned(11 downto 0) := (others => '0');
+	signal last_quarter   : unsigned(11 downto 0) := (others => '0');
+	signal hcount         : unsigned(11 downto 0) := (others => '0');
+	signal last_vsync_pos : unsigned(11 downto 0) := (others => '0');
+	signal second_field   : std_logic := '0';
+begin
+clk_proc: process(clk)
+	begin
+		if rising_edge(clk) then
+			if last_vsync = '0' and vsync = '1' then
+				is_second_field <= '0';
+				if hcount > first_quarter and hcount < last_quarter then
+					-- The second field of an interlaced 
+                           -- frame is indicated when the vsync is
+	                      -- asserted in the middle of the scan line.
+					--
+					-- Also add a little check for a misbehaving source
+					if last_vsync_pos /= hcount then
+						is_interlaced   <= '1';
+						is_second_field <= '1';
+						second_field    <= '1';
+					else
+						is_interlaced   <= '1';
+						is_second_field <= '1';
+						second_field    <= '1';
+					end if;
+
+				else
+					-- If we see two 'field 1's in a row we 
+					-- switch back to indicating an 
+                    -- uninterlaced source
+					if second_field = '0' then
+						is_interlaced <= '0';
+					end if;									
+					is_second_field <= '0';
+					second_field    <= '0';
+				end if;
+				last_vsync_pos <= hcount;
+			else
+			end if;
+
+			if last_hsync = '0' and hsync = '1' then
+				hcount <= (others => '0');
+				first_quarter <= "00" & hcount(11 downto 2);
+				last_quarter <= hcount+1-hcount(11 downto 2);
+			else
+				hcount <= hcount +1;
+			end if;
+			last_vsync <= vsync;
+			last_hsync <= hsync;
+		end if;
+	end process;
+end architecture;
+		
\ No newline at end of file
diff --git a/src/extract_video_infopacket_data.vhd b/src/extract_video_infopacket_data.vhd
index 75110bc..5e1e11a 100644
--- a/src/extract_video_infopacket_data.vhd
+++ b/src/extract_video_infopacket_data.vhd
@@ -84,7 +84,7 @@ process(clk)
                 -- Move the incoming bits into a shift register
                 -----------------------------------------------
                 header_bits     <= adp_header_bit      & header_bits(header_bits'high downto 1);
-                frame_bits      <=  adp_frame_bit      & frame_bits(frame_bits'high   downto 1);
+                frame_bits      <= adp_frame_bit       & frame_bits(frame_bits'high   downto 1);
                 subpacket0_bits <= adp_subpacket0_bits & subpacket0_bits(subpacket0_bits'high downto 2);
                 updated         <= '1';  
             end if;
diff --git a/src/hdmi_design.vhd b/src/hdmi_design.vhd
index e1d9b31..4f9296d 100644
--- a/src/hdmi_design.vhd
+++ b/src/hdmi_design.vhd
@@ -123,12 +123,14 @@ architecture Behavioral of hdmi_design is
         -- VGA data recovered from HDMI
         -------------------------------
         in_hdmi_detected : out std_logic;
-        in_blank      : out std_logic;
-        in_hsync      : out std_logic;
-        in_vsync      : out std_logic;
-        in_red        : out std_logic_vector(7 downto 0);
-        in_green      : out std_logic_vector(7 downto 0);
-        in_blue       : out std_logic_vector(7 downto 0);
+        in_blank        : out std_logic;
+        in_hsync        : out std_logic;
+        in_vsync        : out std_logic;
+        in_red          : out std_logic_vector(7 downto 0);
+        in_green        : out std_logic_vector(7 downto 0);
+        in_blue         : out std_logic_vector(7 downto 0);
+        is_interlaced   : out std_logic;
+        is_second_field : out std_logic;
             
         -------------------------------------
         -- Audio Levels
@@ -160,6 +162,8 @@ architecture Behavioral of hdmi_design is
             in_red    : in std_logic_vector(7 downto 0);
             in_green  : in std_logic_vector(7 downto 0);
             in_blue   : in std_logic_vector(7 downto 0);
+            is_interlaced   : in  std_logic;
+            is_second_field : in  std_logic;
         
             -------------------
             -- Processed pixels
@@ -187,6 +191,8 @@ architecture Behavioral of hdmi_design is
     signal in_red    : std_logic_vector(7 downto 0);
     signal in_green  : std_logic_vector(7 downto 0);
     signal in_blue   : std_logic_vector(7 downto 0);
+    signal is_interlaced   : std_logic;
+    signal is_second_field : std_logic;
     signal out_blank : std_logic;
     signal out_hsync : std_logic;
     signal out_vsync : std_logic;
@@ -274,7 +280,8 @@ i_processing: pixel_processing Port map (
         in_red   => in_red,
         in_green => in_green,
         in_blue  => in_blue,    
-
+        is_interlaced => is_interlaced,
+        is_second_field => is_second_field,
         audio_channel => audio_channel,
         audio_de      => audio_de,
         audio_sample  => audio_sample,
diff --git a/src/hdmi_io.vhd b/src/hdmi_io.vhd
index 27b2675..3631a9f 100644
--- a/src/hdmi_io.vhd
+++ b/src/hdmi_io.vhd
@@ -95,6 +95,8 @@ entity hdmi_io is
         in_red    : out std_logic_vector(7 downto 0);
         in_green  : out std_logic_vector(7 downto 0);
         in_blue   : out std_logic_vector(7 downto 0);
+        is_interlaced   : out std_logic;
+        is_second_field : out std_logic;
         
         -----------------------------------
         -- VGA data to be converted to HDMI
@@ -160,7 +162,7 @@ architecture Behavioral of hdmi_io is
         adp_subpacket3_bits : out std_logic_vector(1 downto 0)
     );
     end component;
-
+    
     -----------------------------------------------------
     -- This is a half-baked solution to extracting data
     -- from ADP packets - just pipe the data thorugh and 
@@ -192,6 +194,8 @@ architecture Behavioral of hdmi_io is
     signal adp_subpacket1_bits : std_logic_vector(1 downto 0);
     signal adp_subpacket2_bits : std_logic_vector(1 downto 0);
     signal adp_subpacket3_bits : std_logic_vector(1 downto 0);
+    signal is_interlaced_i     : std_logic;
+    signal is_second_field_i   : std_logic;
 
     component extract_audio_samples is
     Port ( clk                 : in STD_LOGIC;
@@ -219,6 +223,14 @@ architecture Behavioral of hdmi_io is
     signal raw_ch1   : std_logic_vector(7 downto 0);  -- G or Y
     signal raw_ch0   : std_logic_vector(7 downto 0);   -- R or Cr
 
+    component detect_interlace is
+        Port ( clk : in STD_LOGIC;
+               hsync           : in  std_logic;
+               vsync           : in  std_logic;
+               is_interlaced   : out std_logic;
+               is_second_field : out std_logic);
+    end component;
+
     component expand_422_to_444 is
     Port ( clk : in STD_LOGIC;
         input_is_422 : in std_logic;
@@ -324,16 +336,17 @@ begin
     hdmi_rx_txen <= '1';
     hdmi_rx_cec  <= 'Z';
 
-    debug(7)          <= input_is_YCbCr;
-    debug(6)          <= input_is_422;
-    debug(5)          <= input_is_sRGB;        
-    debug(4 downto 3) <= (others => '0');
+    debug(7)          <= raw_hsync;
+    debug(6)          <= raw_vsync;
+    debug(5)          <= is_second_field_i;  
+    debug(4)          <= is_interlaced_i;      
+    debug(3 downto 0) <= (others => '0');
 
 i_edid_rom: edid_rom  port map (
              clk      => clk100,
              sclk_raw => hdmi_rx_scl,
              sdat_raw => hdmi_rx_sda,
-             edid_debug => debug(2 downto 0));
+             edid_debug => open);
 
     ---------------------
     -- Input buffers
@@ -411,6 +424,15 @@ i_expand_422_to_444: expand_422_to_444 Port map (
         out_W     => fourfourfour_W
     );
 
+    is_interlaced   <= is_interlaced_i;
+    is_second_field <= is_second_field_i; 
+i_detect_interlace: detect_interlace Port map ( 
+    clk             => pixel_clk_i,
+    hsync           => raw_hsync,
+    vsync           => raw_vsync,
+    is_interlaced   => is_interlaced_i,
+    is_second_field => is_second_field_i);
+
 i_conversion_to_RGB: conversion_to_RGB 
     port map (
            clk              => pixel_clk_i,
diff --git a/src/pixel_processing.vhd b/src/pixel_processing.vhd
index e2da145..66895f8 100644
--- a/src/pixel_processing.vhd
+++ b/src/pixel_processing.vhd
@@ -59,6 +59,8 @@ entity pixel_processing is
             in_red    : in std_logic_vector(7 downto 0);
             in_green  : in std_logic_vector(7 downto 0);
             in_blue   : in std_logic_vector(7 downto 0);
+            is_interlaced   : in std_logic;
+            is_second_field : in std_logic;
             -----------------------------------
             -- VGA data to be converted to HDMI
             -----------------------------------
@@ -104,6 +106,8 @@ architecture Behavioral of pixel_processing is
            in_red    : in std_logic_vector(7 downto 0);
            in_green  : in std_logic_vector(7 downto 0);
            in_blue   : in std_logic_vector(7 downto 0);
+           is_interlaced   : in std_logic;
+           is_second_field : in std_logic;
             
            -----------------------------------
            -- VGA data to be converted to HDMI
@@ -146,7 +150,9 @@ i_audio_meters: audio_meters Port map (
         in_red    => in_red,
         in_green  => in_green,
         in_blue   => in_blue,
-        
+        is_interlaced => is_interlaced,
+        is_second_field => is_second_field,
+       
         out_blank => out_blank,
         out_hsync => out_hsync,
         out_vsync => out_vsync,