118 lines
No EOL
4.6 KiB
VHDL
118 lines
No EOL
4.6 KiB
VHDL
----------------------------------------------------------------------------------
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-- Engineer: Mike Field <hamster@snap.net.nz>
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--
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-- Module Name: detect_interlace - Behavioral
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--
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-- Description: Detect if the source is interlaced, and report what field is
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-- being processed
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--
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-- Will need to make allowances for interlaced sources!
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------------------------------------------------------------------------------------
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-- The MIT License (MIT)
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--
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-- Copyright (c) 2015 Michael Alan Field
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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------------------------------------------------------------------------------------
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----- Want to say thanks? ----------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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-- This design has taken many hours - with the industry metric of 30 lines
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-- per day, it is equivalent to about 6 months of work. I'm more than happy
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-- to share it if you can make use of it. It is released under the MIT license,
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-- so you are not under any onus to say thanks, but....
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--
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-- If you what to say thanks for this design how about trying PayPal?
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-- Educational use - Enough for a beer
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-- Hobbyist use - Enough for a pizza
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-- Research use - Enough to take the family out to dinner
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-- Commercial use - A weeks pay for an engineer (I wish!)
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity detect_interlace is
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Port ( clk : in STD_LOGIC;
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hsync : in std_logic;
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vsync : in std_logic;
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is_interlaced : out std_logic;
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is_second_field : out std_logic);
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end entity;
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architecture Behavioral of detect_interlace is
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signal last_vsync : std_logic := '0';
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signal last_hsync : std_logic := '0';
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signal first_quarter : unsigned(11 downto 0) := (others => '0');
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signal last_quarter : unsigned(11 downto 0) := (others => '0');
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signal hcount : unsigned(11 downto 0) := (others => '0');
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signal last_vsync_pos : unsigned(11 downto 0) := (others => '0');
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signal second_field : std_logic := '0';
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begin
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clk_proc: process(clk)
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begin
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if rising_edge(clk) then
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if last_vsync = '0' and vsync = '1' then
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is_second_field <= '0';
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if hcount > first_quarter and hcount < last_quarter then
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-- The second field of an interlaced
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-- frame is indicated when the vsync is
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-- asserted in the middle of the scan line.
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--
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-- Also add a little check for a misbehaving source
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if last_vsync_pos /= hcount then
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is_interlaced <= '1';
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is_second_field <= '1';
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second_field <= '1';
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else
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is_interlaced <= '1';
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is_second_field <= '1';
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second_field <= '1';
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end if;
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else
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-- If we see two 'field 1's in a row we
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-- switch back to indicating an
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-- uninterlaced source
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if second_field = '0' then
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is_interlaced <= '0';
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end if;
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is_second_field <= '0';
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second_field <= '0';
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end if;
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last_vsync_pos <= hcount;
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else
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end if;
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if last_hsync = '0' and hsync = '1' then
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hcount <= (others => '0');
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first_quarter <= "00" & hcount(11 downto 2);
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last_quarter <= hcount+1-hcount(11 downto 2);
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else
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hcount <= hcount +1;
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end if;
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last_vsync <= vsync;
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last_hsync <= hsync;
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end if;
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end process;
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end architecture;
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