SPI regfile WIP
This commit is contained in:
jaseg
parent
1daef761b6
commit
9a1f05363a
6 changed files with 426 additions and 2 deletions
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@ -42,7 +42,7 @@
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<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="WTXSimLaunchSim" Val="435"/>
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<Option Name="WTXSimLaunchSim" Val="458"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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@ -245,6 +245,14 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/src/spi_regfile.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="hdmi_design"/>
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@ -266,8 +274,16 @@
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/test_bench/spi_regfile_tb.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/test_bench/spi_core_tb.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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@ -373,9 +389,14 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/spi_regfile_tb_behav.wcfg">
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<FileInfo>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="spi_core_tb"/>
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<Option Name="TopModule" Val="spi_regfile_tb"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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@ -390,6 +411,7 @@
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<Option Name="XSimWcfgFile" Val="$PPRDIR/term_renderer_tb_behav.wcfg"/>
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<Option Name="XSimWcfgFile" Val="$PPRDIR/term_emu_tb_behav.wcfg"/>
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<Option Name="XSimWcfgFile" Val="$PPRDIR/spi_core_tb_behav.wcfg"/>
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<Option Name="XSimWcfgFile" Val="$PPRDIR/spi_regfile_tb_behav.wcfg"/>
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<Option Name="xsim.simulate.runtime" Val="10ms"/>
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<Option Name="NLNetlistMode" Val="funcsim"/>
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</Config>
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181
spi_regfile_tb_behav.wcfg
Normal file
181
spi_regfile_tb_behav.wcfg
Normal file
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@ -0,0 +1,181 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<wave_config>
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<wave_state>
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</wave_state>
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<db_ref_list>
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<db_ref path="spi_regfile_tb_behav.wdb" id="1">
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<top_modules>
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<top_module name="glbl" />
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<top_module name="spi_regfile_tb" />
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</top_modules>
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</db_ref>
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</db_ref_list>
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<zoom_setting>
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<ZoomStartTime time="731666fs"></ZoomStartTime>
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<ZoomEndTime time="5121667fs"></ZoomEndTime>
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<Cursor1Time time="4390000fs"></Cursor1Time>
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</zoom_setting>
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<column_width_setting>
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<NameColumnWidth column_width="175"></NameColumnWidth>
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<ValueColumnWidth column_width="154"></ValueColumnWidth>
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</column_width_setting>
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<WVObjectSize size="34" />
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<wvobject fp_name="/spi_regfile_tb/testcase" type="array">
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<obj_property name="ElementShortName">testcase[31:0]</obj_property>
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<obj_property name="ObjectShortName">testcase[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/clk" type="logic">
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<obj_property name="ElementShortName">clk</obj_property>
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<obj_property name="ObjectShortName">clk</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/rst" type="logic">
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<obj_property name="ElementShortName">rst</obj_property>
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<obj_property name="ObjectShortName">rst</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/sck" type="logic">
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<obj_property name="ElementShortName">sck</obj_property>
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<obj_property name="ObjectShortName">sck</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/sdi" type="logic">
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<obj_property name="ElementShortName">sdi</obj_property>
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<obj_property name="ObjectShortName">sdi</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/sdo" type="logic">
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<obj_property name="ElementShortName">sdo</obj_property>
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<obj_property name="ObjectShortName">sdo</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/ncs" type="logic">
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<obj_property name="ElementShortName">ncs</obj_property>
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<obj_property name="ObjectShortName">ncs</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_data_in" type="array">
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<obj_property name="ElementShortName">spi_data_in[15:0]</obj_property>
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<obj_property name="ObjectShortName">spi_data_in[15:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_data_out" type="array">
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<obj_property name="ElementShortName">spi_data_out[15:0]</obj_property>
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<obj_property name="ObjectShortName">spi_data_out[15:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_status_word" type="array">
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<obj_property name="ElementShortName">spi_status_word[15:0]</obj_property>
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<obj_property name="ObjectShortName">spi_status_word[15:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_cmd_word" type="array">
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<obj_property name="ElementShortName">spi_cmd_word[15:0]</obj_property>
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<obj_property name="ObjectShortName">spi_cmd_word[15:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_cmd_begin" type="logic">
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<obj_property name="ElementShortName">spi_cmd_begin</obj_property>
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<obj_property name="ObjectShortName">spi_cmd_begin</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_cmd_active" type="logic">
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<obj_property name="ElementShortName">spi_cmd_active</obj_property>
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<obj_property name="ObjectShortName">spi_cmd_active</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_cmd_step" type="logic">
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<obj_property name="ElementShortName">spi_cmd_step</obj_property>
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<obj_property name="ObjectShortName">spi_cmd_step</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_cmd_idx" type="array">
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<obj_property name="ElementShortName">spi_cmd_idx[19:0]</obj_property>
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<obj_property name="ObjectShortName">spi_cmd_idx[19:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/i" type="array">
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<obj_property name="ElementShortName">i[31:0]</obj_property>
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<obj_property name="ObjectShortName">i[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/j" type="array">
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<obj_property name="ElementShortName">j[31:0]</obj_property>
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<obj_property name="ObjectShortName">j[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/k" type="array">
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<obj_property name="ElementShortName">k[31:0]</obj_property>
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<obj_property name="ObjectShortName">k[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/sim_rxdata" type="array">
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<obj_property name="ElementShortName">sim_rxdata[1:4][15:0]</obj_property>
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<obj_property name="ObjectShortName">sim_rxdata[1:4][15:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/sim_txdata" type="array">
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<obj_property name="ElementShortName">sim_txdata[1:4][15:0]</obj_property>
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<obj_property name="ObjectShortName">sim_txdata[1:4][15:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/sim_txbuf" type="array">
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<obj_property name="ElementShortName">sim_txbuf[15:0]</obj_property>
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<obj_property name="ObjectShortName">sim_txbuf[15:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/period" type="array">
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<obj_property name="ElementShortName">period[31:0]</obj_property>
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<obj_property name="ObjectShortName">period[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/WORDSIZE" type="array">
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<obj_property name="ElementShortName">WORDSIZE[31:0]</obj_property>
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<obj_property name="ObjectShortName">WORDSIZE[31:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/data_out" type="array">
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<obj_property name="ElementShortName">data_out[15:0]</obj_property>
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<obj_property name="ObjectShortName">data_out[15:0]</obj_property>
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<obj_property name="CustomSignalColor">#FFFF00</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/data_out_valid" type="logic">
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<obj_property name="ElementShortName">data_out_valid</obj_property>
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<obj_property name="ObjectShortName">data_out_valid</obj_property>
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<obj_property name="CustomSignalColor">#FFFF00</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/data_in" type="array">
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<obj_property name="ElementShortName">data_in[15:0]</obj_property>
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<obj_property name="ObjectShortName">data_in[15:0]</obj_property>
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<obj_property name="CustomSignalColor">#FFFF00</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/data_in_valid" type="logic">
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<obj_property name="ElementShortName">data_in_valid</obj_property>
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<obj_property name="ObjectShortName">data_in_valid</obj_property>
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<obj_property name="CustomSignalColor">#FFFF00</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/sck_rising" type="logic">
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<obj_property name="ElementShortName">sck_rising</obj_property>
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<obj_property name="ObjectShortName">sck_rising</obj_property>
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<obj_property name="CustomSignalColor">#FFFF00</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/sck_falling" type="logic">
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<obj_property name="ElementShortName">sck_falling</obj_property>
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<obj_property name="ObjectShortName">sck_falling</obj_property>
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<obj_property name="CustomSignalColor">#FFFF00</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/tx_buf" type="array">
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<obj_property name="ElementShortName">tx_buf[15:0]</obj_property>
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<obj_property name="ObjectShortName">tx_buf[15:0]</obj_property>
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<obj_property name="CustomSignalColor">#FFFF00</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/tx_buf_next" type="array">
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<obj_property name="ElementShortName">tx_buf_next[15:0]</obj_property>
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<obj_property name="ObjectShortName">tx_buf_next[15:0]</obj_property>
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<obj_property name="CustomSignalColor">#FFFF00</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/is_spi_cmd_word" type="logic">
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<obj_property name="ElementShortName">is_spi_cmd_word</obj_property>
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<obj_property name="ObjectShortName">is_spi_cmd_word</obj_property>
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<obj_property name="CustomSignalColor">#FAAFBE</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_cs_rising" type="logic">
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<obj_property name="ElementShortName">spi_core_cs_rising</obj_property>
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<obj_property name="ObjectShortName">spi_core_cs_rising</obj_property>
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<obj_property name="CustomSignalColor">#FAAFBE</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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</wvobject>
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<wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_cs_falling" type="logic">
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<obj_property name="ElementShortName">spi_core_cs_falling</obj_property>
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<obj_property name="ObjectShortName">spi_core_cs_falling</obj_property>
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<obj_property name="CustomSignalColor">#FAAFBE</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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</wvobject>
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</wave_config>
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@ -1,3 +1,4 @@
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`timescale 1ns / 1ps
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module spi_core(
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input clk, rst,
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85
src/spi_regfile.v
Normal file
85
src/spi_regfile.v
Normal file
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@ -0,0 +1,85 @@
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`timescale 1ns / 1ps
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module spi_regfile(
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input clk, rst,
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input sck, sdi, ncs,
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output sdo,
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input [15:0] spi_data_in,
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output reg [15:0] spi_data_out,
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input [15:0] spi_status_word,
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output reg [15:0] spi_cmd_word,
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output reg spi_cmd_begin,
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output reg spi_cmd_active,
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output reg spi_cmd_step,
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output reg [19:0] spi_cmd_idx
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);
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wire spi_core_cs_rising, spi_core_cs_falling;
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reg [15:0] spi_core_data_in;
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reg spi_core_data_in_valid;
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wire [15:0] spi_core_data_out;
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wire spi_core_data_out_valid;
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reg is_spi_cmd_word;
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always @(posedge clk) begin
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spi_core_data_in_valid <= 0;
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spi_cmd_begin <= 0;
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spi_cmd_step <= 0;
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spi_core_data_in <= spi_status_word;
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if (rst) begin
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is_spi_cmd_word <= 1;
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spi_cmd_active <= 0;
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spi_cmd_idx <= 0;
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end else begin
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if (spi_core_cs_rising) begin
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is_spi_cmd_word <= 1;
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spi_cmd_active <= 0;
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end
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if (ncs) begin
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/* constantly refresh status word */
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spi_core_data_in_valid <= 1;
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end
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if (spi_core_data_out_valid) begin
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spi_core_data_in <= spi_data_in;
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spi_core_data_in_valid <= 1;
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if (is_spi_cmd_word) begin
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spi_cmd_word <= spi_core_data_out;
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spi_cmd_idx <= 0;
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spi_cmd_active <= 1;
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spi_cmd_begin <= 1;
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is_spi_cmd_word <= 0;
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end else begin
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spi_cmd_idx <= spi_cmd_idx + 1;
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spi_cmd_step <= 1;
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spi_data_out <= spi_core_data_out;
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end
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end
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end
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end
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spi_core #(.WORDSIZE(16)) spi_core_dut (
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.clk(clk), .rst(rst),
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.sck(sck), .sdi(sdi), .sdo(sdo), .ncs(ncs),
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.cs_rising(spi_core_cs_rising),
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.cs_falling(spi_core_cs_falling),
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.data_out(spi_core_data_out),
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.data_out_valid(spi_core_data_out_valid),
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.data_in(spi_core_data_in),
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.data_in_valid(spi_core_data_in_valid)
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);
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endmodule
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@ -1,3 +1,4 @@
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`timescale 1ns / 1ps
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module spi_core_tb();
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134
test_bench/spi_regfile_tb.v
Normal file
134
test_bench/spi_regfile_tb.v
Normal file
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@ -0,0 +1,134 @@
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`timescale 1ns / 1ps
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module spi_regfile_tb();
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localparam period = 10;
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parameter WORDSIZE = 16;
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reg clk, rst;
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reg sck, sdi, ncs;
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wire sdo;
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reg [15:0] spi_data_in;
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wire [15:0] spi_data_out;
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||||
wire [15:0] spi_status_word = 16'h3141;
|
||||
wire [15:0] spi_cmd_word;
|
||||
wire spi_cmd_begin, spi_cmd_active, spi_cmd_step;
|
||||
wire [19:0] spi_cmd_idx;
|
||||
|
||||
initial begin
|
||||
clk = 0;
|
||||
/* rst set below */
|
||||
sck = 0;
|
||||
sdi = 0;
|
||||
ncs = 1;
|
||||
forever #period clk = ~clk;
|
||||
end
|
||||
|
||||
integer i;
|
||||
integer j;
|
||||
integer k;
|
||||
integer testcase;
|
||||
reg [WORDSIZE-1:0] sim_rxdata [1:4];
|
||||
reg [WORDSIZE-1:0] sim_txdata [1:4];
|
||||
reg [WORDSIZE-1:0] sim_txbuf;
|
||||
initial begin
|
||||
sim_rxdata[1] = 16'h523a;
|
||||
sim_rxdata[2] = 16'hbeef;
|
||||
sim_rxdata[3] = 16'h7721;
|
||||
sim_rxdata[4] = 16'h0108;
|
||||
|
||||
sim_txdata[1] = 16'h1234;
|
||||
sim_txdata[2] = 16'h5678;
|
||||
sim_txdata[3] = 16'h9abc;
|
||||
sim_txdata[4] = 16'hdef9;
|
||||
|
||||
for (j=1; j<=4; j=j+1) begin
|
||||
$display("TC-%d: rx/tx %d word", j, j);
|
||||
testcase = j;
|
||||
|
||||
rst = 1;
|
||||
repeat(2) @(posedge clk);
|
||||
rst = 0;
|
||||
@(posedge clk);
|
||||
|
||||
spi_data_in = sim_txdata[1];
|
||||
@(posedge clk);
|
||||
|
||||
ncs = 0;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
if (spi_cmd_begin) $finish;
|
||||
if (spi_cmd_active) $finish;
|
||||
if (spi_cmd_step) $finish;
|
||||
|
||||
for (k=0; k<j; k=k+1) begin
|
||||
sim_txbuf = 0;
|
||||
|
||||
for (i=0; i<WORDSIZE; i=i+1) begin
|
||||
sdi = sim_rxdata[k+1][WORDSIZE-1-i];
|
||||
sck = 0;
|
||||
if (spi_cmd_step) $finish;
|
||||
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
|
||||
sck = 1;
|
||||
sim_txbuf[WORDSIZE-1-i] = sdo;
|
||||
|
||||
if (i == WORDSIZE-1) begin
|
||||
spi_data_in = sim_txdata[k+2];
|
||||
end
|
||||
|
||||
if (spi_cmd_step) $finish;
|
||||
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
end
|
||||
|
||||
@(posedge clk);
|
||||
|
||||
if (!spi_cmd_active) $finish;
|
||||
if (k == 0 && !spi_cmd_begin) $finish;
|
||||
if (k > 0 && spi_cmd_begin) $finish;
|
||||
if (k == 0 && spi_cmd_step) $finish;
|
||||
if (k > 0 && !spi_cmd_step) $finish;
|
||||
if (spi_cmd_word != sim_rxdata[1]) $finish;
|
||||
if (k > 0 && spi_data_out != sim_rxdata[k+1]) $finish;
|
||||
if (k == 0 && sim_txbuf != 16'h3141) $finish;
|
||||
if (k > 0 && sim_txbuf != sim_txdata[k]) $finish;
|
||||
end
|
||||
|
||||
sck = 0;
|
||||
@(posedge clk);
|
||||
ncs = 1;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
|
||||
if (spi_cmd_active) $finish;
|
||||
if (spi_cmd_step) $finish;
|
||||
if (spi_cmd_begin) $finish;
|
||||
|
||||
repeat(10) @(posedge clk);
|
||||
end
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
spi_regfile spi_regfile_dut (
|
||||
.clk(clk), .rst(rst),
|
||||
|
||||
.sck(sck), .sdi(sdi), .sdo(sdo), .ncs(ncs),
|
||||
|
||||
.spi_data_in(spi_data_in),
|
||||
.spi_data_out(spi_data_out),
|
||||
|
||||
.spi_status_word(spi_status_word),
|
||||
.spi_cmd_word(spi_cmd_word),
|
||||
.spi_cmd_begin(spi_cmd_begin),
|
||||
.spi_cmd_active(spi_cmd_active),
|
||||
.spi_cmd_step(spi_cmd_step),
|
||||
.spi_cmd_idx(spi_cmd_idx)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue