From 9a1f05363ac92711540888ae3e4aa1347e16a4c6 Mon Sep 17 00:00:00 2001
From: jaseg <git-bigdata-wsl-arch@jaseg.de>
Date: Wed, 23 Jun 2021 13:31:52 +0200
Subject: [PATCH] SPI regfile WIP

---
 Artix-7-HDMI-processing.xpr |  26 +++++-
 spi_regfile_tb_behav.wcfg   | 181 ++++++++++++++++++++++++++++++++++++
 src/spi_core.v              |   1 +
 src/spi_regfile.v           |  85 +++++++++++++++++
 test_bench/spi_core_tb.v    |   1 +
 test_bench/spi_regfile_tb.v | 134 ++++++++++++++++++++++++++
 6 files changed, 426 insertions(+), 2 deletions(-)
 create mode 100644 spi_regfile_tb_behav.wcfg
 create mode 100644 src/spi_regfile.v
 create mode 100644 test_bench/spi_regfile_tb.v

diff --git a/Artix-7-HDMI-processing.xpr b/Artix-7-HDMI-processing.xpr
index 6c0ad59..492b92a 100644
--- a/Artix-7-HDMI-processing.xpr
+++ b/Artix-7-HDMI-processing.xpr
@@ -42,7 +42,7 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="WTXSimLaunchSim" Val="435"/>
+    <Option Name="WTXSimLaunchSim" Val="458"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -245,6 +245,14 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/src/spi_regfile.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="hdmi_design"/>
@@ -266,8 +274,16 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
       <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/test_bench/spi_regfile_tb.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/test_bench/spi_core_tb.v">
         <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
@@ -373,9 +389,14 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/spi_regfile_tb_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="spi_core_tb"/>
+        <Option Name="TopModule" Val="spi_regfile_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
@@ -390,6 +411,7 @@
         <Option Name="XSimWcfgFile" Val="$PPRDIR/term_renderer_tb_behav.wcfg"/>
         <Option Name="XSimWcfgFile" Val="$PPRDIR/term_emu_tb_behav.wcfg"/>
         <Option Name="XSimWcfgFile" Val="$PPRDIR/spi_core_tb_behav.wcfg"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/spi_regfile_tb_behav.wcfg"/>
         <Option Name="xsim.simulate.runtime" Val="10ms"/>
         <Option Name="NLNetlistMode" Val="funcsim"/>
       </Config>
diff --git a/spi_regfile_tb_behav.wcfg b/spi_regfile_tb_behav.wcfg
new file mode 100644
index 0000000..4735b15
--- /dev/null
+++ b/spi_regfile_tb_behav.wcfg
@@ -0,0 +1,181 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="spi_regfile_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="spi_regfile_tb" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="731666fs"></ZoomStartTime>
+      <ZoomEndTime time="5121667fs"></ZoomEndTime>
+      <Cursor1Time time="4390000fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="175"></NameColumnWidth>
+      <ValueColumnWidth column_width="154"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="34" />
+   <wvobject fp_name="/spi_regfile_tb/testcase" type="array">
+      <obj_property name="ElementShortName">testcase[31:0]</obj_property>
+      <obj_property name="ObjectShortName">testcase[31:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/clk" type="logic">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/rst" type="logic">
+      <obj_property name="ElementShortName">rst</obj_property>
+      <obj_property name="ObjectShortName">rst</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/sck" type="logic">
+      <obj_property name="ElementShortName">sck</obj_property>
+      <obj_property name="ObjectShortName">sck</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/sdi" type="logic">
+      <obj_property name="ElementShortName">sdi</obj_property>
+      <obj_property name="ObjectShortName">sdi</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/sdo" type="logic">
+      <obj_property name="ElementShortName">sdo</obj_property>
+      <obj_property name="ObjectShortName">sdo</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/ncs" type="logic">
+      <obj_property name="ElementShortName">ncs</obj_property>
+      <obj_property name="ObjectShortName">ncs</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_data_in" type="array">
+      <obj_property name="ElementShortName">spi_data_in[15:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_data_in[15:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_data_out" type="array">
+      <obj_property name="ElementShortName">spi_data_out[15:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_data_out[15:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_status_word" type="array">
+      <obj_property name="ElementShortName">spi_status_word[15:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_status_word[15:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_cmd_word" type="array">
+      <obj_property name="ElementShortName">spi_cmd_word[15:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_cmd_word[15:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_cmd_begin" type="logic">
+      <obj_property name="ElementShortName">spi_cmd_begin</obj_property>
+      <obj_property name="ObjectShortName">spi_cmd_begin</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_cmd_active" type="logic">
+      <obj_property name="ElementShortName">spi_cmd_active</obj_property>
+      <obj_property name="ObjectShortName">spi_cmd_active</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_cmd_step" type="logic">
+      <obj_property name="ElementShortName">spi_cmd_step</obj_property>
+      <obj_property name="ObjectShortName">spi_cmd_step</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_cmd_idx" type="array">
+      <obj_property name="ElementShortName">spi_cmd_idx[19:0]</obj_property>
+      <obj_property name="ObjectShortName">spi_cmd_idx[19:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/i" type="array">
+      <obj_property name="ElementShortName">i[31:0]</obj_property>
+      <obj_property name="ObjectShortName">i[31:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/j" type="array">
+      <obj_property name="ElementShortName">j[31:0]</obj_property>
+      <obj_property name="ObjectShortName">j[31:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/k" type="array">
+      <obj_property name="ElementShortName">k[31:0]</obj_property>
+      <obj_property name="ObjectShortName">k[31:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/sim_rxdata" type="array">
+      <obj_property name="ElementShortName">sim_rxdata[1:4][15:0]</obj_property>
+      <obj_property name="ObjectShortName">sim_rxdata[1:4][15:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/sim_txdata" type="array">
+      <obj_property name="ElementShortName">sim_txdata[1:4][15:0]</obj_property>
+      <obj_property name="ObjectShortName">sim_txdata[1:4][15:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/sim_txbuf" type="array">
+      <obj_property name="ElementShortName">sim_txbuf[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sim_txbuf[15:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/period" type="array">
+      <obj_property name="ElementShortName">period[31:0]</obj_property>
+      <obj_property name="ObjectShortName">period[31:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/WORDSIZE" type="array">
+      <obj_property name="ElementShortName">WORDSIZE[31:0]</obj_property>
+      <obj_property name="ObjectShortName">WORDSIZE[31:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/data_out" type="array">
+      <obj_property name="ElementShortName">data_out[15:0]</obj_property>
+      <obj_property name="ObjectShortName">data_out[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/data_out_valid" type="logic">
+      <obj_property name="ElementShortName">data_out_valid</obj_property>
+      <obj_property name="ObjectShortName">data_out_valid</obj_property>
+      <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/data_in" type="array">
+      <obj_property name="ElementShortName">data_in[15:0]</obj_property>
+      <obj_property name="ObjectShortName">data_in[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/data_in_valid" type="logic">
+      <obj_property name="ElementShortName">data_in_valid</obj_property>
+      <obj_property name="ObjectShortName">data_in_valid</obj_property>
+      <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/sck_rising" type="logic">
+      <obj_property name="ElementShortName">sck_rising</obj_property>
+      <obj_property name="ObjectShortName">sck_rising</obj_property>
+      <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/sck_falling" type="logic">
+      <obj_property name="ElementShortName">sck_falling</obj_property>
+      <obj_property name="ObjectShortName">sck_falling</obj_property>
+      <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/tx_buf" type="array">
+      <obj_property name="ElementShortName">tx_buf[15:0]</obj_property>
+      <obj_property name="ObjectShortName">tx_buf[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_dut/tx_buf_next" type="array">
+      <obj_property name="ElementShortName">tx_buf_next[15:0]</obj_property>
+      <obj_property name="ObjectShortName">tx_buf_next[15:0]</obj_property>
+      <obj_property name="CustomSignalColor">#FFFF00</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/is_spi_cmd_word" type="logic">
+      <obj_property name="ElementShortName">is_spi_cmd_word</obj_property>
+      <obj_property name="ObjectShortName">is_spi_cmd_word</obj_property>
+      <obj_property name="CustomSignalColor">#FAAFBE</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_cs_rising" type="logic">
+      <obj_property name="ElementShortName">spi_core_cs_rising</obj_property>
+      <obj_property name="ObjectShortName">spi_core_cs_rising</obj_property>
+      <obj_property name="CustomSignalColor">#FAAFBE</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spi_regfile_tb/spi_regfile_dut/spi_core_cs_falling" type="logic">
+      <obj_property name="ElementShortName">spi_core_cs_falling</obj_property>
+      <obj_property name="ObjectShortName">spi_core_cs_falling</obj_property>
+      <obj_property name="CustomSignalColor">#FAAFBE</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+</wave_config>
diff --git a/src/spi_core.v b/src/spi_core.v
index bf828ab..41b66e0 100644
--- a/src/spi_core.v
+++ b/src/spi_core.v
@@ -1,3 +1,4 @@
+`timescale 1ns / 1ps
 	
 module spi_core(
 	input clk, rst,
diff --git a/src/spi_regfile.v b/src/spi_regfile.v
new file mode 100644
index 0000000..f211dac
--- /dev/null
+++ b/src/spi_regfile.v
@@ -0,0 +1,85 @@
+`timescale 1ns / 1ps
+
+module spi_regfile(
+	input clk, rst,
+	
+	input sck, sdi, ncs,
+	output sdo,
+	
+	input [15:0] spi_data_in,
+	output reg [15:0] spi_data_out,
+	
+	input [15:0] spi_status_word,
+	output reg [15:0] spi_cmd_word,
+	output reg spi_cmd_begin,
+	output reg spi_cmd_active,
+	output reg spi_cmd_step,
+	output reg [19:0] spi_cmd_idx
+);
+
+wire spi_core_cs_rising, spi_core_cs_falling;
+reg [15:0] spi_core_data_in;
+reg spi_core_data_in_valid;
+wire [15:0] spi_core_data_out;
+wire spi_core_data_out_valid;
+
+reg is_spi_cmd_word;
+
+always @(posedge clk) begin
+	spi_core_data_in_valid <= 0;
+	spi_cmd_begin <= 0;
+	spi_cmd_step <= 0;
+	spi_core_data_in <= spi_status_word;
+
+	if (rst) begin
+		is_spi_cmd_word <= 1;
+		spi_cmd_active <= 0;
+		spi_cmd_idx <= 0;
+		
+	end else begin
+		
+		if (spi_core_cs_rising) begin
+			is_spi_cmd_word <= 1;
+			spi_cmd_active <= 0;
+		end
+		
+		if (ncs) begin
+			/* constantly refresh status word */
+			spi_core_data_in_valid <= 1;
+		end
+		
+		if (spi_core_data_out_valid) begin
+			spi_core_data_in <= spi_data_in;
+			spi_core_data_in_valid <= 1;
+			
+			if (is_spi_cmd_word) begin
+				spi_cmd_word <= spi_core_data_out;
+				spi_cmd_idx <= 0;
+				spi_cmd_active <= 1;
+				spi_cmd_begin <= 1;
+				is_spi_cmd_word <= 0;
+				
+			end else begin
+				 spi_cmd_idx <= spi_cmd_idx + 1;
+				 spi_cmd_step <= 1;
+				 spi_data_out <= spi_core_data_out;
+			end
+		end
+	end
+end
+
+spi_core #(.WORDSIZE(16)) spi_core_dut (
+	.clk(clk), .rst(rst),
+	
+	.sck(sck), .sdi(sdi), .sdo(sdo), .ncs(ncs),
+	
+	.cs_rising(spi_core_cs_rising),
+	.cs_falling(spi_core_cs_falling),
+	
+	.data_out(spi_core_data_out),
+	.data_out_valid(spi_core_data_out_valid),
+	.data_in(spi_core_data_in),
+	.data_in_valid(spi_core_data_in_valid)
+);
+
+endmodule
diff --git a/test_bench/spi_core_tb.v b/test_bench/spi_core_tb.v
index fff7fa1..4a2e6a2 100644
--- a/test_bench/spi_core_tb.v
+++ b/test_bench/spi_core_tb.v
@@ -1,3 +1,4 @@
+`timescale 1ns / 1ps
 
 module spi_core_tb();
 
diff --git a/test_bench/spi_regfile_tb.v b/test_bench/spi_regfile_tb.v
new file mode 100644
index 0000000..9831475
--- /dev/null
+++ b/test_bench/spi_regfile_tb.v
@@ -0,0 +1,134 @@
+`timescale 1ns / 1ps
+
+module spi_regfile_tb();
+
+localparam period = 10;
+parameter WORDSIZE = 16;
+reg clk, rst;
+
+reg sck, sdi, ncs;
+wire sdo;
+
+reg [15:0] spi_data_in;
+wire [15:0] spi_data_out;
+wire [15:0] spi_status_word = 16'h3141;
+wire [15:0] spi_cmd_word;
+wire spi_cmd_begin, spi_cmd_active, spi_cmd_step;
+wire [19:0] spi_cmd_idx;
+
+initial begin
+	clk = 0;
+	/* rst set below */
+	sck = 0;
+	sdi = 0;
+	ncs = 1;
+	forever #period clk = ~clk;
+end
+
+integer i;
+integer j;
+integer k;
+integer testcase;
+reg [WORDSIZE-1:0] sim_rxdata [1:4];
+reg [WORDSIZE-1:0] sim_txdata [1:4];
+reg [WORDSIZE-1:0] sim_txbuf;
+initial begin
+	sim_rxdata[1] = 16'h523a;
+	sim_rxdata[2] = 16'hbeef;
+	sim_rxdata[3] = 16'h7721;
+	sim_rxdata[4] = 16'h0108;
+	
+	sim_txdata[1] = 16'h1234;
+	sim_txdata[2] = 16'h5678;
+	sim_txdata[3] = 16'h9abc;
+	sim_txdata[4] = 16'hdef9;
+	
+	for (j=1; j<=4; j=j+1) begin
+		$display("TC-%d: rx/tx %d word", j, j);
+		testcase = j;
+	
+		rst = 1;
+		repeat(2) @(posedge clk);
+		rst = 0;
+		@(posedge clk);
+		
+		spi_data_in = sim_txdata[1];
+		@(posedge clk);
+		
+		ncs = 0;
+		@(posedge clk);
+		@(posedge clk);
+		if (spi_cmd_begin) $finish;
+		if (spi_cmd_active) $finish;
+		if (spi_cmd_step) $finish;
+		
+		for (k=0; k<j; k=k+1) begin
+			sim_txbuf = 0;
+			
+			for (i=0; i<WORDSIZE; i=i+1) begin
+				sdi = sim_rxdata[k+1][WORDSIZE-1-i];
+				sck = 0;
+				if (spi_cmd_step) $finish;
+				
+				@(posedge clk);
+				@(posedge clk);
+				
+				sck = 1;
+				sim_txbuf[WORDSIZE-1-i] = sdo;
+				
+				if (i == WORDSIZE-1) begin
+					spi_data_in = sim_txdata[k+2];
+				end
+				
+				if (spi_cmd_step) $finish;
+				
+				@(posedge clk);
+				@(posedge clk);
+			end
+			
+			@(posedge clk);
+			
+			if (!spi_cmd_active) $finish;
+			if (k == 0 && !spi_cmd_begin) $finish;
+			if (k > 0 && spi_cmd_begin) $finish;
+			if (k == 0 && spi_cmd_step) $finish;
+			if (k > 0 && !spi_cmd_step) $finish;
+			if (spi_cmd_word != sim_rxdata[1]) $finish;
+			if (k > 0 && spi_data_out != sim_rxdata[k+1]) $finish;
+			if (k == 0 && sim_txbuf != 16'h3141) $finish;
+			if (k > 0 && sim_txbuf != sim_txdata[k]) $finish;
+		end
+		
+		sck = 0;
+		@(posedge clk);
+		ncs = 1;
+		@(posedge clk);
+		@(posedge clk);
+		
+		if (spi_cmd_active) $finish;
+		if (spi_cmd_step) $finish;
+		if (spi_cmd_begin) $finish;
+		
+		repeat(10) @(posedge clk);
+	end
+
+	$finish;
+end
+
+spi_regfile spi_regfile_dut (
+	.clk(clk), .rst(rst),
+	
+	.sck(sck), .sdi(sdi), .sdo(sdo), .ncs(ncs),
+	
+	.spi_data_in(spi_data_in),
+	.spi_data_out(spi_data_out),
+	
+	.spi_status_word(spi_status_word),
+	.spi_cmd_word(spi_cmd_word),
+	.spi_cmd_begin(spi_cmd_begin),
+	.spi_cmd_active(spi_cmd_active),
+	.spi_cmd_step(spi_cmd_step),
+	.spi_cmd_idx(spi_cmd_idx)
+);
+
+endmodule
\ No newline at end of file