85 lines
1.8 KiB
Verilog
85 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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module spi_regfile(
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input clk, rst,
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input sck, sdi, ncs,
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output sdo,
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input [15:0] spi_data_in,
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output reg [15:0] spi_data_out,
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input [15:0] spi_status_word,
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output reg [15:0] spi_cmd_word,
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output reg spi_cmd_begin,
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output reg spi_cmd_active,
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output reg spi_cmd_step,
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output reg [19:0] spi_cmd_idx
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);
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wire spi_core_cs_rising, spi_core_cs_falling;
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reg [15:0] spi_core_data_in;
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reg spi_core_data_in_valid;
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wire [15:0] spi_core_data_out;
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wire spi_core_data_out_valid;
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reg is_spi_cmd_word;
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always @(posedge clk) begin
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spi_core_data_in_valid <= 0;
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spi_cmd_begin <= 0;
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spi_cmd_step <= 0;
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spi_core_data_in <= spi_status_word;
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if (rst) begin
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is_spi_cmd_word <= 1;
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spi_cmd_active <= 0;
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spi_cmd_idx <= 0;
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end else begin
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if (spi_core_cs_rising) begin
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is_spi_cmd_word <= 1;
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spi_cmd_active <= 0;
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end
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if (ncs) begin
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/* constantly refresh status word */
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spi_core_data_in_valid <= 1;
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end
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if (spi_core_data_out_valid) begin
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spi_core_data_in <= spi_data_in;
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spi_core_data_in_valid <= 1;
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if (is_spi_cmd_word) begin
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spi_cmd_word <= spi_core_data_out;
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spi_cmd_idx <= 0;
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spi_cmd_active <= 1;
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spi_cmd_begin <= 1;
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is_spi_cmd_word <= 0;
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end else begin
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spi_cmd_idx <= spi_cmd_idx + 1;
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spi_cmd_step <= 1;
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spi_data_out <= spi_core_data_out;
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end
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end
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end
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end
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spi_core #(.WORDSIZE(16)) spi_core_dut (
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.clk(clk), .rst(rst),
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.sck(sck), .sdi(sdi), .sdo(sdo), .ncs(ncs),
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.cs_rising(spi_core_cs_rising),
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.cs_falling(spi_core_cs_falling),
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.data_out(spi_core_data_out),
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.data_out_valid(spi_core_data_out_valid),
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.data_in(spi_core_data_in),
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.data_in_valid(spi_core_data_in_valid)
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);
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endmodule
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