basic timer interleaving works
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jaseg
parent
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commit
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3 changed files with 35 additions and 134 deletions
3
Makefile
3
Makefile
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@ -1,4 +1,4 @@
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# Megumin LED display firmware
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# MoaRGB RGB COB controller
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# Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
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#
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# This program is free software: you can redistribute it and/or modify
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@ -18,6 +18,7 @@ CUBE_PATH ?= $(wildcard ~)/resource/STM32CubeF1
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CMSIS_PATH ?= $(CUBE_PATH)/Drivers/CMSIS
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CMSIS_DEV_PATH ?= $(CMSIS_PATH)/Device/ST/STM32F1xx
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HAL_PATH ?= $(CUBE_PATH)/Drivers/STM32F1xx_HAL_Driver
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USBD_PATH ?= $(CUBE_PATH)/Middlewares/ST/STM32_USB_Device_Library
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CC := arm-none-eabi-gcc
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LD := arm-none-eabi-ld
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164
main.c
164
main.c
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@ -17,14 +17,6 @@
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#include "global.h"
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#define RTC_INITIALIZED_REGISTER_HIGH BKP->DR1
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#define RTC_INITIALIZED_REGISTER_LOW BKP->DR2
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#define REBOOT_REGISTER BKP->DR3
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#define DAY_SECONDS (24*3600)
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void RTC_IRQHandler(void);
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uint32_t pcg32_random_r() {
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// *Really* minimal PCG32 code / (c) 2014 M.E. O'Neill / pcg-random.org
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// Licensed under Apache License 2.0 (NO WARRANTY, etc. see website)
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@ -39,64 +31,6 @@ uint32_t pcg32_random_r() {
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return (xorshifted >> rot) | (xorshifted << ((-rot) & 31));
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}
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unsigned char dumb_random() {
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static unsigned char x=0x66, a=0x05, b=0xe3, c=0xbc;
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x++; //x is incremented every round and is not affected by any other variable
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a = (a ^ c ^ x); //note the mix of addition and XOR
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b = (b + a); //And the use of very few instructions
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c = (((c + (b >> 1)) ^ a)); // the AES S-Box Operation ensures an even distributon of entropy
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return (c);
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}
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void rtc_write(volatile uint32_t *reg, uint32_t val) {
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while (!(RTC->CRL & RTC_CRL_RTOFF)) ;
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RTC->CRL |= RTC_CRL_CNF;
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reg[0] = val>>16;
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reg[1] = val&0xffff;
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RTC->CRL &= ~RTC_CRL_CNF;
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while (!(RTC->CRL & RTC_CRL_RTOFF)) ;
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}
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void rtc_alarm_reset(void) {
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RTC->CRL &= ~RTC_CRL_ALRF;
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}
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void rtc_init(void) {
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RTC->CRH = RTC_CRH_ALRIE;
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/* Cold boot config */
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if (((RTC_INITIALIZED_REGISTER_HIGH<<16) | RTC_INITIALIZED_REGISTER_LOW) != COMPILE_TIME) {
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/* RTC clock config */
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RCC->BDCR = RCC_BDCR_RTCEN | (1<<RCC_BDCR_RTCSEL_Pos) | RCC_BDCR_LSEON;
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while (!(RCC->BDCR & RCC_BDCR_LSERDY)) ;
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rtc_write(&RTC->PRLH, 32768-1);
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rtc_write(&RTC->CNTH, COMPILE_TIME);
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RTC_INITIALIZED_REGISTER_HIGH = COMPILE_TIME>>16;
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RTC_INITIALIZED_REGISTER_LOW = COMPILE_TIME&0xffff;
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REBOOT_REGISTER = 0;
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}
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/* Synchronize RTC registers from backup domain */
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RTC->CRL &= ~RTC_CRL_RSF;
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}
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void rtc_set_alarm_sec(uint32_t value) {
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rtc_write(&RTC->ALRH, value);
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}
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uint32_t rtc_time(void) {
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/* Wait for register synchronization after bootup */
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while (!(RTC->CRL & RTC_CRL_RSF)) ;
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return RTC->CNTH<<16 | RTC->CNTL;
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}
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void rtc_set_alarm_rel_sec(uint32_t value) {
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rtc_set_alarm_sec(rtc_time() + value);
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}
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int main(void){
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/* We're starting out from HSI@8MHz */
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SystemCoreClockUpdate();
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@ -105,82 +39,46 @@ int main(void){
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asm volatile ("nop");
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/* Turn on lots of neat things */
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RCC->APB2ENR |= RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPBEN;
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RCC->APB1ENR |= RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN;
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PWR->CR = PWR_CR_DBP;
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN | RCC_APB1ENR_TIM4EN;
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GPIOC->CRH |=
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(0<<GPIO_CRH_CNF13_Pos) | (2<<GPIO_CRH_MODE13_Pos); /* PC13 - LED */
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GPIOB->CRH =
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(0<<GPIO_CRH_CNF8_Pos) | (2<<GPIO_CRH_MODE8_Pos); /* PB8 - MOSFET */
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GPIOB->CRL |=
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(2<<GPIO_CRL_CNF5_Pos) | (2<<GPIO_CRL_MODE5_Pos); /* PB5 - TIM3_CH2 */
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AFIO->MAPR |= (2 << AFIO_MAPR_TIM3_REMAP_Pos); /* Map TIM3_CH2 to PB5 */
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GPIOB->CRH |=
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(2<<GPIO_CRH_CNF8_Pos) | (2<<GPIO_CRH_MODE8_Pos) /* PB8 - TIM4_CH3 */
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| (2<<GPIO_CRH_CNF9_Pos) | (2<<GPIO_CRH_MODE9_Pos); /* PB9 - TIM4_CH4 */
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GPIOC->ODR |= 1<<13; /* LED */
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GPIOB->ODR &= ~(1<<8); /* MOSFET */
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rtc_init();
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rtc_alarm_reset();
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NVIC_ClearPendingIRQ(RTC_IRQn);
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//NVIC_EnableIRQ(RTC_IRQn);
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//NVIC_SetPriority(RTC_IRQn, 1);
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TIM3->SMCR = (3<<TIM_SMCR_TS_Pos) | (6 << TIM_SMCR_SMS_Pos);
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TIM4->CR2 = (4<<TIM_CR2_MMS_Pos);
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rtc_set_alarm_rel_sec(1);
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int period = 0xffff;
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int thr[3] = {20000, 30000};
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if (!(PWR->CSR & PWR_CSR_WUF)) /* This reset wasn't caused by the RTC alarm */
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REBOOT_REGISTER++;
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int overlap = 1000;
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SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
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//SCB->SCR &= (~SCB_SCR_SLEEPONEXIT_Msk) & (~SCB_SCR_SLEEPDEEP_Msk);
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//PWR->CR &= (~PWR_CR_PDDS) & (~PWR_CR_LPDS);
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while (42) {
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RTC_IRQHandler();
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PWR->CR |= PWR_CR_CWUF; /* This has 2 cycles latency, thus the NOPs */
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("wfe");
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TIM4->CCR3 = thr[0];
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TIM4->CCR4 = thr[1];
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TIM4->CCR1 = thr[0];
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TIM3->CCR2 = thr[1] - thr[0];
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TIM3->ARR = 0xfffe;
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TIM4->ARR = 0xffff;
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TIM3->CCER = TIM_CCER_CC2E;
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TIM3->CCMR1 = (0<<TIM_CCMR1_CC2S_Pos) | TIM_CCMR1_OC2PE | (6<<TIM_CCMR1_OC2M_Pos);
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TIM4->CCER = TIM_CCER_CC3E | TIM_CCER_CC4E | TIM_CCER_CC1E | TIM_CCER_CC3P | TIM_CCER_CC4P;
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TIM4->CCMR1 = (0<<TIM_CCMR1_CC1S_Pos) | TIM_CCMR1_OC1PE | (7<<TIM_CCMR1_OC1M_Pos);
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TIM4->CCMR2 = (0<<TIM_CCMR2_CC4S_Pos) | TIM_CCMR2_OC4PE | (6<<TIM_CCMR2_OC4M_Pos) \
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| (0<<TIM_CCMR2_CC3S_Pos) | TIM_CCMR2_OC3PE | (7<<TIM_CCMR2_OC3M_Pos);
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TIM3->CR1 = TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_OPM;
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TIM4->CR1 = TIM_CR1_ARPE | TIM_CR1_CEN;
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for (;;) {
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}
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//while (42)
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// asm volatile ("wfi");
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}
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void RTC_IRQHandler(void) {
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rtc_alarm_reset();
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rtc_set_alarm_rel_sec(1);
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uint32_t now = rtc_time();
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bool switch_on = false;
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if (REBOOT_REGISTER > 1) { /* We have rebooted since initial bring-up */
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/* Give status indication and active output as fail-safe */
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if ((now&3) == 0) {
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GPIOC->ODR &= ~(1<<13);
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for (int i=0; i<5000; i++)
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asm volatile ("nop");
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GPIOC->ODR |= 1<<13;
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}
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switch_on = true;
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} else {
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switch_on = (now >= TARGET_DATE - (DAY_SECONDS*24) && now < TARGET_DATE);
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}
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if (switch_on && (now/2) % 3 == 0) {
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GPIOB->ODR |= 1<<8;
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/* Go to sleep mode to keep GPIO active */
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PWR->CR &= ~PWR_CR_PDDS;
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SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); /* Use deep sleep mode */
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} else {
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GPIOB->ODR &= ~(1<<8);
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/* Go to standby mode to reduce power consumption */
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PWR->CR = PWR_CR_PDDS;
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Use deep sleep mode */
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}
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GPIOC->ODR &= ~(1<<13);
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for (int i=0; i<5000; i++)
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asm volatile ("nop");
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GPIOC->ODR |= 1<<13;
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}
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void gdb_dump(void) {
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@ -1,6 +1,8 @@
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telnet_port 4444
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gdb_port 3333
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set CPUTAPID 0x2ba01477
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source [find interface/stlink-v2.cfg]
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#hla_serial "000000000001"
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transport select hla_swd
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