109 lines
3.6 KiB
C
109 lines
3.6 KiB
C
/* Megumin LED display firmware
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* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "global.h"
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uint32_t pcg32_random_r() {
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// *Really* minimal PCG32 code / (c) 2014 M.E. O'Neill / pcg-random.org
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// Licensed under Apache License 2.0 (NO WARRANTY, etc. see website)
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static uint64_t state = 0xbc422715d3aef60f;
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static uint64_t inc = 0x6605e3bc6d1a869b;
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uint64_t oldstate = state;
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// Advance internal state
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state = oldstate * 6364136223846793005ULL + (inc|1);
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// Calculate output function (XSH RR), uses old state for max ILP
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uint32_t xorshifted = ((oldstate >> 18u) ^ oldstate) >> 27u;
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uint32_t rot = oldstate >> 59u;
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return (xorshifted >> rot) | (xorshifted << ((-rot) & 31));
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}
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int main(void){
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/* We're starting out from HSI@8MHz */
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SystemCoreClockUpdate();
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SCB->SCR &= (~SCB_SCR_SLEEPONEXIT_Msk) & (~SCB_SCR_SLEEPDEEP_Msk); /* Disable for now */
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for (int i=0; i<50000; i++)
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asm volatile ("nop");
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/* Turn on lots of neat things */
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN | RCC_APB1ENR_TIM4EN;
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GPIOC->CRH |=
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(0<<GPIO_CRH_CNF13_Pos) | (2<<GPIO_CRH_MODE13_Pos); /* PC13 - LED */
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GPIOB->CRL |=
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(2<<GPIO_CRL_CNF5_Pos) | (2<<GPIO_CRL_MODE5_Pos); /* PB5 - TIM3_CH2 */
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AFIO->MAPR |= (2 << AFIO_MAPR_TIM3_REMAP_Pos); /* Map TIM3_CH2 to PB5 */
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GPIOB->CRH |=
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(2<<GPIO_CRH_CNF8_Pos) | (2<<GPIO_CRH_MODE8_Pos) /* PB8 - TIM4_CH3 */
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| (2<<GPIO_CRH_CNF9_Pos) | (2<<GPIO_CRH_MODE9_Pos); /* PB9 - TIM4_CH4 */
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GPIOC->ODR |= 1<<13; /* LED */
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TIM3->SMCR = (3<<TIM_SMCR_TS_Pos) | (6 << TIM_SMCR_SMS_Pos);
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TIM4->CR2 = (4<<TIM_CR2_MMS_Pos);
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int period = 0xffff;
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int thr[3] = {20000, 30000};
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int overlap = 1000;
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TIM4->CCR3 = thr[0];
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TIM4->CCR4 = thr[1];
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TIM4->CCR1 = thr[0];
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TIM3->CCR2 = thr[1] - thr[0];
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TIM3->ARR = 0xfffe;
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TIM4->ARR = 0xffff;
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TIM3->CCER = TIM_CCER_CC2E;
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TIM3->CCMR1 = (0<<TIM_CCMR1_CC2S_Pos) | TIM_CCMR1_OC2PE | (6<<TIM_CCMR1_OC2M_Pos);
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TIM4->CCER = TIM_CCER_CC3E | TIM_CCER_CC4E | TIM_CCER_CC1E | TIM_CCER_CC3P | TIM_CCER_CC4P;
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TIM4->CCMR1 = (0<<TIM_CCMR1_CC1S_Pos) | TIM_CCMR1_OC1PE | (7<<TIM_CCMR1_OC1M_Pos);
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TIM4->CCMR2 = (0<<TIM_CCMR2_CC4S_Pos) | TIM_CCMR2_OC4PE | (6<<TIM_CCMR2_OC4M_Pos) \
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| (0<<TIM_CCMR2_CC3S_Pos) | TIM_CCMR2_OC3PE | (7<<TIM_CCMR2_OC3M_Pos);
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TIM3->CR1 = TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_OPM;
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TIM4->CR1 = TIM_CR1_ARPE | TIM_CR1_CEN;
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for (;;) {
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}
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}
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void gdb_dump(void) {
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/* debugger hook */
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}
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void NMI_Handler(void) {
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asm volatile ("bkpt");
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}
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void HardFault_Handler(void) __attribute__((naked));
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void HardFault_Handler() {
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asm volatile ("bkpt");
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}
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void SVC_Handler(void) {
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asm volatile ("bkpt");
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}
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void PendSV_Handler(void) {
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asm volatile ("bkpt");
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}
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void SysTick_Handler(void) {
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asm volatile ("bkpt");
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}
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