driver: Add ac bc framing and a bunch of comments
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jaseg
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c6bf873e9f
commit
cb4a682e55
2 changed files with 66 additions and 34 deletions
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@ -2745,7 +2745,7 @@ F 3 "~" H 17400 2950 50 0001 C CNN
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1 0 0 -1
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$EndComp
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Text Notes 7600 10050 0 50 ~ 0
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TODO:\n* RS485 drv fp is wide, should be narrow SOIC-8\n* Heatsink holes are plated-through, shouln't be\n* Add thermal reliefs in upper logic ground plane\n* GND/VCC input labels are swapped\n* White label field for MAC\n* Remove optoisolators\n* Add series resistor to RS485 GND\n* Add decoupling cap next to mosfet temp sensor\n* Add INA226 filter network (see datasheet p.14)\n* Add voltage test points\n* Add pulldowns plus filter caps for CTRL_A, CTRL_B
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TODO:\n* RS485 drv fp is wide, should be narrow SOIC-8\n* Heatsink holes are plated-through, shouln't be\n* Add thermal reliefs in upper logic ground plane\n* GND/VCC input labels are swapped\n* White label field for MAC\n* Remove optoisolators\n* Add series resistor to RS485 GND\n* Add decoupling cap next to mosfet temp sensor\n* Add INA226 filter network (see datasheet p.14)\n* Add voltage test points\n* Add pulldowns plus filter caps for CTRL_A, CTRL_B\n* Label J4/J5 something like "in" and "out"
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NoConn ~ 14600 2800
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Text Notes 14100 9650 0 50 ~ 0
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I2C addr=010'0111
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@ -75,8 +75,6 @@ enum STATUS_LEDS {
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static void set_status_leds(uint8_t val) {
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/* Reset strobe. Will be set in systick handler */
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GPIOA->BRR = 1<<4;
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//for (int i=0; i<100; i++)
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// asm volatile ("nop");
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/* Workaround for *nasty* hardware behavior: If SPI data width is configured as 8 bit but DR is written as 16
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* bit, SPI actually sends 16 clock cycles. Thus, we have to make sure the compiler emits a 8-bit write here.
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* Thanks, TI! */
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@ -102,7 +100,12 @@ int main(void) {
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NVIC_EnableIRQ(SysTick_IRQn);
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NVIC_SetPriority(SysTick_IRQn, 3<<5);
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/* GPIO setup */
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/* GPIO setup
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*
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* Note: since we have quite a bunch of pin constraints we can't actually use complementary outputs for the
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* complementary MOSFET driver control signals (CTRL_A & CTRL_B). Instead, we use two totally separate output
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* channels (1 & 4) and emulate the dead-time generator in software.
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*/
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GPIOA->MODER |=
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(3<<GPIO_MODER_MODER0_Pos) /* PA0 - Vboot to ADC */
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| (2<<GPIO_MODER_MODER1_Pos) /* PA1 - RS485 DE */
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@ -135,9 +138,6 @@ int main(void) {
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(3<<GPIO_OSPEEDR_OSPEEDR1_Pos)
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| (3<<GPIO_OSPEEDR_OSPEEDR2_Pos);
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/* Note: since we have quite a bunch of pin constraints we can't actually use complementary outputs for the
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* complementary MOSFET driver control signals (CTRL_A & CTRL_B). Instead, we use two totally separate output
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* channels (1 & 4) and emulate the dead-time generator in software. */
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GPIOB->MODER |=
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(2<<GPIO_MODER_MODER1_Pos); /* PB1 - CTRL_B to TIM 3 ch 4 */
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@ -165,50 +165,56 @@ int main(void) {
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using a Java(TM) GUI. */
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i2c_enable(I2C1);
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lcd1602_init();
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ina226_init();
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mcp9801_init();
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/* The MCP9801 temperature sensor is initialized below in the SysTick ISR since it needs a few milliseconds to
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* powerup. */
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ina226_init(); /* Current/voltage monitor */
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mcp9801_init(); /* MOSFET temperature. Placed between middle two low-side MOSFETs. */
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/* TIM3 is used to generate the MOSFET driver control signals */
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/* TIM3 running off 48MHz APB1 clk, T=20.833ns */
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TIM3->CR1 = 0; /* Disable ARR preload (double-buffering) */
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TIM3->PSC = 48-1; /* Prescaler 48 -> f=1MHz/T=1us */
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TIM3->DIER = TIM_DIER_UIE; /* Enable update (overflow) interrupt */
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/* Set both CCRs to 0xffff to ensure both bridge halves are turned off after we enable the timer. If we don't do
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* this, we will cause a very low-ohm short circuit that at best will trigger our power supply's short-circuit or
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* over-current protection right after power-on but at worst will detonate the mosfets. */
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TIM3->CCR1 = 0xffff;
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TIM3->CCR4 = 0xffff;
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TIM3->CCMR1 = 6<<TIM_CCMR1_OC1M_Pos | TIM_CCMR1_OC1PE; /* Configure output compare unit 1 to PWM mode 1, enable CCR1 preload */
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TIM3->CCMR2 = 6<<TIM_CCMR2_OC4M_Pos | TIM_CCMR2_OC4PE; /* Configure output compare unit 4 to PWM mode 1, enable CCR4 preload */
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TIM3->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC4E | TIM_CCER_CC4P; /* Confiugre CH1 to complementary outputs */
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TIM3->BDTR = TIM_BDTR_MOE; /* Enable MOE on next update event, i.e. on initial timer load. */
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/* Configure output compare unit 1 to PWM mode 1, enable CCR1 preload */
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TIM3->CCMR1 = 6<<TIM_CCMR1_OC1M_Pos | TIM_CCMR1_OC1PE;
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/* Configure output compare unit 4 to PWM mode 1, enable CCR4 preload */
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TIM3->CCMR2 = 6<<TIM_CCMR2_OC4M_Pos | TIM_CCMR2_OC4PE;
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/* Confiugre CH1 to complementary outputs */
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TIM3->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC4E | TIM_CCER_CC4P;
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/* Enable MOE on next update event, i.e. on initial timer load. */
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TIM3->BDTR = TIM_BDTR_MOE;
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/* Enable timer */
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TIM3->CR1 |= TIM_CR1_CEN;
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TIM3->ARR = 800-1; /* Set f=2.5kHz/T=0.4ms */
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/* Set f=2.5kHz/T=0.4ms */
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TIM3->ARR = 800-1;
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/* Initialize AC protocol state machine in TIM3 ISR with the AC protocol comma */
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xfr_8b10b_encode_reset(&txstate.st);
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txstate.current_symbol = xfr_8b10b_encode(&txstate.st, K28_1) | 1<<10;
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/* The timer is still stopped. Start it by manually triggering an update event. */
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TIM3->EGR |= TIM_EGR_UG;
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lcd_write_str(0, 0, "8seg driver");
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lcd_write_str(0, 1, "initialized \xbc");
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NVIC_EnableIRQ(TIM3_IRQn);
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NVIC_SetPriority(TIM3_IRQn, 2<<4);
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lcd_write_str(0, 0, "8seg driver");
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lcd_write_str(0, 1, "initialized \xbc");
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while (42) {
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if (sys_flag_1Hz) {
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if (sys_flag_1Hz) { /* Update display every second */
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sys_flag_1Hz = 0;
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char buf[17];
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int temp = mcp9801_read_mdegC();
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int deg = temp/1000;
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int frac = (temp%1000)/100;
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mini_snprintf(buf, sizeof(buf), "Temp: %d.%01d\xdf""C" LCD_FILL, deg, frac);
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lcd_write_str(0, 0, buf);
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mini_snprintf(buf, sizeof(buf), "I=%dmA U=%dmV" LCD_FILL, ina226_read_i()*INA226_I_LSB_uA/1000, ina226_read_v()*INA226_VB_LSB_uV/1000);
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lcd_write_str(0, 1, buf);
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}
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}
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}
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@ -228,33 +234,58 @@ static int flipbits10(int in) {
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}
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#define BACKCHANNEL_INTERVAL 10
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void TIM3_IRQHandler() {
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static int txpos = -1;
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static unsigned int tx_start_tick = 0;
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static uint8_t txbuf[3] = {0x01, 0x05, 0x01};
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static uint8_t txbuf[2] = {0x04, 0x05};
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static int backchannel_counter = 0;
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TIM3->SR &= ~TIM_SR_UIF;
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int sym = txstate.current_symbol;
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int bit = sym&1;
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sym >>= 1;
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if (sym == 1) { /* last bit shifted out */
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if (txpos == -1)
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sym = xfr_8b10b_encode(&txstate.st, -K28_1);
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else
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sym = xfr_8b10b_encode(&txstate.st, txbuf[txpos]);
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txpos++;
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if (txpos >= sizeof(txbuf)/sizeof(txbuf[0])) {
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frame_duration_us = (sys_time_tick - tx_start_tick) * 10 * 1000;
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tx_start_tick = sys_time_tick;
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txpos = -1;
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/* Insert the backchannel sync control symbol K.28.2 once every BACKCHANNEL_INTERVAL symbols independent from AC
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* forward channel protocol framing. The backchannel sync control symbol is different from the AC protocol comma
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* K.28.1. The backchannel sync control symbol is not a comma, so the 8b10b receiver cannot lock on it. The only
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* practical implication of this is that after powerup or other loss of sync, the receiver will only lock on the
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* backchannel sync once the first AC forward-channel protocol frame has been begun. Since all backchannel comm
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* is triggered by the driver anyway this should not be noticeable in practice.
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*/
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backchannel_counter++;
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if (backchannel_counter == BACKCHANNEL_INTERVAL) {
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backchannel_counter = 0;
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sym = xfr_8b10b_encode(&txstate.st, -K28_2); /* TODO factor out backchannel comma into constant */
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} else {
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if (txpos == -1)
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sym = xfr_8b10b_encode(&txstate.st, -K28_1); /* TODO factor out comma into constant */
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else
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sym = xfr_8b10b_encode(&txstate.st, txbuf[txpos]);
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txpos++;
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if (txpos >= sizeof(txbuf)/sizeof(txbuf[0])) {
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frame_duration_us = (sys_time_tick - tx_start_tick) * 10 * 1000;
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tx_start_tick = sys_time_tick;
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txpos = -1;
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}
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}
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/* Append one '1' bit as an end-of-symbol marker for this state machine. This bit is not actually transmitted. */
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sym = flipbits10(sym) | 1<<10;
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}
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txstate.current_symbol = sym;
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/* FIXME factor out into header, or even make configurable */
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#define DEAD_TIME 100
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/* Set both CCRs to values for opposing polarities. The dead time is always inserted at the beginning of the timer
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* cycle due to the way the capture/compare unit PWM machinery works. By setting the CCR to 0xffff we make sure the
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* output is never turned on, since 0xffff is larger than the ARR/counter top value.
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*/
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TIM3->CCR1 = bit ? 0xffff : DEAD_TIME;
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TIM3->CCR4 = bit ? DEAD_TIME : 0xffff;
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}
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@ -285,7 +316,7 @@ void SysTick_Handler(void) {
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/* This is a hack. We could use the SPI interrupt here if that didn't fire at the start instead of end of transmission.... -.- */
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if (sys_time_tick&1) {
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uint8_t val = (sys_time_ms >= 500) ? STATUS_LED_OPERATION : 0;
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uint8_t val = (sys_time_ms >= 300) ? STATUS_LED_OPERATION : 0;
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if (comm_led_ctr) {
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comm_led_ctr--;
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@ -299,6 +330,7 @@ void SysTick_Handler(void) {
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set_status_leds(val);
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} else {
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/* Reset strobe for the status LED shift register. Reset in set_status_leds. */
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GPIOA->BSRR = 1<<4;
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}
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}
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