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driver: Make fw not short-circuit itself on startup

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jaseg 2019-04-23 18:48:26 +09:00
parent 69ead15835
commit c6bf873e9f
2 changed files with 3 additions and 1 deletions
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2
driver/driver.sch
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@ -2745,7 +2745,7 @@ F 3 "~" H 17400 2950 50 0001 C CNN
1 0 0 -1
$EndComp
Text Notes 7600 10050 0 50 ~ 0
TODO:\n* RS485 drv fp is wide, should be narrow SOIC-8\n* Heatsink holes are plated-through, shouln't be\n* Add thermal reliefs in upper logic ground plane\n* GND/VCC input labels are swapped\n* White label field for MAC\n* Remove optoisolators\n* Add series resistor to RS485 GND\n* Add decoupling cap next to mosfet temp sensor\n* Add INA226 filter network (see datasheet p.14)
TODO:\n* RS485 drv fp is wide, should be narrow SOIC-8\n* Heatsink holes are plated-through, shouln't be\n* Add thermal reliefs in upper logic ground plane\n* GND/VCC input labels are swapped\n* White label field for MAC\n* Remove optoisolators\n* Add series resistor to RS485 GND\n* Add decoupling cap next to mosfet temp sensor\n* Add INA226 filter network (see datasheet p.14)\n* Add voltage test points\n* Add pulldowns plus filter caps for CTRL_A, CTRL_B
NoConn ~ 14600 2800
Text Notes 14100 9650 0 50 ~ 0
I2C addr=010'0111

2
driver_fw/main.c
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@ -175,6 +175,8 @@ int main(void) {
TIM3->CR1 = 0; /* Disable ARR preload (double-buffering) */
TIM3->PSC = 48-1; /* Prescaler 48 -> f=1MHz/T=1us */
TIM3->DIER = TIM_DIER_UIE; /* Enable update (overflow) interrupt */
TIM3->CCR1 = 0xffff;
TIM3->CCR4 = 0xffff;
TIM3->CCMR1 = 6<<TIM_CCMR1_OC1M_Pos | TIM_CCMR1_OC1PE; /* Configure output compare unit 1 to PWM mode 1, enable CCR1 preload */
TIM3->CCMR2 = 6<<TIM_CCMR2_OC4M_Pos | TIM_CCMR2_OC4PE; /* Configure output compare unit 4 to PWM mode 1, enable CCR4 preload */
TIM3->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC4E | TIM_CCER_CC4P; /* Confiugre CH1 to complementary outputs */