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Official ARM version: v5.6.0

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This commit is contained in:
rihab kouki 2020-07-28 11:24:49 +01:00
parent 9f95ff5b6b
commit 96d6da4e25
2939 changed files with 339304 additions and 113320 deletions
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136
DSP/DSP_Lib_TestSuite/CMakeLists.txt Normal file
View file

@ -0,0 +1,136 @@
cmake_minimum_required (VERSION 3.6)
cmake_policy(SET CMP0077 NEW)
# The tests are assuming that MATRIX_CHECK is enabled when building
# CMSIS-DSP.
set(MATRIXCHECK ON)
set(FASTMATHCOMPUTATIONS OFF)
option(DUMPPATTERN "Dump test patterns when test is failing" ON)
option(CUSTOMIZE_TESTS "Enable customizations of tests" ON)
option(BASICMATH_TESTS "Enable Basic Math testing" ON)
option(COMPLEXMATH_TESTS "Enable Complex Math testing" ON)
option(CONTROLLER_TESTS "Enable Controller testing" ON)
option(FASTMATH_TESTS "Enable Fast Math testing" ON)
option(INTRINSICS_TESTS "Enable Intrinsics testing" ON)
option(FILTERING_TESTS "Enable Filtering testing" ON)
option(MATRIX_TESTS "Enable Matrix testing" ON)
option(STATISTICS_TESTS "Enable Statistics testing" ON)
option(SUPPORT_TESTS "Enable Support testing" ON)
option(TRANSFORM_TESTS "Enable Transform testing" ON)
project(DSP_Lib_TestSuite)
# Needed to find the config modules
list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/..)
set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../..)
file(GLOB MAIN "Common/src/*.c")
file(GLOB BASICMATH_TESTS_SRC "Common/src/basic_math_tests/*.c")
file(GLOB COMPLEXMATH_TESTS_SRC "Common/src/complex_math_tests/*.c")
file(GLOB CONTROLLER_TESTS_SRC "Common/src/controller_tests/*.c")
file(GLOB FASTMATH_TESTS_SRC "Common/src/fast_math_tests/*.c")
file(GLOB FILTERING_TESTS_SRC "Common/src/filtering_tests/*.c")
file(GLOB INTRINSINCS_TESTS_SRC "Common/src/intrinsics_tests/*.c")
file(GLOB MATRIX_TESTS_SRC "Common/src/matrix_tests/*.c")
file(GLOB STATISTICS_TESTS_SRC "Common/src/statistics_tests/*.c")
file(GLOB SUPPORT_TESTS_SRC "Common/src/support_tests/*.c")
file(GLOB TRANSFORM_TESTS_SRC "Common/src/transform_tests/*.c")
file(GLOB JTEST_MAIN "Common/JTest/src/*.c")
set(TESTSRC ${MAIN}
${BASICMATH_TESTS_SRC}
${COMPLEXMATH_TESTS_SRC}
${CONTROLLER_TESTS_SRC}
${FASTMATH_TESTS_SRC}
${FILTERING_TESTS_SRC}
${INTRINSINCS_TESTS_SRC}
${MATRIX_TESTS_SRC}
${STATISTICS_TESTS_SRC}
${SUPPORT_TESTS_SRC}
${TRANSFORM_TESTS_SRC}
${JTEST_MAIN}
)
set(JINCS
Common/JTest/inc
Common/JTest/inc/arr_desc
Common/inc/basic_math_tests
Common/inc/complex_math_tests
Common/inc/controller_tests
Common/inc/fast_math_tests
Common/inc/filtering_tests
Common/inc/intrinsics_tests
Common/inc/matrix_tests
Common/inc/statistics_tests
Common/inc/support_tests
Common/inc/transform_tests
)
add_subdirectory(../Source bin_dsp)
add_subdirectory(RefLibs bin_ref)
add_executable(DSP_Lib_TestSuite)
if (CUSTOMIZE_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE CUSTOMIZE_TESTS)
endif()
if (BASICMATH_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_BASICMATH_TESTS)
endif()
if (COMPLEXMATH_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_COMPLEXMATH_TESTS)
endif()
if (CONTROLLER_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_CONTROLLER_TESTS)
endif()
if (FASTMATH_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_FASTMATH_TESTS)
endif()
if (FILTERING_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_FILTERING_TESTS)
endif()
if (INTRINSICS_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_INTRINSICS_TESTS)
endif()
if (MATRIX_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_MATRIX_TESTS)
endif()
if (STATISTICS_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_STATISTICS_TESTS)
endif()
if (SUPPORT_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_SUPPORT_TESTS)
endif()
if (TRANSFORM_TESTS)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE ENABLE_TRANSFORM_TESTS)
endif()
if (DUMPPATTERN)
target_compile_definitions(DSP_Lib_TestSuite PRIVATE DUMPPATTERN)
endif()
# Change behavior of configBoot for scatter file
set(TESTFRAMEWORK ON)
include(configBoot)
file(COPY ${ROOT}/CMSIS/DSP/Examples/ARM/boot/RTE_Components.h DESTINATION tempLink)
target_link_libraries(DSP_Lib_TestSuite PRIVATE CMSISDSP)
target_link_libraries(DSP_Lib_TestSuite PRIVATE DspRefLibs)
target_sources(DSP_Lib_TestSuite PRIVATE ${TESTSRC})
### Includes
target_include_directories(DSP_Lib_TestSuite PRIVATE "Common/inc")
target_include_directories(DSP_Lib_TestSuite PRIVATE "Common/inc/templates")
target_include_directories(DSP_Lib_TestSuite PRIVATE ${JINCS})

16
DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h
View file

@ -43,6 +43,8 @@ extern const char * JTEST_CYCLE_STRF;
__jtest_cycle_end_count)); \
} while (0)
*/
#ifndef ARMv7A
#define JTEST_COUNT_CYCLES(fn_call) \
do \
{ \
@ -56,10 +58,22 @@ extern const char * JTEST_CYCLE_STRF;
__jtest_cycle_end_count = \
JTEST_SYSTICK_VALUE(SysTick); \
\
JTEST_SYSTICK_RESET(SysTick); \
JTEST_SYSTICK_RESET(SysTick); \
JTEST_DUMP_STRF(JTEST_CYCLE_STRF, \
(JTEST_SYSTICK_INITIAL_VALUE - \
__jtest_cycle_end_count)); \
} while (0)
#else
/* TODO */
#define JTEST_COUNT_CYCLES(fn_call) \
do \
{ \
fn_call; \
} while (0)
#endif
#endif /* _JTEST_CYCLE_H_ */

29
DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h
View file

@ -141,6 +141,19 @@ typedef struct JTEST_FW_struct
* Fill the buffer named buf_name with value and dump it to the Keil debugger
* using action.
*/
#if defined(ARMv7A) || defined(FILEIO)
#define JTEST_ACT_DUMP(action, buf_name, value) \
do \
{ \
JTEST_CLEAR_BUFFER(buf_name); \
printf("%s",value); \
strcpy(JTEST_FW.buf_name, (value)); \
JTEST_TRIGGER_ACTION(action); \
} while (0)
#else
#define JTEST_ACT_DUMP(action, buf_name, value) \
do \
{ \
@ -149,6 +162,7 @@ typedef struct JTEST_FW_struct
JTEST_TRIGGER_ACTION(action); \
} while (0)
#endif
/**
* Trigger the "Exit Framework" action in the Keil Debugger.
*/
@ -192,6 +206,19 @@ typedef struct JTEST_FW_struct
/**
* Dump a formatted string to the Keil Debugger.
*/
#if defined(ARMv7A) || defined(FILEIO)
#define JTEST_DUMP_STRF(format_str, ... ) \
do \
{ \
JTEST_CLEAR_STR_BUFFER(); \
sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__); \
printf("%s",JTEST_FW.str_buffer); \
jtest_dump_str_segments(); \
} while (0)
#else
#define JTEST_DUMP_STRF(format_str, ... ) \
do \
{ \
@ -200,6 +227,8 @@ typedef struct JTEST_FW_struct
jtest_dump_str_segments(); \
} while (0)
#endif
/* Pass/Fail Macros */
/*--------------------------------------------------------------------------------*/

25
DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h
View file

@ -2,7 +2,7 @@
#define _JTEST_SYSTICK_H_
/*--------------------------------------------------------------------------------*/
/* Includes */
/* Includes */
/*--------------------------------------------------------------------------------*/
/* Get access to the SysTick structure. */
@ -10,6 +10,8 @@
#include "ARMCM0.h"
#elif defined ARMCM0P
#include "ARMCM0plus.h"
#elif defined ARMCM0P_MPU
#include "ARMCM0plus_MPU.h"
#elif defined ARMCM3
#include "ARMCM3.h"
#elif defined ARMCM4
@ -40,22 +42,22 @@
#include "ARMv8MML_DP.h"
#elif defined ARMv8MML_DSP_DP
#include "ARMv8MML_DSP_DP.h"
#elif defined ARMv7A
/* TODO */
#else
#warning "no appropriate header file found!"
#endif
/*--------------------------------------------------------------------------------*/
/* Macros and Defines */
/* Macros and Defines */
/*--------------------------------------------------------------------------------*/
/**
* Initial value for the SysTick module.
*
* @note This is also the maximum value, important as SysTick is a decrementing
* counter.
* This is also the maximum value, important as SysTick is a decrementing counter.
*/
#define JTEST_SYSTICK_INITIAL_VALUE 0xFFFFFF
#define JTEST_SYSTICK_INITIAL_VALUE 0xFFFFFF
/**
* Reset the SysTick, decrementing timer to it's maximum value and disable it.
@ -66,11 +68,10 @@
#define JTEST_SYSTICK_RESET(systick_ptr) \
do \
{ \
(systick_ptr)->LOAD = JTEST_SYSTICK_INITIAL_VALUE; \
(systick_ptr)->VAL = 1; \
(systick_ptr)->CTRL = SysTick_CTRL_CLKSOURCE_Msk; \
\
/* Disable the SysTick module. */ \
(systick_ptr)->CTRL = UINT32_C(0x000000); \
(systick_ptr)->LOAD = JTEST_SYSTICK_INITIAL_VALUE; \
(systick_ptr)->VAL = JTEST_SYSTICK_INITIAL_VALUE; \
} while (0)
/**
@ -81,13 +82,13 @@
{ \
(systick_ptr)->CTRL = \
SysTick_CTRL_ENABLE_Msk | \
SysTick_CTRL_CLKSOURCE_Msk; /* Internal clk*/ \
SysTick_CTRL_CLKSOURCE_Msk; \
} while (0)
/**
* Evaluate to the current value of the SysTick timer.
*/
#define JTEST_SYSTICK_VALUE(systick_ptr) \
#define JTEST_SYSTICK_VALUE(systick_ptr) \
((systick_ptr)->VAL)
#endif /* _JTEST_SYSTICK_H_ */

2
DSP/DSP_Lib_TestSuite/Common/JTest/jtest_FVP.ini
View file

@ -12,7 +12,7 @@ LOG OFF /* Turn off Logging by defau
BK * /* Remove existing breakpoints. */
INCLUDE ../../Common/JTest/jtest_fns.ini /* Load the JTEST helper functions */
INCLUDE ../../Common/JTest/jtest_log_FVP.ini /* Include a log file if specified by jtest_log.ini */
INCLUDE ../../Common/JTest/jtest_log_FVP.ini /* Include specified log file */
/* Break on special members of the JTEST framework. The framework's
name is defined in jtest_fw.h by the #DEFINE JTEST_FW. */

6
DSP/DSP_Lib_TestSuite/Common/JTest/jtest_Simulator.ini
View file

@ -17,12 +17,12 @@ INCLUDE ../../Common/JTest/jtest_log_Simulator.ini /* Include specified log fil
/* Break on special members of the JTEST framework. The framework's
name is defined in jtest_fw.h by the #DEFINE JTEST_FW. */
BS test_start , 1, "coverage_clear(); test_start_msg();"
BS test_end , 1, "coverage_msg(); test_end_msg();"
BS test_start , 1, "test_start_msg();"
BS test_end , 1, "test_end_msg();"
BS group_start , 1, "group_start_msg();"
BS group_end , 1, "group_end_msg();"
BS dump_str , 1, "dump_str_fn();"
BS dump_data , 1, "dump_data_fn();"
//BS dump_data , 1, "dump_data_fn();"
BS exit_fw , 1, "break_fn(); debug_clean_fn(); log_off_fn();"
debug_setup_finished_msg() /* Output a message to let the output

32
DSP/DSP_Lib_TestSuite/Common/JTest/jtest_Simulator.ini.withCoverage Normal file
View file

@ -0,0 +1,32 @@
/* This demonstrates how to setup a Debugger '*.ini' file to interface with the
* C-code using the JTEST test framework.
*/
MAP 0x00000000, 0x001FFFFF EXEC READ /* 2048K Flash */
MAP 0x20000000, 0x201FFFFF READ WRITE /* 2048K RAM */
LOAD %L INCREMENTAL
RESET /* Reset the target processor */
LOG OFF /* Turn off Logging by default. */
BK * /* Remove existing breakpoints. */
INCLUDE ../../Common/JTest/jtest_fns.ini /* Load the JTEST helper functions */
INCLUDE ../../Common/JTest/jtest_log_Simulator.ini /* Include specified log file */
/* Break on special members of the JTEST framework. The framework's
name is defined in jtest_fw.h by the #DEFINE JTEST_FW. */
BS test_start , 1, "coverage_clear(); test_start_msg();"
BS test_end , 1, "coverage_msg(); test_end_msg();"
BS group_start , 1, "group_start_msg();"
BS group_end , 1, "group_end_msg();"
BS dump_str , 1, "dump_str_fn();"
BS dump_data , 1, "dump_data_fn();"
BS exit_fw , 1, "break_fn(); debug_clean_fn(); log_off_fn();"
debug_setup_finished_msg() /* Output a message to let the output
parser know that setup has
finished. */
G /* Start the Tests */

62
DSP/DSP_Lib_TestSuite/Common/inc/templates/test_templates.h
View file

@ -62,25 +62,29 @@
/**
* Assert that buffers A and B are byte-equivalent for a number of bytes.
*/
#define TEST_ASSERT_BUFFERS_EQUAL(buf_a, buf_b, bytes) \
do \
{ \
if (memcmp(buf_a, buf_b, bytes) != 0) \
{ \
return JTEST_TEST_FAILED; \
} \
#define TEST_ASSERT_BUFFERS_EQUAL(buf_a, buf_b, bytes)\
do \
{ \
if (memcmp(buf_a, buf_b, bytes) != 0) \
{ \
return JTEST_TEST_FAILED; \
} \
} while (0)
/**
* Assert that the two entities are equal.
*/
#define TEST_ASSERT_EQUAL(a, b) \
do \
{ \
if ((a) != (b)) \
{ \
return JTEST_TEST_FAILED; \
} \
#define TEST_ASSERT_EQUAL(a, b) \
do \
{ \
if ((a) != (b)) \
{ \
return JTEST_TEST_FAILED;\
} \
} while (0)
/**
@ -111,31 +115,35 @@
* Assert that the SNR between a reference and test sample is above a given
* threshold.
*/
#define TEST_ASSERT_SNR(ref_ptr, tst_ptr, block_size, threshold) \
do \
{ \
float32_t snr = arm_snr_f32(ref_ptr, tst_ptr, block_size); \
if ( snr <= threshold) \
{ \
JTEST_DUMP_STRF("SNR: %f\n", snr); \
return JTEST_TEST_FAILED; \
} \
} while (0) \
#define TEST_ASSERT_SNR(ref_ptr, tst_ptr, block_size, threshold) \
do \
{ \
float32_t snr = arm_snr_f32(ref_ptr, tst_ptr, block_size);\
if ( snr <= threshold) \
{ \
JTEST_DUMP_STRF("SNR: %f\n", snr); \
return JTEST_TEST_FAILED; \
} \
} while (0)
/**
* Assert that the SNR between a reference and test sample is above a given
* threshold. Special case for float64_t
*/
#define TEST_ASSERT_DBL_SNR(ref_ptr, tst_ptr, block_size, threshold) \
#define TEST_ASSERT_DBL_SNR(ref_ptr, tst_ptr, block_size, threshold)\
do \
{ \
float64_t snr = arm_snr_f64(ref_ptr, tst_ptr, block_size); \
if ( snr <= threshold) \
if ( snr <= threshold) \
{ \
JTEST_DUMP_STRF("SNR: %f\n", snr); \
return JTEST_TEST_FAILED; \
} \
} while (0) \
} while (0)
/**
* Compare test and reference elements by converting to float and

70
DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/armcc5_arm.sct Normal file
View file

@ -0,0 +1,70 @@
#! armcc -E
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Flash Configuration -------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00200000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00200000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000400
#define __HEAP_SIZE 0x00000C00
/*----------------------------------------------------------------------------
User Stack & Heap boundery definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE)
#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE (__RAM_BASE )
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

88
DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s
View file

@ -31,33 +31,6 @@
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -66,11 +39,12 @@ __heap_limit
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit||
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
@ -134,62 +108,4 @@ SysTick_Handler PROC
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
;/*
; __user_setup_stackheap() returns the:
; - heap base in r0 (if the program uses the heap)
; - stack base in sp
; - heap limit in r2 (if the program uses the heap and uses two-region memory).
; */
EXPORT __user_setup_stackheap
__user_setup_stackheap PROC
LDR R0, = __initial_sp
MOV SP, R0
IF Heap_Size > 0
LDR R2, = __heap_limit
LDR R0, = __heap_base
ELSE
MOV R0, #0
MOV R2, #0
ENDIF
BX LR
ENDP
;/*
;__user_initial_stackheap() returns the:
; - heap base in r0
; - stack base in r1, that is, the highest address in the stack region
; - heap limit in r2
; - stack limit in r3, that is, the lowest address in the stack region.
; */
;
;/* DEPRICATED
; EXPORT __user_initial_stackheap
;
;__user_initial_stackheap PROC
; LDR R0, = Heap_Mem
; LDR R1, =(Stack_Mem + Stack_Size)
; LDR R2, = (Heap_Mem + Heap_Size)
; LDR R3, = Stack_Mem
; BX LR
; ENDP
; */
ALIGN
ENDIF
END

195
DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s.noSCT Normal file
View file

@ -0,0 +1,195 @@
;/* File: startup_armv6-m.s
; * Purpose: startup file for armv7-m architecture devices.
; * Should be used with ARMCC
; * Version: V2.00
; * Date: 16 November 2015
; *
; */
;/* Copyright (c) 2011 - 2014 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
BKPT #0
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
BKPT #0
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
;/*
; __user_setup_stackheap() returns the:
; - heap base in r0 (if the program uses the heap)
; - stack base in sp
; - heap limit in r2 (if the program uses the heap and uses two-region memory).
; */
EXPORT __user_setup_stackheap
__user_setup_stackheap PROC
LDR R0, = __initial_sp
MOV SP, R0
IF Heap_Size > 0
LDR R2, = __heap_limit
LDR R0, = __heap_base
ELSE
MOV R0, #0
MOV R2, #0
ENDIF
BX LR
ENDP
;/*
;__user_initial_stackheap() returns the:
; - heap base in r0
; - stack base in r1, that is, the highest address in the stack region
; - heap limit in r2
; - stack limit in r3, that is, the lowest address in the stack region.
; */
;
;/* DEPRICATED
; EXPORT __user_initial_stackheap
;
;__user_initial_stackheap PROC
; LDR R0, = Heap_Mem
; LDR R1, =(Stack_Mem + Stack_Size)
; LDR R2, = (Heap_Mem + Heap_Size)
; LDR R3, = Stack_Mem
; BX LR
; ENDP
; */
ALIGN
ENDIF
END

88
DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s
View file

@ -31,33 +31,6 @@
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
@ -66,11 +39,12 @@ __heap_limit
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit||
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
@ -157,62 +131,4 @@ SysTick_Handler PROC
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
;/*
; __user_setup_stackheap() returns the:
; - heap base in r0 (if the program uses the heap)
; - stack base in sp
; - heap limit in r2 (if the program uses the heap and uses two-region memory).
; */
EXPORT __user_setup_stackheap
__user_setup_stackheap PROC
LDR R0, = __initial_sp
MOV SP, R0
IF Heap_Size > 0
LDR R2, = __heap_limit
LDR R0, = __heap_base
ELSE
MOV R0, #0
MOV R2, #0
ENDIF
BX LR
ENDP
;/*
;__user_initial_stackheap() returns the:
; - heap base in r0
; - stack base in r1, that is, the highest address in the stack region
; - heap limit in r2
; - stack limit in r3, that is, the lowest address in the stack region.
; */
;
;/* DEPRICATED
; EXPORT __user_initial_stackheap
;
;__user_initial_stackheap PROC
; LDR R0, = Heap_Mem
; LDR R1, =(Stack_Mem + Stack_Size)
; LDR R2, = (Heap_Mem + Heap_Size)
; LDR R3, = Stack_Mem
; BX LR
; ENDP
; */
ALIGN
ENDIF
END

218
DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s.noSCT Normal file
View file

@ -0,0 +1,218 @@
;/* File: startup_armv7-m.s
; * Purpose: startup file for armv7-m architecture devices.
; * Should be used with ARMCC
; * Version: V2.00
; * Date: 16 November 2015
; *
; */
;/* Copyright (c) 2011 - 2014 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
BKPT #0
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
BKPT #0
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
BKPT #0
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
BKPT #0
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
BKPT #0
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
;/*
; __user_setup_stackheap() returns the:
; - heap base in r0 (if the program uses the heap)
; - stack base in sp
; - heap limit in r2 (if the program uses the heap and uses two-region memory).
; */
EXPORT __user_setup_stackheap
__user_setup_stackheap PROC
LDR R0, = __initial_sp
MOV SP, R0
IF Heap_Size > 0
LDR R2, = __heap_limit
LDR R0, = __heap_base
ELSE
MOV R0, #0
MOV R2, #0
ENDIF
BX LR
ENDP
;/*
;__user_initial_stackheap() returns the:
; - heap base in r0
; - stack base in r1, that is, the highest address in the stack region
; - heap limit in r2
; - stack limit in r3, that is, the lowest address in the stack region.
; */
;
;/* DEPRICATED
; EXPORT __user_initial_stackheap
;
;__user_initial_stackheap PROC
; LDR R0, = Heap_Mem
; LDR R1, =(Stack_Mem + Stack_Size)
; LDR R2, = (Heap_Mem + Heap_Size)
; LDR R3, = Stack_Mem
; BX LR
; ENDP
; */
ALIGN
ENDIF
END

70
DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/armcc6_arm.sct Normal file
View file

@ -0,0 +1,70 @@
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Flash Configuration -------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00200000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00200000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000400
#define __HEAP_SIZE 0x00000C00
/*----------------------------------------------------------------------------
User Stack & Heap boundery definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE)
#define __HEAP_BASE (__RAM_BASE + __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE (__RAM_BASE )
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}

80
DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S
View file

@ -42,39 +42,7 @@
/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
/*
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Stack_Size, 0x00000400
.section STACK, "w"
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
__StackTop: /* formerly known as __initial_sp */
/*
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Heap_Size, 0x00000C00
.section HEAP, "w"
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
__HeapLimit:
.global Image$$ARM_LIB_STACK$$ZI$$Limit
.section RESET, "x"
@ -83,7 +51,7 @@ __HeapLimit:
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __StackTop /* Top of Stack */
.long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
@ -156,48 +124,4 @@ SysTick_Handler:
bkpt #0
b .
.global __use_two_region_memory
/*
__user_setup_stackheap() returns the:
- heap base in r0 (if the program uses the heap)
- stack base in sp
- heap limit in r2 (if the program uses the heap and uses two-region memory).
*/
.globl __user_setup_stackheap
.type __user_setup_stackheap, %function
.thumb_func
__user_setup_stackheap:
ldr r0, =__StackTop
mov sp, r0
.if Heap_Size
ldr r0, =__HeapBase
ldr r2, =__HeapLimit
.else
mov r0, #0
mov r2, #0
.endif
bx lr
/*
__user_initial_stackheap() returns the:
- heap base in r0
- stack base in r1, that is, the highest address in the stack region
- heap limit in r2
- stack limit in r3, that is, the lowest address in the stack region.
*/
/* DEPRICATED
.globl __user_initial_stackheap
.type __user_initial_stackheap, %function
.thumb_func
__user_initial_stackheap:
ldr r0, = __HeapBase
ldr r1, = __StackTop
ldr r2, = __HeapLimit
ldr r3, = __StackLimit
bx lr
*/
.end

203
DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S.noSCT Normal file
View file

@ -0,0 +1,203 @@
/* File: startup_armv6-m.S
* Purpose: startup file for armv6-m architecture devices.
* Should be used with ARMCLANG
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
.syntax unified
.arch armv6-m
/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
/*
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Stack_Size, 0x00000400
.section STACK, "w"
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
__StackTop: /* formerly known as __initial_sp */
/*
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Heap_Size, 0x00000C00
.section HEAP, "w"
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
__HeapLimit:
.section RESET, "x"
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.text
.thumb
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
.thumb_func
Reset_Handler:
bl SystemInit
bl __main
.globl NMI_Handler
.weak NMI_Handler
.type NMI_Handler, %function
.thumb_func
NMI_Handler:
bkpt #0
b .
.globl HardFault_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
.thumb_func
HardFault_Handler:
bkpt #0
b .
.globl SVC_Handler
.weak SVC_Handler
.type SVC_Handler, %function
.thumb_func
SVC_Handler:
bkpt #0
b .
.globl PendSV_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
.thumb_func
PendSV_Handler:
bkpt #0
b .
.globl SysTick_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
.thumb_func
SysTick_Handler:
bkpt #0
b .
.global __use_two_region_memory
/*
__user_setup_stackheap() returns the:
- heap base in r0 (if the program uses the heap)
- stack base in sp
- heap limit in r2 (if the program uses the heap and uses two-region memory).
*/
.globl __user_setup_stackheap
.type __user_setup_stackheap, %function
.thumb_func
__user_setup_stackheap:
ldr r0, =__StackTop
mov sp, r0
.if Heap_Size
ldr r0, =__HeapBase
ldr r2, =__HeapLimit
.else
mov r0, #0
mov r2, #0
.endif
bx lr
/*
__user_initial_stackheap() returns the:
- heap base in r0
- stack base in r1, that is, the highest address in the stack region
- heap limit in r2
- stack limit in r3, that is, the lowest address in the stack region.
*/
/* DEPRICATED
.globl __user_initial_stackheap
.type __user_initial_stackheap, %function
.thumb_func
__user_initial_stackheap:
ldr r0, = __HeapBase
ldr r1, = __StackTop
ldr r2, = __HeapLimit
ldr r3, = __StackLimit
bx lr
*/
.end

82
DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S
View file

@ -37,44 +37,12 @@
.syntax unified
.arch armv6-m
.arch armv7-m
/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
/*
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Stack_Size, 0x00000400
.section STACK, "w"
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
__StackTop: /* formerly known as __initial_sp */
/*
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Heap_Size, 0x00000C00
.section HEAP, "w"
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
__HeapLimit:
.global Image$$ARM_LIB_STACK$$ZI$$Limit
.section RESET, "x"
@ -83,7 +51,7 @@ __HeapLimit:
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __StackTop /* Top of Stack */
.long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
@ -188,48 +156,4 @@ SysTick_Handler:
bkpt #0
b .
.global __use_two_region_memory
/*
__user_setup_stackheap() returns the:
- heap base in r0 (if the program uses the heap)
- stack base in sp
- heap limit in r2 (if the program uses the heap and uses two-region memory).
*/
.globl __user_setup_stackheap
.type __user_setup_stackheap, %function
.thumb_func
__user_setup_stackheap:
ldr r0, =__StackTop
mov sp, r0
.if Heap_Size
ldr r0, =__HeapBase
ldr r2, =__HeapLimit
.else
mov r0, #0
mov r2, #0
.endif
bx lr
/*
__user_initial_stackheap() returns the:
- heap base in r0
- stack base in r1, that is, the highest address in the stack region
- heap limit in r2
- stack limit in r3, that is, the lowest address in the stack region.
*/
/* DEPRICATED
.globl __user_initial_stackheap
.type __user_initial_stackheap, %function
.thumb_func
__user_initial_stackheap:
ldr r0, = __HeapBase
ldr r1, = __StackTop
ldr r2, = __HeapLimit
ldr r3, = __StackLimit
bx lr
*/
.end

235
DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S.noSCT Normal file
View file

@ -0,0 +1,235 @@
/* File: startup_armv7-m.S
* Purpose: startup file for armv7-m architecture devices.
* Should be used with ARMCLANG
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
.syntax unified
.arch armv6-m
/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
/*
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Stack_Size, 0x00000400
.section STACK, "w"
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
__StackTop: /* formerly known as __initial_sp */
/*
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Heap_Size, 0x00000C00
.section HEAP, "w"
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
__HeapLimit:
.section RESET, "x"
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.text
.thumb
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
.thumb_func
Reset_Handler:
bl SystemInit
bl __main
.globl NMI_Handler
.weak NMI_Handler
.type NMI_Handler, %function
.thumb_func
NMI_Handler:
bkpt #0
b .
.globl HardFault_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
.thumb_func
HardFault_Handler:
bkpt #0
b .
.globl MemManage_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
.thumb_func
MemManage_Handler:
bkpt #0
b .
.globl BusFault_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
.thumb_func
BusFault_Handler:
bkpt #0
b .
.globl UsageFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
.thumb_func
UsageFault_Handler:
bkpt #0
b .
.globl SVC_Handler
.weak SVC_Handler
.type SVC_Handler, %function
.thumb_func
SVC_Handler:
bkpt #0
b .
.globl DebugMon_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
.thumb_func
DebugMon_Handler:
bkpt #0
b .
.globl PendSV_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
.thumb_func
PendSV_Handler:
bkpt #0
b .
.globl SysTick_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
.thumb_func
SysTick_Handler:
bkpt #0
b .
.global __use_two_region_memory
/*
__user_setup_stackheap() returns the:
- heap base in r0 (if the program uses the heap)
- stack base in sp
- heap limit in r2 (if the program uses the heap and uses two-region memory).
*/
.globl __user_setup_stackheap
.type __user_setup_stackheap, %function
.thumb_func
__user_setup_stackheap:
ldr r0, =__StackTop
mov sp, r0
.if Heap_Size
ldr r0, =__HeapBase
ldr r2, =__HeapLimit
.else
mov r0, #0
mov r2, #0
.endif
bx lr
/*
__user_initial_stackheap() returns the:
- heap base in r0
- stack base in r1, that is, the highest address in the stack region
- heap limit in r2
- stack limit in r3, that is, the lowest address in the stack region.
*/
/* DEPRICATED
.globl __user_initial_stackheap
.type __user_initial_stackheap, %function
.thumb_func
__user_initial_stackheap:
ldr r0, = __HeapBase
ldr r1, = __StackTop
ldr r2, = __HeapLimit
ldr r3, = __StackLimit
bx lr
*/
.end

48
DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S
View file

@ -1,56 +1,62 @@
#if defined (__CC_ARM)
#if (defined (ARM_MATH_CM0))
#if (defined (ARMCM0))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARM_MATH_CM0P))
#elif (defined (ARMCM0P) || defined (ARMCM0P_MPU))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARM_MATH_CM3))
#elif (defined (ARMCM3))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARM_MATH_CM4))
#elif (defined (ARMCM4) || defined (ARMCM4_FP))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARM_MATH_CM7))
#elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARM_MATH_ARMV8MBL))
#elif (defined (ARMv8MBL))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARM_MATH_ARMV8MML))
#elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \
defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \
defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) )
#include "ARMCC\startup_armv7-m.s"
#else
#error "No appropriate startup file found!"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if (defined (ARM_MATH_CM0))
#if (defined (ARMCM0))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM0P))
#elif (defined (ARMCM0P) || defined (ARMCM0P_MPU))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM3))
#elif (defined (ARMCM3))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM4))
#elif (defined (ARMCM4) || defined (ARMCM4_FP))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM7))
#elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARM_MATH_ARMV8MBL))
#elif (defined (ARMv8MBL))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARM_MATH_ARMV8MML))
#elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \
defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \
defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) )
#include "ARMCLANG\startup_armv7-m.S"
#else
#error "No appropriate startup file found!"
#endif
#elif defined (__GNUC__)
#if (defined (ARM_MATH_CM0))
#if (defined (ARMCM0))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM0P))
#elif (defined (ARMCM0P) || defined (ARMCM0P_MPU))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM3))
#elif (defined (ARMCM3))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM4))
#elif (defined (ARMCM4) || defined (ARMCM4_FP))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM7))
#elif (defined (ARMCM7) || defined (ARMCM7_SP) || defined (ARMCM7_DP))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARM_MATH_ARMV8MBL))
#elif (defined (ARMv8MBL))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARM_MATH_ARMV8MML))
#elif (defined (ARMv8MML) || defined (ARMv8MML_DSP) || \
defined (ARMv8MML_SP) || defined (ARMv8MML_DSP_SP) || \
defined (ARMv8MML_DP) || defined (ARMv8MML_DSP_DP) )
#include "GCC\startup_armv7-m.S"
#else
#error "No appropriate startup file found!"

60
DSP/DSP_Lib_TestSuite/Common/src/all_tests.c
View file

@ -12,19 +12,51 @@
JTEST_DEFINE_GROUP(all_tests)
{
/*
To skip a test, comment it out
*/
JTEST_GROUP_CALL(basic_math_tests);
JTEST_GROUP_CALL(complex_math_tests);
JTEST_GROUP_CALL(controller_tests);
JTEST_GROUP_CALL(fast_math_tests);
JTEST_GROUP_CALL(filtering_tests);
JTEST_GROUP_CALL(matrix_tests);
JTEST_GROUP_CALL(statistics_tests);
JTEST_GROUP_CALL(support_tests);
JTEST_GROUP_CALL(transform_tests);
JTEST_GROUP_CALL(intrinsics_tests);
/*
To skip a test, comment it out
*/
#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_BASICMATH_TESTS)
JTEST_GROUP_CALL(basic_math_tests);
#endif
return;
#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_COMPLEXMATH_TESTS)
JTEST_GROUP_CALL(complex_math_tests);
#endif
#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_CONTROLLER_TESTS)
JTEST_GROUP_CALL(controller_tests);
#endif
#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_FASTMATH_TESTS)
JTEST_GROUP_CALL(fast_math_tests);
#endif
#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_FILTERING_TESTS)
/* Biquad df2T_f32 will fail with Neon. The test must be updated.
Neon implementation is requiring a different initialization.
*/
JTEST_GROUP_CALL(filtering_tests);
#endif
#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_MATRIX_TESTS)
JTEST_GROUP_CALL(matrix_tests);
#endif
#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_STATISTICS_TESTS)
JTEST_GROUP_CALL(statistics_tests);
#endif()
#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_SUPPORT_TESTS)
JTEST_GROUP_CALL(support_tests);
#endif
#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_TRANSFORM_TESTS)
JTEST_GROUP_CALL(transform_tests);
#endif
#if !defined(CUSTOMIZE_TESTS) || defined(ENABLE_INTRINSICS_TESTS)
JTEST_GROUP_CALL(intrinsics_tests);
#endif
return;
}

348
DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c
View file

@ -190,175 +190,181 @@ const q15_t * fast_math_q15_inputs = (q15_t *) fast_math_q31_inputs;
const float32_t fast_math_f32_inputs[FAST_MATH_MAX_LEN] =
{
-1.5E-07, 5.0545058, 6.1958757, 0.1884450, 3.3656774, 0.5471223,
-5.0396892, 6.2149808, 0.4206357, 5.9024140, 0.1142128, 4.2966847,
-4.9243615, 3.3560853, 5.5628775, 5.6486144, 3.9328821, 0.8662564,
-1.3684878, 1.1444261, 0.2627620, 0.6719343, 3.8732286, 5.9040643,
-2.2271110, 2.5800587, 6.1848498, 5.9412493, 4.2514839, 6.2096863,
-4.8181437, 2.1155439, 4.1618680, 1.5341357, 1.8567268, 4.2736867,
-3.3165594, 2.5861183, 3.7864876, 4.7156566, 3.6664471, 3.4670146,
-3.6666823, 3.2158594, 0.5189454, 4.5211925, 6.2590334, 2.2276047,
-6.1025991, 2.1768018, 5.5703194, 2.8569321, 2.5976403, 1.3680509,
-0.7895111, 1.9409676, 4.5622487, 4.9189303, 4.3591961, 0.0615894,
-5.2980657, 5.7951829, 4.8440482, 0.2680398, 2.3762136, 4.4254964,
-4.5836656, 1.4091744, 1.6905207, 4.2287795, 3.0001720, 3.9189258,
-1.4856273, 1.1129014, 5.2128031, 4.8187110, 5.8715002, 0.6778860,
-1.1449692, 0.6226340, 3.0772767, 1.2141962, 5.6290528, 0.6225986,
-0.2775005, 3.5015887, 4.8537297, 1.9599772, 1.1245801, 2.1297213,
-1.3203840, 3.2053828, 5.6948550, 3.9516457, 0.6379562, 2.4558128,
-0.3431663, 3.1496534, 2.7125841, 6.2678565, 5.0994494, 3.0514394,
-5.6199810, 0.8642307, 2.4504731, 5.8267510, 5.7647838, 4.4835177,
3.8851284, 2.1569414, 5.8812331, 0.7839784, 4.5904032, 4.0619375,
5.2348483, 2.5024810, 4.7112719, 5.2478452, 2.0260784, 3.4699621,
6.1520498, 3.4514073, 2.0761128, 3.8922546, 2.2659464, 4.7532896,
2.6006151, 3.0934955, 4.3652005, 6.1118673, 2.0593452, 5.2640727,
4.6437278, 5.9952549, 0.2005758, 2.2422740, 4.1635768, 1.7687265,
1.4475395, 4.4681525, 3.9243074, 3.7109036, 4.1496541, 0.2987948,
2.1914796, 2.8358565, 1.5136507, 4.4927603, 5.3795520, 1.7687650,
4.5933278, 0.8655898, 5.2572843, 0.8708603, 3.6958286, 2.3006310,
5.0690197, 3.1653480, 3.0762120, 5.5106597, 2.2188555, 2.8239372,
6.0540393, 0.2657649, 6.1132775, 1.1888217, 4.1916405, 3.6847088,
4.2418564, 2.2683684, 3.8973243, 5.0966113, 0.1209983, 0.5269928,
6.1248595, 4.0925498, 1.4529100, 2.5352096, 0.7666775, 1.6866509,
1.6200953, 2.0839142, 0.9565145, 2.1865966, 0.7644026, 5.5552975,
0.5923686, 5.8436176, 2.5071164, 0.2978322, 2.1511962, 4.6242118,
4.9931353, 3.4237447, 4.3116692, 5.6148598, 0.3442670, 1.9079607,
0.2902301, 1.2282167, 4.5249352, 4.5349096, 5.5153742, 3.6595342,
0.4441228, 5.7977751, 5.0288862, 1.7966571, 3.4159368, 6.1875316,
4.4967379, 5.2714014, 2.7222564, 2.9570223, 3.5230663, 1.6907520,
4.7062218, 3.1660203, 4.0640250, 1.9336225, 0.8716326, 2.9881129,
2.2773988, 4.9518627, 4.9027432, 4.2003861, 0.8388295, 0.1354396,
3.5175829, 1.8901016, 5.9024853, 6.1631993, 1.8008890, 5.0317023,
5.6304337, 3.7543702, 5.5544410, 5.9296402, 3.4504620, 4.5765894,
3.6238793, 0.1624673, 2.8056369, 4.0608350, 3.2748147, 2.3393094,
5.8881908, 5.2121085, 5.3349614, 2.3407017, 3.7270886, 5.4824095,
5.8653636, 4.2000849, 1.2992148, 4.1082644, 0.4527132, 2.5555406,
4.1904544, 5.8667713, 5.0953493, 3.0445066, 4.7547955, 2.6203864,
6.1059115, 6.2076281, 5.4295991, 2.4434288, 2.8572272, 1.5499814,
4.9286757, 5.5470323, 5.7410198, 3.5078076, 3.7627993, 0.9354200,
5.6530665, 2.8299063, 1.2922774, 5.6526739, 4.7914663, 5.5448250,
1.7903950, 4.2300036, 4.1737937, 0.7716694, 2.5592571, 1.7296789,
4.5029688, 1.7805566, 5.6309835, 5.1935484, 2.4506089, 3.1284165,
4.3655898, 5.2424950, 3.8304163, 3.6111801, 2.0485834, 2.8678003,
4.4849099, 5.5568808, 4.5292698, 0.1169475, 4.2397456, 2.7552322,
2.7509053, 0.7353640, 5.1187960, 2.0411269, 1.5470969, 2.1533307,
2.3605433, 3.4340988, 3.5306485, 2.4870244, 2.5015301, 3.2381477,
4.1313862, 5.9747764, 4.5386496, 2.5137752, 5.2268018, 0.8440727,
0.3799239, 0.5293398, 0.0000000, 2.0371338, 1.8958053, 0.0733938,
3.3923238, 0.5992443, 0.9205800, 3.9655772, 5.3992694, 6.1212150,
3.5866836, 6.2633946, 3.4780043, 3.2387210, 2.0777367, 2.7017810,
3.0901098, 0.4463392, 5.5778300, 0.4061048, 2.7406309, 5.1938664,
2.4789345, 3.8545764, 5.1436714, 5.5683790, 5.8503469, 1.1987353,
1.6247202, 5.6414565, 3.7282025, 3.1657206, 3.8503962, 5.1485818,
3.3419582, 1.2696753, 2.8518968, 2.6886436, 6.0698884, 3.8959208,
4.3692639, 4.5249277, 2.1796068, 3.2483466, 3.4978155, 0.9832885,
3.5315023, 4.3655778, 2.6794992, 5.2544420, 4.5954405, 2.2621418,
2.8539005, 2.4277593, 4.8729535, 4.6135614, 2.7035154, 4.3589760,
5.9389515, 4.9274787, 4.4332387, 0.6869673, 2.4500066, 3.7127639,
2.8863700, 0.3162955, 1.4368865, 5.2413645, 0.0982985, 5.4268554,
0.4905223, 4.2037186, 3.1429204, 1.3696954, 3.5915675, 0.7677371,
4.2170618, 3.7673071, 0.3517086, 0.3540136, 0.9581898, 0.1232828,
2.7342886, 5.2290017, 3.8791769, 3.2680695, 5.4278441, 0.6138541,
5.7054603, 0.6786889, 3.2483864, 0.8994758, 3.5146290, 0.0287746,
4.8172051, 5.3325973, 5.7605579, 6.2013046, 3.1738449, 1.7053924,
0.6330341, 3.1909083, 3.6794907, 4.7933610, 0.5212697, 4.1569315,
3.2482749, 1.0747264, 5.8971330, 3.7101152, 2.7685894, 5.9182512,
4.1212281, 2.8396586, 5.2759745, 3.3465722, 3.4801751, 4.2729777,
2.3071222, 1.5035072, 3.6374836, 5.4468120, 2.5558538, 0.7075818,
2.7887656, 1.8861142, 2.5219880, 5.2361777, 2.5360737, 2.4515477,
2.2647672, 0.8812504, 1.6344462, 0.5454754, 2.6979830, 1.6165554,
1.8695956, 2.6694641, 0.7490013, 3.1105972, 4.4384875, 1.5304166,
4.9327408, 0.4655185, 2.4748426, 0.0213259, 1.3865538, 0.0081717,
1.1886509, 0.8952537, 1.6843712, 1.0988793, 0.8711572, 3.7629093,
5.6615138, 5.9022971, 1.3897429, 3.0327137, 2.3625475, 3.2910070,
1.6642436, 0.4295011, 2.7415239, 1.0923508, 0.1640358, 5.9984205,
2.7055177, 6.0416507, 4.7903915, 0.0461730, 4.2728088, 4.4356194,
4.0534637, 3.4702651, 1.3704176, 4.8529200, 1.4327442, 2.3302118,
5.5978709, 5.3807748, 2.5285646, 1.9981730, 3.8241692, 5.7189253,
5.7120324, 3.7170973, 2.0896078, 5.3599569, 2.7796679, 5.6822331,
0.2084724, 3.3453343, 4.5018856, 1.1265867, 2.1144987, 1.1794352,
2.0227281, 2.5375066, 3.4467437, 0.3062336, 3.4729184, 1.7266910,
1.5174002, 1.5277262, 0.9686124, 6.0093412, 5.8789338, 5.1441345,
4.5758041, 1.1046577, 2.2642776, 1.1862024, 0.0075297, 1.9881224,
4.3958232, 3.9285942, 3.4121603, 2.7585521, 1.8059588, 3.1520171,
4.7849358, 4.7903511, 3.6194660, 4.6977042, 4.0560129, 0.7742111,
3.1692252, 2.1819072, 0.5789810, 0.9289656, 1.2451370, 4.2239985,
2.7112647, 4.3630684, 1.6134250, 0.0613154, 3.3444332, 1.7554715,
5.9453394, 5.6953510, 2.4673100, 0.1561700, 4.2187618, 5.2600982,
6.1041123, 0.3577199, 2.8294680, 3.6597688, 4.3142726, 4.5203293,
4.0843265, 4.5673388, 2.3489542, 3.6541880, 0.7295941, 0.3622530,
6.1560465, 1.7896003, 3.7383338, 6.0454361, 1.1672793, 1.2129049,
2.1466132, 5.8615704, 2.4546365, 1.7166712, 0.9547117, 2.4951084,
2.3544507, 0.8238180, 2.7334414, 0.5749942, 3.8618151, 0.0689837,
3.6019012, 4.9620190, 1.4788531, 2.8149909, 3.5773830, 0.3857966,
3.1182750, 4.0357856, 1.3902536, 5.2593808, 6.1014456, 5.3179177,
3.1792883, 1.7522271, 4.6911344, 1.4886775, 6.0151778, 3.8972087,
3.7715583, 1.0845061, 0.5676653, 1.6038597, 5.3945577, 5.7244031,
4.3959286, 4.5564551, 1.4444168, 3.6194506, 5.0933266, 2.5374227,
6.2105471, 0.5654792, 2.0165320, 3.2132771, 0.3808010, 4.5596317,
3.4969429, 3.3260664, 5.2149334, 5.3957421, 4.9576149, 1.9970040,
2.8413032, 4.7263877, 0.6902815, 0.6895316, 1.6957291, 3.2963937,
6.1113470, 4.4636294, 1.9594738, 1.8312791, 5.3429527, 5.7280497,
4.0166905, 1.6045389, 0.5571039, 5.2669152, 3.6738954, 5.9571429,
0.3834561, 3.6734096, 1.7913869, 5.2007946, 1.2000032, 2.7804978,
2.4718774, 5.1935175, 4.2529065, 1.3044083, 1.9987109, 0.8407592,
4.2189258, 3.5876427, 1.0666779, 0.9277486, 2.9912971, 5.7057758,
3.4694180, 0.2069675, 0.3384307, 5.0583614, 2.8360719, 2.4042372,
4.9614777, 2.2888819, 3.3448533, 4.4714710, 5.4756485, 2.0652177,
4.0848120, 6.1250762, 0.4773170, 3.6883502, 2.6005256, 1.9423615,
1.6577182, 4.7674690, 6.2531264, 1.1722630, 4.9080805, 1.2302350,
6.2351753, 5.0407581, 2.6654950, 4.5795867, 3.1312479, 5.0830358,
2.2400117, 0.4602021, 3.7133088, 5.7188788, 1.2174673, 2.7166470,
4.7071094, 0.2462034, 5.9459353, 4.7983010, 3.5111731, 1.1551193,
3.1287047, 3.2537199, 6.2470131, 5.3711915, 6.0469623, 4.2659122,
2.5352740, 5.8746469, 3.0126903, 1.4563896, 2.4899651, 4.4301324,
3.5095299, 4.7540509, 6.2547920, 6.0471349, 3.3619258, 6.0561746,
0.7264988, 0.3232592, 1.9122808, 3.6454528, 3.3361480, 5.6624574,
3.3963785, 2.7142142, 3.4096772, 4.4762342, 0.1047703, 5.0323343,
0.8954125, 3.0063438, 1.6137441, 2.3190715, 4.1579916, 1.0656836,
1.7516517, 1.2454643, 1.2256706, 2.0535941, 5.5313259, 2.9600203,
2.5382144, 1.1261446, 6.0879353, 2.5601199, 5.3060708, 3.8662016,
2.3663172, 5.5114955, 4.9313732, 2.9213939, 5.1143679, 5.6450910,
2.6969853, 2.1006537, 3.7488443, 5.6673754, 4.4112136, 2.3716204,
4.6178643, 5.9948046, 3.4105954, 3.3935850, 1.9547595, 0.4475800,
1.1434170, 0.5842667, 2.9121888, 0.0586379, 5.7492774, 4.0384655,
0.0089162, 0.1909163, 1.3098570, 2.8586366, 0.7996361, 0.0543350,
4.5683759, 2.2249794, 4.9036865, 2.7435946, 2.7429546, 0.3092155,
0.3118464, 0.5723993, 3.7324447, 1.5147758, 5.2864780, 5.3860266,
6.0545540, 3.0718480, 1.3842492, 1.4213108, 3.3727372, 4.7884765,
2.1838288, 2.8980046, 4.0169897, 5.7637923, 1.0151904, 4.4964699,
3.6300404, 2.7224978, 5.5558613, 2.4696170, 1.1245340, 3.9793522,
3.9207111, 2.0605178, 5.0451799, 6.2799046, 6.1636676, 0.7981966,
1.4592079, 0.1484872, 3.8166117, 0.6962355, 2.5601436, 5.5548184,
3.4440198, 2.3185147, 1.3090764, 2.7705283, 6.0079576, 0.7792778,
2.9578927, 5.3840384, 0.2726304, 4.3456090, 6.1511471, 1.7798247,
0.8405677, 4.3057392, 5.7142715, 3.8382030, 5.6547587, 1.2153801,
4.7401894, 2.1756202, 2.6303011, 0.9784166, 5.1459324, 3.9265103,
4.6405120, 5.0586705, 0.4223724, 5.9739917, 3.1263686, 4.7447217,
4.6646686, 5.2221411, 0.9833301, 2.8733554, 3.8836400, 5.8570808,
-5.2470141, 5.6261119, 3.6600718, 3.6615062, 5.3716581, 0.2190677,
-5.5632585, 2.5618482, 0.2285950, 4.6881858, 0.9728179, 0.9042027,
-3.8073530, 1.5989503, 2.0367209, 2.5245268, 2.5533189, 2.4265105,
-3.8314979, 1.0486053, 1.1818174, 0.5945707, 2.0306392, 4.8355201,
-1.4710068, 4.6518534, 4.3531065, 5.1778361, 5.2023364, 1.8432851,
-1.9438243, 3.2862931, 2.0439139, 5.2266206, 5.0912323, 3.4997233,
-1.6522518, 4.2761236, 1.4680860, 2.8678051, 2.4163051, 3.3841326,
-6.2310582, 4.7451897, 6.1603795, 1.4751828, 3.3210347, 0.3231823,
-4.7555888, 3.7823504, 5.3857498, 6.2095284, 5.8401232, 2.5730582,
-0.0021455, 3.3984387, 1.3052100, 1.3777994, 2.0471011, 0.6028680,
-4.6968925, 4.7030205, 3.4136510, 2.1245480, 5.2297066, 3.4719134,
-6.0164208, 5.6098372, 2.2399783, 3.4331443, 2.1782657, 3.9131853,
-5.0053405, 4.6864702, 0.7887674, 5.1672539, 0.1580253, 2.6039335,
-4.5955687, 4.9095176, 2.3077255, 4.6801428, 5.6062801, 1.5243220,
-0.8142818, 1.4141432, 2.1992023, 1.8038058, 5.8275790, 0.3224138,
-3.7238350, 1.0235240, 5.2678588, 1.0528164, 3.1554195, 6.2789723,
-2.2330890, 0.2957980, 1.3424690, 2.4996969, 2.0964990, 1.4426353,
-5.8818165, 4.2926017, 6.0451393, 2.7518666, 5.9083095, 0.0366581,
-3.8346722, 5.0333074, 1.4638661, 5.8588735, 4.7957215, 5.1927356,
-3.6031780, 4.9799375, 2.0674268, 1.4040530, 1.9627813, 3.6726693,
-5.2145043, 1.8250297, 2.5293238, 5.4164658, 3.8625225, 6.2278165,
-1.2798778, 5.1975080, 4.2465638, 1.5641957, 2.9894493, 2.5074636,
-3.7663816, 5.0298329, 0.6601666, 5.1612735, 5.2847013, 2.2274284,
-2.7022061, 3.5954850, 4.4034117, 4.6650751, 4.7619266, 2.4449681,
-2.6973871, 6.0088907, 3.6000853, 5.3389611
/* Special values close to increments of pi/2 */
-0.0, 0.0, -1.5E-07, 1.5E-07, 1.5707964, 1.5707965,
-1.5707964, -1.5707965, 3.1415925, 3.1415927, -3.1415925, -3.1415927,
6.2831855, 6.283186, -6.2831855, -6.283186,
/* Test some slightly larger values too */
10.1, -13.2,
/* Random values (0, 2pi) */
-1.3684878, 1.1444261, 0.2627620, 0.6719343, 3.8732286, 5.9040643,
-2.2271110, 2.5800587, 6.1848498, 5.9412493, 4.2514839, 6.2096863,
-4.8181437, 2.1155439, 4.1618680, 1.5341357, 1.8567268, 4.2736867,
-3.3165594, 2.5861183, 3.7864876, 4.7156566, 3.6664471, 3.4670146,
-3.6666823, 3.2158594, 0.5189454, 4.5211925, 6.2590334, 2.2276047,
-6.1025991, 2.1768018, 5.5703194, 2.8569321, 2.5976403, 1.3680509,
-0.7895111, 1.9409676, 4.5622487, 4.9189303, 4.3591961, 0.0615894,
-5.2980657, 5.7951829, 4.8440482, 0.2680398, 2.3762136, 4.4254964,
-4.5836656, 1.4091744, 1.6905207, 4.2287795, 3.0001720, 3.9189258,
-1.4856273, 1.1129014, 5.2128031, 4.8187110, 5.8715002, 0.6778860,
-1.1449692, 0.6226340, 3.0772767, 1.2141962, 5.6290528, 0.6225986,
-0.2775005, 3.5015887, 4.8537297, 1.9599772, 1.1245801, 2.1297213,
-1.3203840, 3.2053828, 5.6948550, 3.9516457, 0.6379562, 2.4558128,
-0.3431663, 3.1496534, 2.7125841, 6.2678565, 5.0994494, 3.0514394,
-5.6199810, 0.8642307, 2.4504731, 5.8267510, 5.7647838, 4.4835177,
3.8851284, 2.1569414, 5.8812331, 0.7839784, 4.5904032, 4.0619375,
5.2348483, 2.5024810, 4.7112719, 5.2478452, 2.0260784, 3.4699621,
6.1520498, 3.4514073, 2.0761128, 3.8922546, 2.2659464, 4.7532896,
2.6006151, 3.0934955, 4.3652005, 6.1118673, 2.0593452, 5.2640727,
4.6437278, 5.9952549, 0.2005758, 2.2422740, 4.1635768, 1.7687265,
1.4475395, 4.4681525, 3.9243074, 3.7109036, 4.1496541, 0.2987948,
2.1914796, 2.8358565, 1.5136507, 4.4927603, 5.3795520, 1.7687650,
4.5933278, 0.8655898, 5.2572843, 0.8708603, 3.6958286, 2.3006310,
5.0690197, 3.1653480, 3.0762120, 5.5106597, 2.2188555, 2.8239372,
6.0540393, 0.2657649, 6.1132775, 1.1888217, 4.1916405, 3.6847088,
4.2418564, 2.2683684, 3.8973243, 5.0966113, 0.1209983, 0.5269928,
6.1248595, 4.0925498, 1.4529100, 2.5352096, 0.7666775, 1.6866509,
1.6200953, 2.0839142, 0.9565145, 2.1865966, 0.7644026, 5.5552975,
0.5923686, 5.8436176, 2.5071164, 0.2978322, 2.1511962, 4.6242118,
4.9931353, 3.4237447, 4.3116692, 5.6148598, 0.3442670, 1.9079607,
0.2902301, 1.2282167, 4.5249352, 4.5349096, 5.5153742, 3.6595342,
0.4441228, 5.7977751, 5.0288862, 1.7966571, 3.4159368, 6.1875316,
4.4967379, 5.2714014, 2.7222564, 2.9570223, 3.5230663, 1.6907520,
4.7062218, 3.1660203, 4.0640250, 1.9336225, 0.8716326, 2.9881129,
2.2773988, 4.9518627, 4.9027432, 4.2003861, 0.8388295, 0.1354396,
3.5175829, 1.8901016, 5.9024853, 6.1631993, 1.8008890, 5.0317023,
5.6304337, 3.7543702, 5.5544410, 5.9296402, 3.4504620, 4.5765894,
3.6238793, 0.1624673, 2.8056369, 4.0608350, 3.2748147, 2.3393094,
5.8881908, 5.2121085, 5.3349614, 2.3407017, 3.7270886, 5.4824095,
5.8653636, 4.2000849, 1.2992148, 4.1082644, 0.4527132, 2.5555406,
4.1904544, 5.8667713, 5.0953493, 3.0445066, 4.7547955, 2.6203864,
6.1059115, 6.2076281, 5.4295991, 2.4434288, 2.8572272, 1.5499814,
4.9286757, 5.5470323, 5.7410198, 3.5078076, 3.7627993, 0.9354200,
5.6530665, 2.8299063, 1.2922774, 5.6526739, 4.7914663, 5.5448250,
1.7903950, 4.2300036, 4.1737937, 0.7716694, 2.5592571, 1.7296789,
4.5029688, 1.7805566, 5.6309835, 5.1935484, 2.4506089, 3.1284165,
4.3655898, 5.2424950, 3.8304163, 3.6111801, 2.0485834, 2.8678003,
4.4849099, 5.5568808, 4.5292698, 0.1169475, 4.2397456, 2.7552322,
2.7509053, 0.7353640, 5.1187960, 2.0411269, 1.5470969, 2.1533307,
2.3605433, 3.4340988, 3.5306485, 2.4870244, 2.5015301, 3.2381477,
4.1313862, 5.9747764, 4.5386496, 2.5137752, 5.2268018, 0.8440727,
0.3799239, 0.5293398, 0.0000000, 2.0371338, 1.8958053, 0.0733938,
3.3923238, 0.5992443, 0.9205800, 3.9655772, 5.3992694, 6.1212150,
3.5866836, 6.2633946, 3.4780043, 3.2387210, 2.0777367, 2.7017810,
3.0901098, 0.4463392, 5.5778300, 0.4061048, 2.7406309, 5.1938664,
2.4789345, 3.8545764, 5.1436714, 5.5683790, 5.8503469, 1.1987353,
1.6247202, 5.6414565, 3.7282025, 3.1657206, 3.8503962, 5.1485818,
3.3419582, 1.2696753, 2.8518968, 2.6886436, 6.0698884, 3.8959208,
4.3692639, 4.5249277, 2.1796068, 3.2483466, 3.4978155, 0.9832885,
3.5315023, 4.3655778, 2.6794992, 5.2544420, 4.5954405, 2.2621418,
2.8539005, 2.4277593, 4.8729535, 4.6135614, 2.7035154, 4.3589760,
5.9389515, 4.9274787, 4.4332387, 0.6869673, 2.4500066, 3.7127639,
2.8863700, 0.3162955, 1.4368865, 5.2413645, 0.0982985, 5.4268554,
0.4905223, 4.2037186, 3.1429204, 1.3696954, 3.5915675, 0.7677371,
4.2170618, 3.7673071, 0.3517086, 0.3540136, 0.9581898, 0.1232828,
2.7342886, 5.2290017, 3.8791769, 3.2680695, 5.4278441, 0.6138541,
5.7054603, 0.6786889, 3.2483864, 0.8994758, 3.5146290, 0.0287746,
4.8172051, 5.3325973, 5.7605579, 6.2013046, 3.1738449, 1.7053924,
0.6330341, 3.1909083, 3.6794907, 4.7933610, 0.5212697, 4.1569315,
3.2482749, 1.0747264, 5.8971330, 3.7101152, 2.7685894, 5.9182512,
4.1212281, 2.8396586, 5.2759745, 3.3465722, 3.4801751, 4.2729777,
2.3071222, 1.5035072, 3.6374836, 5.4468120, 2.5558538, 0.7075818,
2.7887656, 1.8861142, 2.5219880, 5.2361777, 2.5360737, 2.4515477,
2.2647672, 0.8812504, 1.6344462, 0.5454754, 2.6979830, 1.6165554,
1.8695956, 2.6694641, 0.7490013, 3.1105972, 4.4384875, 1.5304166,
4.9327408, 0.4655185, 2.4748426, 0.0213259, 1.3865538, 0.0081717,
1.1886509, 0.8952537, 1.6843712, 1.0988793, 0.8711572, 3.7629093,
5.6615138, 5.9022971, 1.3897429, 3.0327137, 2.3625475, 3.2910070,
1.6642436, 0.4295011, 2.7415239, 1.0923508, 0.1640358, 5.9984205,
2.7055177, 6.0416507, 4.7903915, 0.0461730, 4.2728088, 4.4356194,
4.0534637, 3.4702651, 1.3704176, 4.8529200, 1.4327442, 2.3302118,
5.5978709, 5.3807748, 2.5285646, 1.9981730, 3.8241692, 5.7189253,
5.7120324, 3.7170973, 2.0896078, 5.3599569, 2.7796679, 5.6822331,
0.2084724, 3.3453343, 4.5018856, 1.1265867, 2.1144987, 1.1794352,
2.0227281, 2.5375066, 3.4467437, 0.3062336, 3.4729184, 1.7266910,
1.5174002, 1.5277262, 0.9686124, 6.0093412, 5.8789338, 5.1441345,
4.5758041, 1.1046577, 2.2642776, 1.1862024, 0.0075297, 1.9881224,
4.3958232, 3.9285942, 3.4121603, 2.7585521, 1.8059588, 3.1520171,
4.7849358, 4.7903511, 3.6194660, 4.6977042, 4.0560129, 0.7742111,
3.1692252, 2.1819072, 0.5789810, 0.9289656, 1.2451370, 4.2239985,
2.7112647, 4.3630684, 1.6134250, 0.0613154, 3.3444332, 1.7554715,
5.9453394, 5.6953510, 2.4673100, 0.1561700, 4.2187618, 5.2600982,
6.1041123, 0.3577199, 2.8294680, 3.6597688, 4.3142726, 4.5203293,
4.0843265, 4.5673388, 2.3489542, 3.6541880, 0.7295941, 0.3622530,
6.1560465, 1.7896003, 3.7383338, 6.0454361, 1.1672793, 1.2129049,
2.1466132, 5.8615704, 2.4546365, 1.7166712, 0.9547117, 2.4951084,
2.3544507, 0.8238180, 2.7334414, 0.5749942, 3.8618151, 0.0689837,
3.6019012, 4.9620190, 1.4788531, 2.8149909, 3.5773830, 0.3857966,
3.1182750, 4.0357856, 1.3902536, 5.2593808, 6.1014456, 5.3179177,
3.1792883, 1.7522271, 4.6911344, 1.4886775, 6.0151778, 3.8972087,
3.7715583, 1.0845061, 0.5676653, 1.6038597, 5.3945577, 5.7244031,
4.3959286, 4.5564551, 1.4444168, 3.6194506, 5.0933266, 2.5374227,
6.2105471, 0.5654792, 2.0165320, 3.2132771, 0.3808010, 4.5596317,
3.4969429, 3.3260664, 5.2149334, 5.3957421, 4.9576149, 1.9970040,
2.8413032, 4.7263877, 0.6902815, 0.6895316, 1.6957291, 3.2963937,
6.1113470, 4.4636294, 1.9594738, 1.8312791, 5.3429527, 5.7280497,
4.0166905, 1.6045389, 0.5571039, 5.2669152, 3.6738954, 5.9571429,
0.3834561, 3.6734096, 1.7913869, 5.2007946, 1.2000032, 2.7804978,
2.4718774, 5.1935175, 4.2529065, 1.3044083, 1.9987109, 0.8407592,
4.2189258, 3.5876427, 1.0666779, 0.9277486, 2.9912971, 5.7057758,
3.4694180, 0.2069675, 0.3384307, 5.0583614, 2.8360719, 2.4042372,
4.9614777, 2.2888819, 3.3448533, 4.4714710, 5.4756485, 2.0652177,
4.0848120, 6.1250762, 0.4773170, 3.6883502, 2.6005256, 1.9423615,
1.6577182, 4.7674690, 6.2531264, 1.1722630, 4.9080805, 1.2302350,
6.2351753, 5.0407581, 2.6654950, 4.5795867, 3.1312479, 5.0830358,
2.2400117, 0.4602021, 3.7133088, 5.7188788, 1.2174673, 2.7166470,
4.7071094, 0.2462034, 5.9459353, 4.7983010, 3.5111731, 1.1551193,
3.1287047, 3.2537199, 6.2470131, 5.3711915, 6.0469623, 4.2659122,
2.5352740, 5.8746469, 3.0126903, 1.4563896, 2.4899651, 4.4301324,
3.5095299, 4.7540509, 6.2547920, 6.0471349, 3.3619258, 6.0561746,
0.7264988, 0.3232592, 1.9122808, 3.6454528, 3.3361480, 5.6624574,
3.3963785, 2.7142142, 3.4096772, 4.4762342, 0.1047703, 5.0323343,
0.8954125, 3.0063438, 1.6137441, 2.3190715, 4.1579916, 1.0656836,
1.7516517, 1.2454643, 1.2256706, 2.0535941, 5.5313259, 2.9600203,
2.5382144, 1.1261446, 6.0879353, 2.5601199, 5.3060708, 3.8662016,
2.3663172, 5.5114955, 4.9313732, 2.9213939, 5.1143679, 5.6450910,
2.6969853, 2.1006537, 3.7488443, 5.6673754, 4.4112136, 2.3716204,
4.6178643, 5.9948046, 3.4105954, 3.3935850, 1.9547595, 0.4475800,
1.1434170, 0.5842667, 2.9121888, 0.0586379, 5.7492774, 4.0384655,
0.0089162, 0.1909163, 1.3098570, 2.8586366, 0.7996361, 0.0543350,
4.5683759, 2.2249794, 4.9036865, 2.7435946, 2.7429546, 0.3092155,
0.3118464, 0.5723993, 3.7324447, 1.5147758, 5.2864780, 5.3860266,
6.0545540, 3.0718480, 1.3842492, 1.4213108, 3.3727372, 4.7884765,
2.1838288, 2.8980046, 4.0169897, 5.7637923, 1.0151904, 4.4964699,
3.6300404, 2.7224978, 5.5558613, 2.4696170, 1.1245340, 3.9793522,
3.9207111, 2.0605178, 5.0451799, 6.2799046, 6.1636676, 0.7981966,
1.4592079, 0.1484872, 3.8166117, 0.6962355, 2.5601436, 5.5548184,
3.4440198, 2.3185147, 1.3090764, 2.7705283, 6.0079576, 0.7792778,
2.9578927, 5.3840384, 0.2726304, 4.3456090, 6.1511471, 1.7798247,
0.8405677, 4.3057392, 5.7142715, 3.8382030, 5.6547587, 1.2153801,
4.7401894, 2.1756202, 2.6303011, 0.9784166, 5.1459324, 3.9265103,
4.6405120, 5.0586705, 0.4223724, 5.9739917, 3.1263686, 4.7447217,
4.6646686, 5.2221411, 0.9833301, 2.8733554, 3.8836400, 5.8570808,
-5.2470141, 5.6261119, 3.6600718, 3.6615062, 5.3716581, 0.2190677,
-5.5632585, 2.5618482, 0.2285950, 4.6881858, 0.9728179, 0.9042027,
-3.8073530, 1.5989503, 2.0367209, 2.5245268, 2.5533189, 2.4265105,
-3.8314979, 1.0486053, 1.1818174, 0.5945707, 2.0306392, 4.8355201,
-1.4710068, 4.6518534, 4.3531065, 5.1778361, 5.2023364, 1.8432851,
-1.9438243, 3.2862931, 2.0439139, 5.2266206, 5.0912323, 3.4997233,
-1.6522518, 4.2761236, 1.4680860, 2.8678051, 2.4163051, 3.3841326,
-6.2310582, 4.7451897, 6.1603795, 1.4751828, 3.3210347, 0.3231823,
-4.7555888, 3.7823504, 5.3857498, 6.2095284, 5.8401232, 2.5730582,
-0.0021455, 3.3984387, 1.3052100, 1.3777994, 2.0471011, 0.6028680,
-4.6968925, 4.7030205, 3.4136510, 2.1245480, 5.2297066, 3.4719134,
-6.0164208, 5.6098372, 2.2399783, 3.4331443, 2.1782657, 3.9131853,
-5.0053405, 4.6864702, 0.7887674, 5.1672539, 0.1580253, 2.6039335,
-4.5955687, 4.9095176, 2.3077255, 4.6801428, 5.6062801, 1.5243220,
-0.8142818, 1.4141432, 2.1992023, 1.8038058, 5.8275790, 0.3224138,
-3.7238350, 1.0235240, 5.2678588, 1.0528164, 3.1554195, 6.2789723,
-2.2330890, 0.2957980, 1.3424690, 2.4996969, 2.0964990, 1.4426353,
-5.8818165, 4.2926017, 6.0451393, 2.7518666, 5.9083095, 0.0366581,
-3.8346722, 5.0333074, 1.4638661, 5.8588735, 4.7957215, 5.1927356,
-3.6031780, 4.9799375, 2.0674268, 1.4040530, 1.9627813, 3.6726693,
-5.2145043, 1.8250297, 2.5293238, 5.4164658, 3.8625225, 6.2278165,
-1.2798778, 5.1975080, 4.2465638, 1.5641957, 2.9894493, 2.5074636,
-3.7663816, 5.0298329, 0.6601666, 5.1612735, 5.2847013, 2.2274284,
-2.7022061, 3.5954850, 4.4034117, 4.6650751, 4.7619266, 2.4449681,
-2.6973871, 6.0088907, 3.6000853, 5.3389611
};

42
DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c
View file

@ -442,32 +442,32 @@ CONV_DEFINE_TEST(conv_partial_opt , q7 , q7_t , CONV_PARTIAL_TEST_TEMPL
JTEST_DEFINE_GROUP(conv_tests)
{
/*
To skip a test, comment it out.
*/
JTEST_TEST_CALL(arm_conv_f32_tests);
JTEST_TEST_CALL(arm_conv_q31_tests);
JTEST_TEST_CALL(arm_conv_q15_tests);
JTEST_TEST_CALL(arm_conv_q7_tests);
/*
To skip a test, comment it out.
*/
JTEST_TEST_CALL(arm_conv_f32_tests);
JTEST_TEST_CALL(arm_conv_q31_tests);
JTEST_TEST_CALL(arm_conv_q15_tests);
JTEST_TEST_CALL(arm_conv_q7_tests);
JTEST_TEST_CALL(arm_conv_opt_q15_tests);
JTEST_TEST_CALL(arm_conv_opt_q7_tests);
JTEST_TEST_CALL(arm_conv_opt_q15_tests);
JTEST_TEST_CALL(arm_conv_opt_q7_tests);
JTEST_TEST_CALL(arm_conv_fast_q31_tests);
JTEST_TEST_CALL(arm_conv_fast_q15_tests);
JTEST_TEST_CALL(arm_conv_fast_q31_tests);
JTEST_TEST_CALL(arm_conv_fast_q15_tests);
JTEST_TEST_CALL(arm_conv_fast_opt_q15_tests);
JTEST_TEST_CALL(arm_conv_fast_opt_q15_tests);
JTEST_TEST_CALL(arm_conv_partial_f32_tests);
JTEST_TEST_CALL(arm_conv_partial_q31_tests);
JTEST_TEST_CALL(arm_conv_partial_q15_tests);
JTEST_TEST_CALL(arm_conv_partial_q7_tests);
JTEST_TEST_CALL(arm_conv_partial_f32_tests);
JTEST_TEST_CALL(arm_conv_partial_q31_tests);
JTEST_TEST_CALL(arm_conv_partial_q15_tests);
JTEST_TEST_CALL(arm_conv_partial_q7_tests);
JTEST_TEST_CALL(arm_conv_partial_fast_q31_tests);
JTEST_TEST_CALL(arm_conv_partial_fast_q15_tests);
JTEST_TEST_CALL(arm_conv_partial_fast_q31_tests);
JTEST_TEST_CALL(arm_conv_partial_fast_q15_tests);
JTEST_TEST_CALL(arm_conv_partial_fast_opt_q15_tests);
JTEST_TEST_CALL(arm_conv_partial_fast_opt_q15_tests);
JTEST_TEST_CALL(arm_conv_partial_opt_q15_tests);
JTEST_TEST_CALL(arm_conv_partial_opt_q7_tests);
JTEST_TEST_CALL(arm_conv_partial_opt_q15_tests);
JTEST_TEST_CALL(arm_conv_partial_opt_q7_tests);
}

2
DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c
View file

@ -10,7 +10,7 @@ float32_t filtering_output_ref[LMS_MAX_BLOCKSIZE*2] = {0};
float32_t filtering_output_f32_fut[LMS_MAX_BLOCKSIZE*2] = {0};
float32_t filtering_output_f32_ref[LMS_MAX_BLOCKSIZE*2] = {0};
float32_t filtering_input_lms[LMS_MAX_BLOCKSIZE*2] = {0};
float32_t filtering_pState[LMS_MAX_BLOCKSIZE + FILTERING_MAX_NUMTAPS] = {0};
__ALIGNED(8) float32_t filtering_pState[LMS_MAX_BLOCKSIZE + FILTERING_MAX_NUMTAPS] = {0};
float32_t filtering_scratch[FILTERING_MAX_BLOCKSIZE * 3] = {0};
float32_t filtering_scratch2[FILTERING_MAX_BLOCKSIZE * 3] = {0};
float32_t filtering_coeffs_lms[FILTERING_MAX_NUMTAPS];

20
DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c
View file

@ -3,15 +3,15 @@
JTEST_DEFINE_GROUP(filtering_tests)
{
/*
To skip a test, comment it out.
*/
JTEST_GROUP_CALL(biquad_tests);
JTEST_GROUP_CALL(conv_tests);
JTEST_GROUP_CALL(correlate_tests);
JTEST_GROUP_CALL(fir_tests);
JTEST_GROUP_CALL(iir_tests);
JTEST_GROUP_CALL(lms_tests);
/*
To skip a test, comment it out.
*/
JTEST_GROUP_CALL(biquad_tests);
JTEST_GROUP_CALL(conv_tests);
JTEST_GROUP_CALL(correlate_tests);
JTEST_GROUP_CALL(fir_tests);
JTEST_GROUP_CALL(iir_tests);
JTEST_GROUP_CALL(lms_tests);
return;
return;
}

8
DSP/DSP_Lib_TestSuite/Common/src/main.c
View file

@ -3,8 +3,8 @@
#include "arm_math.h"
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
asm(" .global __ARM_use_no_argv\n");
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && !defined (__MICROLIB)
__asm(" .global __ARM_use_no_argv\n");
#endif
@ -16,12 +16,16 @@ void debug_init(void)
int main(void)
{
#if !defined(FILEIO)
debug_init();
#endif
JTEST_INIT(); /* Initialize test framework. */
JTEST_GROUP_CALL(all_tests); /* Run all tests. */
JTEST_ACT_EXIT_FW(); /* Exit test framework. */
#if !defined(FILEIO)
while (1); /* Never return. */
#endif
}

30
DSP/DSP_Lib_TestSuite/Common/src/math_helper.c
View file

@ -64,7 +64,7 @@ float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
if (temp == 0x7FC00000)
{
return(0);
return(100000.0);
}
/* Checking for a NAN value in pTest array */
@ -73,7 +73,7 @@ float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
if (temp == 0x7FC00000)
{
return(0);
return(100000.0);
}
EnergySignal += pRef[i] * pRef[i];
EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
@ -85,12 +85,21 @@ float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
if (temp == 0x7FC00000)
{
return(0);
return(100000.0);
}
SNR = 10 * log10f (EnergySignal / EnergyError);
/* Checking for a NAN value in SNR */
test = (int *)(&SNR);
temp = *test;
if (temp == 0x7FC00000)
{
return(100000.0);
}
return (SNR);
}
@ -113,7 +122,7 @@ double arm_snr_f64(double *pRef, double *pTest, uint32_t buffSize)
if (temp == 0x7FC00000)
{
return(0);
return(100000.0);
}
/* Checking for a NAN value in pTest array */
@ -122,7 +131,7 @@ double arm_snr_f64(double *pRef, double *pTest, uint32_t buffSize)
if (temp == 0x7FC00000)
{
return(0);
return(100000.0);
}
EnergySignal += pRef[i] * pRef[i];
EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
@ -134,12 +143,21 @@ double arm_snr_f64(double *pRef, double *pTest, uint32_t buffSize)
if (temp == 0x7FC00000)
{
return(0);
return(100000.0);
}
SNR = 10 * log10 (EnergySignal / EnergyError);
/* Checking for a NAN value in SNR */
test = (int *)(&SNR);
temp = *test;
if (temp == 0x7FC00000)
{
return(10000.0);
}
return (SNR);
}

8
DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c
View file

@ -45,7 +45,10 @@ arm_matrix_instance_f64 matrix_output_ref64 = {
* Pool of random data to base matrix inputs from.
*/
float32_t matrix_f32_100_rand[100] = {
-45.0345569674258, -11.0261163038747, -14.6841428777929,
/* -45.0345569674258, first number negativ causes fault in 1x1 multiplay with 0.
AC6 DSP_Lib calculatas a -0.0 which is not a 0.0 in memcmp!
*/
45.0345569674258, -11.0261163038747, -14.6841428777929,
0.0345569674258, -11.0261163038747, -14.6841428777929,
-20.3679194392227, 27.5712678608402, -12.1390617339732,
-19.8753669720509, 42.3379642103244, -23.7788252219155,
@ -82,7 +85,8 @@ float32_t matrix_f32_100_rand[100] = {
};
float64_t matrix_f64_100_rand[100] = {
-45.0345569674258, -11.0261163038747, -14.6841428777929,
// -45.0345569674258, -11.0261163038747, -14.6841428777929,
45.0345569674258, -11.0261163038747, -14.6841428777929,
0.0345569674258, -11.0261163038747, -14.6841428777929,
-20.3679194392227, 27.5712678608402, -12.1390617339732,
-19.8753669720509, 42.3379642103244, -23.7788252219155,

382
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx
View file

@ -101,7 +101,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -138,7 +140,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF"../cortexM0l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -185,6 +187,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -268,7 +274,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -285,7 +293,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF"../cortexM3l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -332,6 +340,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -415,7 +427,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -432,7 +446,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"../cortexM4l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -479,6 +493,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -562,7 +580,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -599,7 +619,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4lf_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -646,6 +666,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -729,7 +753,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -766,7 +792,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -813,6 +839,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -896,7 +926,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -933,7 +965,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7lfsp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -980,6 +1012,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1063,7 +1099,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -1080,7 +1118,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"../cortexM7lfdp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -1127,6 +1165,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1210,6 +1252,8 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
@ -1242,7 +1286,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMv8MBLl_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -1289,6 +1333,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1372,6 +1420,8 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
@ -1389,7 +1439,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLl_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -1436,6 +1486,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1519,6 +1573,8 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
@ -1551,7 +1607,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_FP_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLlfsp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -1598,141 +1654,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
</TargetOption>
</Target>
<Target>
<TargetName>ARMv8MMLlfdp.DoNotUse</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>0</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\IntermediateFiles\ARMv8MMLlfdp\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>1</uSim>
<uTrg>0</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>-1</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon></pMon>
</DebugOpt>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1816,6 +1741,8 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
@ -1848,7 +1775,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLld_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -1895,6 +1822,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1978,6 +1909,8 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
@ -2010,7 +1943,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLldfsp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -2057,141 +1990,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
</TargetOption>
</Target>
<Target>
<TargetName>ARMv8MMLldfdp.DoNotUse</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>0</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\IntermediateFiles\ARMv8MMLldfdp\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>1</uSim>
<uTrg>0</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>-1</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon></pMon>
</DebugOpt>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -2705,7 +2507,7 @@
<GroupNumber>8</GroupNumber>
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Common\src\controller_tests\pid_reset_tests.c</PathWithFileName>

2003
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx
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3068
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/DspLibTest_FVP.uvoptx Normal file
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10151
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/DspLibTest_FVP.uvprojx Normal file
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4
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Lib/.gitignore vendored Normal file
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@ -0,0 +1,4 @@
# Ignore everything in this directory
*
# Except this file
!.gitignore

4
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCLANG/Logs/.gitignore vendored Normal file
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@ -0,0 +1,4 @@
# Ignore everything in this directory
*
# Except this file
!.gitignore

163
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt
View file

@ -1,163 +0,0 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]
fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address
fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
#----------------------------------------------------------------------------------------------

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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]
fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb
fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address
fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot
fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot
fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
#----------------------------------------------------------------------------------------------

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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]
fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb
fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address
fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot
fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot
fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
#----------------------------------------------------------------------------------------------

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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]
fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb
fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address
fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot
fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot
fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
#----------------------------------------------------------------------------------------------

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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]
cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]
cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]
cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8]
cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset
cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write
cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write
cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write
cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]
fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb
fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address
fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component
fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS
fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot
fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot
fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
#----------------------------------------------------------------------------------------------

11
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MBLl_config.txt Normal file
View file

@ -0,0 +1,11 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------

13
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLl_config.txt Normal file
View file

@ -0,0 +1,13 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------

13
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLld_config.txt Normal file
View file

@ -0,0 +1,13 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------

13
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLldfsp_config.txt Normal file
View file

@ -0,0 +1,13 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------

13
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMv8MMLlfsp_config.txt Normal file
View file

@ -0,0 +1,13 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------

380
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx
View file

@ -101,7 +101,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -138,7 +140,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF"..\cortexM0l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -185,6 +187,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -268,7 +274,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -285,7 +293,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M3_MDK" -L"armcortexm3ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M3_MDK.exe" -MF"..\cortexM3l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -332,6 +340,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -415,7 +427,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -432,7 +446,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -479,6 +493,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -562,7 +580,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -599,7 +619,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M4_MDK" -L"armcortexm4ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M4_MDK.exe" -MF"..\cortexM4lf_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -646,6 +666,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -729,7 +753,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -766,7 +792,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7l_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -813,6 +839,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -896,7 +926,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -933,7 +965,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7lfsp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -980,6 +1012,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1063,7 +1099,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>4</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -1080,7 +1118,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFM</Key>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF -MA</Name>
<Name>-I -S"System Generator:FVP_MPS2_Cortex_M7_MDK" -L"armcortexm7ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M7_MDK.exe" -MF"..\cortexM7lfdp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -1127,6 +1165,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1210,6 +1252,8 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
@ -1242,7 +1286,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMv8MBLl_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -1289,6 +1333,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1372,6 +1420,8 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
@ -1389,7 +1439,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLl_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -1436,6 +1486,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1519,6 +1573,8 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
@ -1551,7 +1607,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_FP_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLlfsp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -1598,141 +1654,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
</TargetOption>
</Target>
<Target>
<TargetName>ARMv8MMLlfdp.DoNotUse</TargetName>
<ToolsetNumber>0x3</ToolsetNumber>
<ToolsetName>ARM-GNU</ToolsetName>
<TargetOption>
<CLKARM>12000000</CLKARM>
<OPTTT>
<gFlags>0</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>120</PageWidth>
<PageLength>65</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\IntermediateFiles\ARMv8MMLlfdp\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
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<sDlgPa></sDlgPa>
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<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon></pMon>
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<trace>0</trace>
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<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1816,6 +1741,8 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
@ -1848,7 +1775,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLld_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -1895,6 +1822,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
@ -1978,6 +1909,8 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
@ -2010,7 +1943,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_config.txt" -MA</Name>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMv8MMLldfsp_config.txt" -MA"-Q 1"</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -2057,141 +1990,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
</TargetOption>
</Target>
<Target>
<TargetName>ARMv8MMLldfdp.DoNotUse</TargetName>
<ToolsetNumber>0x3</ToolsetNumber>
<ToolsetName>ARM-GNU</ToolsetName>
<TargetOption>
<CLKARM>12000000</CLKARM>
<OPTTT>
<gFlags>0</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
<RunAbUc>0</RunAbUc>
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<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
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<HexOffset>0</HexOffset>
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<PageWidth>120</PageWidth>
<PageLength>65</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\IntermediateFiles\ARMv8MMLldfdp\</ListingPath>
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1592
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx
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8
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM0l_config.txt Normal file
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@ -0,0 +1,8 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm0ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm0ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm0ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

8
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM3l_config.txt Normal file
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@ -0,0 +1,8 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm3ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm3ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm3ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

9
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4l_config.txt Normal file
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@ -0,0 +1,9 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm4ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

9
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM4lf_config.txt Normal file
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@ -0,0 +1,9 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

9
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7l_config.txt Normal file
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@ -0,0 +1,9 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm7ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

9
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfdp_config.txt Normal file
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@ -0,0 +1,9 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

9
DSP/DSP_Lib_TestSuite/DspLibTest_FVP/cortexM7lfsp_config.txt Normal file
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@ -0,0 +1,9 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

273
DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/.cproject Normal file
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<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value="${workspace_loc:/DspLibTest_FVP_A5/Debug/DspLibTest_FVP_A5.axf}"/>
<intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="1"/>
<listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
<listEntry value="ON_DEMAND_LOAD"/>
<listEntry value="ALSO_LOAD_SYMBOLS"/>
</listAttribute>
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
<intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
<listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
<listEntry value="ON_DEMAND_LOAD"/>
<listEntry value="ALSO_LOAD_SYMBOLS"/>
</listAttribute>
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
<intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
<stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
<stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
<booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
<booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="false"/>
<stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value=""/>
<booleanAttribute key="KEY_COMMANDS_AS_CONNECT" value="false"/>
<stringAttribute key="RSE_CONFIGURATION" value=""/>
<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
<booleanAttribute key="VFS_ENABLED" value="true"/>
<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;breakpoints&gt;&#10;&lt;/breakpoints&gt;&#10;"/>
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.addresses">
<listEntry value="&lt;Next Instruction&gt;"/>
</listAttribute>
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.ranges">
<listEntry value="100"/>
</listAttribute>
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.MemoryView.addresses">
<listEntry value=""/>
</listAttribute>
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.MemoryView.ranges">
<listEntry value=""/>
</listAttribute>
<stringAttribute key="com.arm.debug.views.debugConsole.DebugCommandLine.History" value="set semihosting disabled;set ?;set help;info set;armclang.exe"/>
<stringAttribute key="config_db_activity_name" value="Debug Cortex-A5"/>
<stringAttribute key="config_db_connection_keys" value="dtsl_config dtsl_tracecapture_option dtsl_config_script model_params config_file setup TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
<stringAttribute key="config_db_platform_name" value="Arm FVP (Installed with Arm DS) - VE_Cortex_A5x1"/>
<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
<stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp_installedwitharmds_/ve_cortex_a5x1"/>
<stringAttribute key="config_file" value="CDB://cadi_config.xml"/>
<booleanAttribute key="connectOnly" value="false"/>
<listAttribute key="debugger.view.DisassemblyView:current">
<listEntry value="&lt;Next Instruction&gt;"/>
<listEntry value="100"/>
</listAttribute>
<stringAttribute key="debugger.view.MemoryView" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;page&gt;&#10;&#9;&lt;memoryView/&gt;&#10;&lt;/page&gt;&#10;"/>
<listAttribute key="debugger.view.MemoryView:current">
<listEntry value=""/>
<listEntry value=""/>
</listAttribute>
<stringAttribute key="debugger.view.NewRegisterView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;49&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;45&#9;-1&#9;true&#9;3&#9;false&#9;true&#9;42&#9;-1&#9;true&#9;4&#9;false&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;37&#9;-1&#9;true&#9;6&#9;false&#9;true&#9;62&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;53&#9;-1&#9;true"/>
<stringAttribute key="debugger.view.NewRegisterView:_selectedRegisterSet" value="All registers"/>
<mapAttribute key="debugger.view.NewRegisterView_registerSets"/>
<listAttribute key="debugger.view.TraceView:TRACE_EXPORT_FILTERS"/>
<stringAttribute key="debugger.view.VariableTreeView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;149&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;95&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;42&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;37&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;62&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;53&#9;-1&#9;true"/>
<listAttribute key="debugger.view.VariableTreeView:USER_ADDED_FILE_STATICS"/>
<listAttribute key="debugger.view.VariableTreeView:USER_ADDED_GLOBALS"/>
<booleanAttribute key="debugger.view.register.DrawAsHex" value="false"/>
<booleanAttribute key="debugger.view.variable.DrawAsHex" value="false"/>
<stringAttribute key="dtsl_config" value="DtslScript"/>
<stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
<stringAttribute key="dtsl_options_file" value="default"/>
<stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
<stringAttribute key="launch_configuration_version" value="2018.0"/>
<booleanAttribute key="linuxOS" value="false"/>
<stringAttribute key="model_params" value=""/>
<booleanAttribute key="runAfterConnect" value="false"/>
<listAttribute key="setup">
<listEntry value="CDB://Scripts/rtsm_launcher.py"/>
<listEntry value="&quot;FVP_VE_Cortex-A5x1&quot;"/>
</listAttribute>
<booleanAttribute key="single_platform" value="false"/>
<stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
<stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;watchpoints&gt;&#10;&lt;/watchpoints&gt;&#10;"/>
</launchConfiguration>

83
DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/DspLibTest_FVP_A5.rteconfig Normal file
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@ -0,0 +1,83 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
<toolchain Tcompiler="ARMCC" Toutput="exe"/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.1.3">
<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
<file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/>
<file category="include" name="CMSIS/Core_A/Include/"/>
</component>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cvendor="ARM" Cversion="5.5.0">
<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
<file category="doc" name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
<file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
<file attr="config" category="header" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.5.0"/>
<file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.1.0"/>
<file attr="config" category="source" name="CMSIS/RTOS2/RTX/Config/handlers.c" version="5.1.0"/>
<file attr="template" category="source" name="CMSIS/RTOS2/RTX/Template/main.c" select="CMSIS-RTOS2 'main' function" version="2.1.0"/>
<file attr="template" category="source" name="CMSIS/RTOS2/RTX/Template/Events.c" select="CMSIS-RTOS2 Events" version="2.0.0"/>
<file attr="template" category="source" name="CMSIS/RTOS2/RTX/Template/MemPool.c" select="CMSIS-RTOS2 Memory Pool" version="2.0.0"/>
<file attr="template" category="source" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c" select="CMSIS-RTOS2 Message Queue" version="2.0.0"/>
<file attr="template" category="source" name="CMSIS/RTOS2/RTX/Template/Mutex.c" select="CMSIS-RTOS2 Mutex" version="2.0.0"/>
<file attr="template" category="source" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" select="CMSIS-RTOS2 Semaphore" version="2.0.0"/>
<file attr="template" category="source" name="CMSIS/RTOS2/RTX/Template/Thread.c" select="CMSIS-RTOS2 Thread" version="2.0.0"/>
<file attr="template" category="source" name="CMSIS/RTOS2/RTX/Template/Timer.c" select="CMSIS-RTOS2 Timer" version="2.0.1"/>
<file attr="template" category="source" name="CMSIS/RTOS2/RTX/Template/svc_user.c" select="CMSIS-RTOS2 SVC User Table" version="1.0.0"/>
<file category="other" name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
<file category="source" condition="CA_ARMCC5" name="CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s"/>
<file category="source" condition="CA_ARMCC6" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"/>
</component>
<component Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.1" deviceDependent="1">
<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
<file category="sourceC" deviceDependent="1" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
</component>
<component Capiversion="1.0.1" Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Cvendor="ARM" Cversion="1.0.2" deviceDependent="1">
<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
<file category="sourceC" deviceDependent="1" name="CMSIS/RTOS2/Source/os_tick_ptim.c"/>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
<file category="include" deviceDependent="1" name="Device/ARM/ARMCA5/Include/"/>
<file attr="config" category="sourceC" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0"/>
<file attr="config" category="linkerScript" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct" version="1.0.0"/>
<file attr="config" category="sourceC" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0"/>
<file attr="config" category="linkerScript" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct" version="1.0.0"/>
<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA5/Source/system_ARMCA5.c" version="1.0.1"/>
<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c" version="1.0.0"/>
<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA5/Include/system_ARMCA5.h" version="1.0.0"/>
<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h" version="1.0.0"/>
</component>
</components>
<apis>
<api Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Cvendor="ARM" Cversion="2.1.3" exclusive="1">
<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
<file category="doc" name="CMSIS/Documentation/RTOS2/html/index.html"/>
<file category="header" name="CMSIS/RTOS2/Include/cmsis_os2.h"/>
</api>
<api Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Cvendor="ARM" Cversion="1.0.0" exclusive="1">
<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
<file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
</api>
<api Capiversion="1.0.1" Cclass="Device" Cgroup="OS Tick" Cvendor="ARM" Cversion="1.0.1" exclusive="1">
<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
<file category="header" name="CMSIS/RTOS2/Include/os_tick.h"/>
</api>
</apis>
<device Dcore="Cortex-A5" DcoreVersion="r0p1" Dendian="Little-endian" Dfamily="ARM Cortex A5" Dfpu="DP_FPU" Dmpu="MPU" Dname="ARMCA5" Dvendor="ARM:82" info="ARM , 2 MB RAM, 2 MB ROM" url="http://www.keil.com/dd2/arm/armca5">
<package info="CMSIS (Cortex Microcontroller Software Interface Standard)" name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
</device>
<packages useAllLatestPacks="1"/>
</configuration>

63
DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.c Normal file
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@ -0,0 +1,63 @@
/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
for (;;) {}
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
switch (code) {
case osRtxErrorStackUnderflow:
// Stack underflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
break;
}
for (;;) {}
return 0U;
}

578
DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.h Normal file
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@ -0,0 +1,578 @@
/*
* Copyright (c) 2013-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.5.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 4096
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 0
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 1
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 0
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 256
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 512
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 256
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 512
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 256
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 256
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial recording level applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Recording levels for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <h>Memory Management
// <i> Recording level for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MEMORY_LEVEL
#define OS_EVR_MEMORY_LEVEL 0x01U
#endif
// <h>Kernel
// <i> Recording level for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_KERNEL_LEVEL
#define OS_EVR_KERNEL_LEVEL 0x01U
#endif
// <h>Thread
// <i> Recording level for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_THREAD_LEVEL
#define OS_EVR_THREAD_LEVEL 0x05U
#endif
// <h>Generic Wait
// <i> Recording level for Generic Wait events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_WAIT_LEVEL
#define OS_EVR_WAIT_LEVEL 0x01U
#endif
// <h>Thread Flags
// <i> Recording level for Thread Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_THFLAGS_LEVEL
#define OS_EVR_THFLAGS_LEVEL 0x01U
#endif
// <h>Event Flags
// <i> Recording level for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_EVFLAGS_LEVEL
#define OS_EVR_EVFLAGS_LEVEL 0x01U
#endif
// <h>Timer
// <i> Recording level for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_TIMER_LEVEL
#define OS_EVR_TIMER_LEVEL 0x01U
#endif
// <h>Mutex
// <i> Recording level for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MUTEX_LEVEL
#define OS_EVR_MUTEX_LEVEL 0x01U
#endif
// <h>Semaphore
// <i> Recording level for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_SEMAPHORE_LEVEL
#define OS_EVR_SEMAPHORE_LEVEL 0x01U
#endif
// <h>Memory Pool
// <i> Recording level for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MEMPOOL_LEVEL
#define OS_EVR_MEMPOOL_LEVEL 0x01U
#endif
// <h>Message Queue
// <i> Recording level for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MSGQUEUE_LEVEL
#define OS_EVR_MSGQUEUE_LEVEL 0x01U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Generic Wait
// <i> Enables Generic Wait event generation.
#ifndef OS_EVR_WAIT
#define OS_EVR_WAIT 1
#endif
// <q>Thread Flags
// <i> Enables Thread Flags event generation.
#ifndef OS_EVR_THFLAGS
#define OS_EVR_THFLAGS 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#define OS_THREAD_LIBSPACE_NUM 4
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

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/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* Project: CMSIS-RTOS RTX
* Title: Exception handlers (C functions)
*
* -----------------------------------------------------------------------------
*/
#include "RTE_Components.h"
#include CMSIS_device_header
//Fault Status Register (IFSR/DFSR) definitions
#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external
#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
#define FSR_PERMISSION_FAULT_FIRST 0x0f //MMU Fault - internal
#define FSR_PERMISSION_FAULT_SECOND 0x0d //MMU Fault - internal
#define FSR_DEBUG_EVENT 0x02 //internal
#define FSR_SYNC_EXT_ABORT 0x08 //sync/external
#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
#define FSR_LOCKDOWN 0x14 //internal
#define FSR_COPROCESSOR_ABORT 0x1a //internal
#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
switch(FS) {
//Synchronous parity errors - retry
case FSR_SYNC_PARITY_ERROR:
case FSR_SYNC_PARITY_TTB_WALK_FIRST:
case FSR_SYNC_PARITY_TTB_WALK_SECOND:
return;
//Your code here. Value in DFAR is invalid for some fault statuses.
case FSR_ALIGNMENT_FAULT:
case FSR_INSTRUCTION_CACHE_MAINTENANCE:
case FSR_SYNC_EXT_TTB_WALK_FIRST:
case FSR_SYNC_EXT_TTB_WALK_SECOND:
case FSR_TRANSLATION_FAULT_FIRST:
case FSR_TRANSLATION_FAULT_SECOND:
case FSR_ACCESS_FLAG_FAULT_FIRST:
case FSR_ACCESS_FLAG_FAULT_SECOND:
case FSR_DOMAIN_FAULT_FIRST:
case FSR_DOMAIN_FAULT_SECOND:
case FSR_PERMISSION_FAULT_FIRST:
case FSR_PERMISSION_FAULT_SECOND:
case FSR_DEBUG_EVENT:
case FSR_SYNC_EXT_ABORT:
case FSR_TLB_CONFLICT_ABORT:
case FSR_LOCKDOWN:
case FSR_COPROCESSOR_ABORT:
case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
default:
while(1);
}
}
void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
switch(FS) {
//Synchronous parity errors - retry
case FSR_SYNC_PARITY_ERROR:
case FSR_SYNC_PARITY_TTB_WALK_FIRST:
case FSR_SYNC_PARITY_TTB_WALK_SECOND:
return;
//Your code here. Value in IFAR is invalid for some fault statuses.
case FSR_SYNC_EXT_TTB_WALK_FIRST:
case FSR_SYNC_EXT_TTB_WALK_SECOND:
case FSR_TRANSLATION_FAULT_FIRST:
case FSR_TRANSLATION_FAULT_SECOND:
case FSR_ACCESS_FLAG_FAULT_FIRST:
case FSR_ACCESS_FLAG_FAULT_SECOND:
case FSR_DOMAIN_FAULT_FIRST:
case FSR_DOMAIN_FAULT_SECOND:
case FSR_PERMISSION_FAULT_FIRST:
case FSR_PERMISSION_FAULT_SECOND:
case FSR_DEBUG_EVENT: //IFAR invalid
case FSR_SYNC_EXT_ABORT:
case FSR_TLB_CONFLICT_ABORT:
case FSR_LOCKDOWN:
case FSR_COPROCESSOR_ABORT:
default:
while(1);
}
}
//returns amount to decrement lr by
//this will be 0 when we have emulated the instruction and want to execute the next instruction
//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
const int THUMB = 2;
const int ARM = 4;
//Lazy VFP/NEON initialisation and switching
// (ARM ARM section A7.5) VFP data processing instruction?
// (ARM ARM section A7.6) VFP/NEON register load/store instruction?
// (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
// (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
(state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
if (((opcode & 0x00000E00) >> 9) == 5) {
__FPU_Enable();
return state;
}
}
// (ARM ARM section A7.4) NEON data processing instruction?
if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
(state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
// (ARM ARM section A7.7) NEON load/store instruction?
(state == ARM && ((opcode >> 24) == 0xF4)) ||
(state == THUMB && ((opcode >> 24) == 0xF9))) {
__FPU_Enable();
return state;
}
//Add code here for other Undef cases
while(1);
}

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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc
;**************************************************
; Copyright (c) 2017 ARM Ltd. All rights reserved.
;**************************************************
; Scatter-file for RTX Example on Versatile Express
; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
; This platform has 2GB SDRAM starting at 0x80000000.
#include "mem_ARMCA5.h"
SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
{
VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
{
* (RESET, +FIRST) ; Vector table and other startup code
* (InRoot$$Sections) ; All (library) code that must be in a root region
* (+RO-CODE) ; Application RO code (.text)
* (+RO-DATA) ; Application RO data (.constdata)
}
RW_DATA __RAM_BASE __RW_DATA_SIZE
{ * (+RW) } ; Application RW data (.data)
ZI_DATA (__RAM_BASE+
__RW_DATA_SIZE) __ZI_DATA_SIZE
{ * (+ZI) } ; Application ZI data (.bss)
ARM_LIB_HEAP (__RAM_BASE
+__RW_DATA_SIZE
+__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
{ }
ARM_LIB_STACK (__RAM_BASE
+__RAM_SIZE
-__FIQ_STACK_SIZE
-__IRQ_STACK_SIZE
-__SVC_STACK_SIZE
-__ABT_STACK_SIZE
-__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
{ }
UND_STACK (__RAM_BASE
+__RAM_SIZE
-__FIQ_STACK_SIZE
-__IRQ_STACK_SIZE
-__SVC_STACK_SIZE
-__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
{ }
ABT_STACK (__RAM_BASE
+__RAM_SIZE
-__FIQ_STACK_SIZE
-__IRQ_STACK_SIZE
-__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
{ }
SVC_STACK (__RAM_BASE
+__RAM_SIZE
-__FIQ_STACK_SIZE
-__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
{ }
IRQ_STACK (__RAM_BASE
+__RAM_SIZE
-__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
{ }
FIQ_STACK (__RAM_BASE
+__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
{ }
TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
{ }
}

94
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/**************************************************************************//**
* @file mem_ARMCA5.h
* @brief Memory base and size definitions (used in scatter file)
* @version V1.00
* @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __MEM_ARMCA5_H
#define __MEM_ARMCA5_H
/*----------------------------------------------------------------------------
User Stack & Heap size definition
*----------------------------------------------------------------------------*/
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- ROM Configuration ------------------------------------
//
// <h> ROM Configuration
// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x80000000
#define __ROM_SIZE 0x00200000
/*--------------------- RAM Configuration -----------------------------------
// <h> RAM Configuration
// <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <h> Stack / Heap Configuration
// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <h> Exceptional Modes
// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
// </h>
// </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x80200000
#define __RAM_SIZE 0x00200000
#define __RW_DATA_SIZE 0x00100000
#define __ZI_DATA_SIZE 0x000F0000
#define __STACK_SIZE 0x00001000
#define __HEAP_SIZE 0x00008000
#define __UND_STACK_SIZE 0x00000100
#define __ABT_STACK_SIZE 0x00000100
#define __SVC_STACK_SIZE 0x00000100
#define __IRQ_STACK_SIZE 0x00000100
#define __FIQ_STACK_SIZE 0x00000100
/*----------------------------------------------------------------------------*/
/*--------------------- TTB Configuration ------------------------------------
//
// <h> TTB Configuration
// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*----------------------------------------------------------------------------*/
#define __TTB_BASE 0x80500000
#define __TTB_SIZE 0x00004000
#endif /* __MEM_ARMCA5_H */

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/**************************************************************************//**
* @file mmu_ARMCA5.c
* @brief MMU Configuration for ARM Cortex-A5 Device Series
* @version V1.1.0
* @date 23. November 2018
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
Memory Type
0xffffffff |--------------------------| ------------
| FLAG SYNC | Device Memory
0xfffff000 |--------------------------| ------------
| Fault | Fault
0xfff00000 |--------------------------| ------------
| | Normal
| |
| Daughterboard |
| memory |
| |
0x80505000 |--------------------------| ------------
|TTB (L2 Sync Flags ) 4k | Normal
0x80504C00 |--------------------------| ------------
|TTB (L2 Peripherals-B) 16k| Normal
0x80504800 |--------------------------| ------------
|TTB (L2 Peripherals-A) 16k| Normal
0x80504400 |--------------------------| ------------
|TTB (L2 Priv Periphs) 4k | Normal
0x80504000 |--------------------------| ------------
| TTB (L1 Descriptors) | Normal
0x80500000 |--------------------------| ------------
| Heap | Normal
|--------------------------| ------------
| Stack | Normal
0x80400000 |--------------------------| ------------
| ZI Data | Normal
0x80300000 |--------------------------| ------------
| RW Data | Normal
0x80200000 |--------------------------| ------------
| RO Data | Normal
|--------------------------| ------------
| RO Code | USH Normal
0x80000000 |--------------------------| ------------
| Daughterboard | Fault
| HSB AXI buses |
0x40000000 |--------------------------| ------------
| Daughterboard | Fault
| test chips peripherals |
0x2c002000 |--------------------------| ------------
| Private Address | Device Memory
0x2c000000 |--------------------------| ------------
| Daughterboard | Fault
| test chips peripherals |
0x20000000 |--------------------------| ------------
| Peripherals | Device Memory RW/RO
| | & Fault
0x00000000 |--------------------------|
*/
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
// Write-Through support *not* available
// Write-Back support available.
// Read allocation support available.
// Write allocation support available.
//Note: You should use the Shareable attribute carefully.
//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
//Following MMU configuration is expected
//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
//Domain 0 is always the Client domain
//Descriptors should place all memory in domain 0
#include "ARMCA5.h"
// L2 table pointers
//----------------------------------------
#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space
#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization
#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
//--------------------- PERIPHERALS -------------------
#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
//--------------------- SYNC FLAGS --------------------
#define FLAG_SYNC 0xFFFFF000
#define F_SYNC_BASE 0xFFF00000 //1M aligned
//Import symbols from linker
extern uint32_t Image$$VECTORS$$Base;
extern uint32_t Image$$RW_DATA$$Base;
extern uint32_t Image$$ZI_DATA$$Base;
extern uint32_t Image$$TTB$$ZI$$Base;
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
/* Define global descriptors */
static uint32_t Page_L1_4k = 0x0; //generic
static uint32_t Page_L1_64k = 0x0; //generic
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
void MMU_CreateTranslationTable(void)
{
mmu_region_attributes_Type region;
//Create 4GB of faulting entries
MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
/*
* Generate descriptors. Refer to core_ca.h to get information about attributes
*
*/
//Create descriptors for Vectors, RO, RW, ZI sections
section_normal(Sect_Normal, region);
section_normal_cod(Sect_Normal_Cod, region);
section_normal_ro(Sect_Normal_RO, region);
section_normal_rw(Sect_Normal_RW, region);
//Create descriptors for peripherals
section_device_ro(Sect_Device_RO, region);
section_device_rw(Sect_Device_RW, region);
//Create descriptors for 64k pages
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
//Create descriptors for 4k pages
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
/*
* Define MMU flat-map regions and attributes
*
*/
//Define Image
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 2, Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
//all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
//--------------------- PERIPHERALS -------------------
MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_SRAM_BASE , 64, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_USB_BASE , 16, Sect_Device_RW);
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
// Define peripheral range 0x1C000000-0x1C00FFFF
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
// Define peripheral range 0x1C100000-0x1C10FFFF
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
// Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
// Define private address space entry.
MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Define L2CC entry. Uncomment if PL310 is present
// MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
// Define synchronization space entry.
MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
/* Set location of level 1 page table
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
; 13:7 - 0x0
; 6 - IRGN[0] 0x1 (Inner WB WA)
; 5 - NOS 0x0 (Non-shared)
; 4:3 - RGN 0x01 (Outer WB WA)
; 2 - IMP 0x0 (Implementation Defined)
; 1 - S 0x0 (Non-shared)
; 0 - IRGN[1] 0x0 (Inner WB WA) */
__set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 0x48);
__ISB();
/* Set up domain access control register
; We set domain 0 to Client and all other domains to No Access.
; All translation table entries specify domain 0 */
__set_DACR(1);
__ISB();
}

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@ -0,0 +1,138 @@
/******************************************************************************
* @file startup_ARMCA5.c
* @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
* @version V1.00
* @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <ARMCA5.h>
/*----------------------------------------------------------------------------
Definitions
*----------------------------------------------------------------------------*/
#define USR_MODE 0x10 // User mode
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
#define IRQ_MODE 0x12 // Interrupt Request mode
#define SVC_MODE 0x13 // Supervisor mode
#define ABT_MODE 0x17 // Abort mode
#define UND_MODE 0x1B // Undefined Instruction mode
#define SYS_MODE 0x1F // System mode
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void Vectors (void) __attribute__ ((naked, section("RESET")));
void Reset_Handler (void) __attribute__ ((naked));
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector Table
*----------------------------------------------------------------------------*/
void Vectors(void) {
__ASM volatile(
"LDR PC, =Reset_Handler \n"
"LDR PC, =Undef_Handler \n"
"LDR PC, =SVC_Handler \n"
"LDR PC, =PAbt_Handler \n"
"LDR PC, =DAbt_Handler \n"
"NOP \n"
"LDR PC, =IRQ_Handler \n"
"LDR PC, =FIQ_Handler \n"
);
}
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void) {
__ASM volatile(
// Mask interrupts
"CPSID if \n"
// Put any cores other than 0 to sleep
"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
"ANDS R0, R0, #3 \n"
"goToSleep: \n"
"WFINE \n"
"BNE goToSleep \n"
// Reset SCTLR Settings
"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
"ISB \n"
// Configure ACTLR
"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
"LDR R0, =Vectors \n"
"MCR p15, 0, R0, c12, c0, 0 \n"
// Setup Stack for each exceptional mode
"CPS #0x11 \n"
"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
"CPS #0x12 \n"
"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
"CPS #0x13 \n"
"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
"CPS #0x17 \n"
"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
"CPS #0x1B \n"
"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
"CPS #0x1F \n"
"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
// Call SystemInit
"BL SystemInit \n"
// Unmask interrupts
"CPSIE if \n"
// Call __main
"BL __main \n"
);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
while(1);
}

93
DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.c Normal file
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@ -0,0 +1,93 @@
/******************************************************************************
* @file system_ARMCA5.c
* @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
* @version V1.0.1
* @date 13. February 2019
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "irq_ctrl.h"
#define SYSTEM_CLOCK 12000000U
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System Initialization
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
/* do not use global variables because this function is called before
reaching pre-main. RW section may be overwritten afterwards. */
// Invalidate entire Unified TLB
__set_TLBIALL(0);
// Invalidate entire branch predictor array
__set_BPIALL(0);
__DSB();
__ISB();
// Invalidate instruction cache and flush branch target cache
__set_ICIALLU(0);
__DSB();
__ISB();
// Invalidate data cache
L1C_InvalidateDCacheAll();
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
// Enable FPU
__FPU_Enable();
#endif
// Create Translation Table
MMU_CreateTranslationTable();
// Enable MMU
MMU_Enable();
// Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
#if (__L2C_PRESENT == 1)
// Enable GIC
L2C_Enable();
#endif
// IRQ Initialize
IRQ_Initialize();
}

65
DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.h Normal file
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@ -0,0 +1,65 @@
/******************************************************************************
* @file system_ARMCA5.h
* @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series
* @version V1.00
* @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __SYSTEM_ARMCA5_H
#define __SYSTEM_ARMCA5_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/**
\brief Create Translation Table.
Creates Memory Management Unit Translation Table.
*/
extern void MMU_CreateTranslationTable(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_ARMCA5_H */

20
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@ -0,0 +1,20 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: DspLibTest_FVP_A5
* RTE configuration: DspLibTest_FVP_A5.rteconfig
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "ARMCA5.h"
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */
#endif /* RTE_COMPONENTS_H */

34
DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.c Normal file
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@ -0,0 +1,34 @@
/* --------------------------------------------------------------------------
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*---------------------------------------------------------------------------*/
#include <stdio.h>
#include "jtest.h"
#include "all_tests.h"
#include "arm_math.h"
int main (void) {
JTEST_INIT(); /* Initialize test framework. */
JTEST_GROUP_CALL(all_tests); /* Run all tests. */
JTEST_ACT_EXIT_FW(); /* Exit test framework. */
while(1); /* Never return */
}

28
DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/ARM/DspLibTest_MPS2.uvprojx
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@ -334,7 +334,7 @@
<MiscControls></MiscControls>
<Define>ARM_MATH_CM0</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -1175,7 +1175,7 @@
<MiscControls></MiscControls>
<Define>ARM_MATH_CM3</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -2016,7 +2016,7 @@
<MiscControls></MiscControls>
<Define>ARM_MATH_CM4</Define>
<Undefine></Undefine>
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<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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@ -2857,7 +2857,7 @@
<MiscControls></MiscControls>
<Define>ARM_MATH_CM4 __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
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<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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@ -3698,7 +3698,7 @@
<MiscControls></MiscControls>
<Define>ARM_MATH_CM7</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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<Aads>
@ -4539,7 +4539,7 @@
<MiscControls></MiscControls>
<Define>ARM_MATH_CM7 __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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<Aads>
@ -5380,7 +5380,7 @@
<MiscControls></MiscControls>
<Define>ARM_MATH_CM7 __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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</Cads>
<Aads>
@ -6222,7 +6222,7 @@
<MiscControls>-fhonor-nans</MiscControls>
<Define>ARM_MATH_ARMV8MBL</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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</VariousControls>
</Cads>
<Aads>
@ -7064,7 +7064,7 @@
<MiscControls>-Xclang -target-feature -Xclang +t2xtpk -fhonor-nans</MiscControls>
<Define>ARM_MATH_ARMV8MML</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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</Cads>
<Aads>
@ -7906,7 +7906,7 @@
<MiscControls>-Xclang -target-feature -Xclang +t2xtpk -fhonor-nans</MiscControls>
<Define>ARM_MATH_ARMV8MML __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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<Aads>
@ -8748,7 +8748,7 @@
<MiscControls>-Xclang -target-feature -Xclang +t2xtpk -fhonor-nans</MiscControls>
<Define>ARM_MATH_ARMV8MML __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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</Cads>
<Aads>
@ -9590,7 +9590,7 @@
<MiscControls>-Xclang -target-feature -Xclang +t2xtpk -fhonor-nans</MiscControls>
<Define>ARM_MATH_ARMV8MML __DSP_PRESENT=1U</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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</Cads>
<Aads>
@ -10432,7 +10432,7 @@
<MiscControls>-Xclang -target-feature -Xclang +t2xtpk -fhonor-nans</MiscControls>
<Define>ARM_MATH_ARMV8MML __DSP_PRESENT=1U __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
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<Aads>
@ -11274,7 +11274,7 @@
<MiscControls>-Xclang -target-feature -Xclang +t2xtpk -fhonor-nans</MiscControls>
<Define>ARM_MATH_ARMV8MML __DSP_PRESENT=1U __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
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</Cads>
<Aads>

28
DSP/DSP_Lib_TestSuite/DspLibTest_MPS2/GCC/DspLibTest_MPS2.uvprojx
View file

@ -240,7 +240,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections</MiscControls>
<Define>ARM_MATH_CM0</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM0\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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</Carm>
<Aarm>
@ -964,7 +964,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections</MiscControls>
<Define>ARM_MATH_CM3</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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<Aarm>
@ -1688,7 +1688,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections</MiscControls>
<Define>ARM_MATH_CM4</Define>
<Undefine></Undefine>
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</Carm>
<Aarm>
@ -2412,7 +2412,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls>
<Define>ARM_MATH_CM4 __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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<Aarm>
@ -3136,7 +3136,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections</MiscControls>
<Define>ARM_MATH_CM7</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
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<Aarm>
@ -3860,7 +3860,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls>
<Define>ARM_MATH_CM7 __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
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<Aarm>
@ -4584,7 +4584,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -mfpu=fpv5-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls>
<Define>ARM_MATH_CM7 __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
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<Aarm>
@ -5308,7 +5308,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.base</MiscControls>
<Define>ARM_MATH_ARMV8MBL</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MBL\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Carm>
<Aarm>
@ -6032,7 +6032,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main</MiscControls>
<Define>ARM_MATH_ARMV8MML</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Carm>
<Aarm>
@ -6756,7 +6756,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls>
<Define>ARM_MATH_ARMV8MML __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Carm>
<Aarm>
@ -7480,7 +7480,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main -mfpu=fpv5-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls>
<Define>ARM_MATH_ARMV8MML __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Carm>
<Aarm>
@ -8204,7 +8204,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main+dsp</MiscControls>
<Define>ARM_MATH_ARMV8MML __DSP_PRESENT=1U</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Carm>
<Aarm>
@ -8928,7 +8928,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls>
<Define>ARM_MATH_ARMV8MML __DSP_PRESENT=1U __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Carm>
<Aarm>
@ -9652,7 +9652,7 @@
<MiscControls>-fno-strict-aliasing -ffunction-sections -fdata-sections -march=armv8-m.main+dsp -mfpu=fpv5-d16 -mfloat-abi=hard -ffp-contract=off</MiscControls>
<Define>ARM_MATH_ARMV8MML __DSP_PRESENT=1U __FPU_PRESENT=1U</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
<IncludePath>..\..\..\..\Core\Include;..\..\..\Include;..\..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests</IncludePath>
</VariousControls>
</Carm>
<Aarm>

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# Ignore everything in this directory
*
# Except this file
!.gitignore

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# Ignore everything in this directory
*
# Except this file
!.gitignore

11
DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MBLl_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------

13
DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLl_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------

13
DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLld_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------

13
DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLldfsp_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------

13
DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/ARMv8MMLlfsp_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------

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# Ignore everything in this directory
*
# Except this file
!.gitignore

8
DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM0l_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm0ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm0ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm0ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

8
DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM3l_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm3ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm3ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm3ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

9
DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM4l_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm4ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

9
DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM4lf_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm4ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

9
DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM7l_config.txt Normal file
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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm7ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

9
DSP/DSP_Lib_TestSuite/DspLibTest_SV_FVP/cortexM7lfdp_config.txt Normal file
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@ -0,0 +1,9 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support
armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
armcortexm7ct.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
#----------------------------------------------------------------------------------------------

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# Ignore everything in this directory
*
# Except this file
!.gitignore

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# Ignore everything in this directory
*
# Except this file
!.gitignore

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# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
cpu0.min_sync_level=0x3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
cpu0.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------

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