Official ARM version: v5.6.0
This commit is contained in:
rihab kouki
parent
9f95ff5b6b
commit
96d6da4e25
2939 changed files with 339304 additions and 113320 deletions
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@ -1,11 +1,11 @@
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/**************************************************************************//**
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* @file cmsis_armcc.h
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* @brief CMSIS compiler specific macros, functions, instructions
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* @version V1.0.2
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* @date 10. January 2018
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* @version V1.0.3
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* @date 15. May 2019
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -86,6 +86,9 @@
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __COMPILER_BARRIER
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#define __COMPILER_BARRIER() __memory_changed()
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#endif
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/* ########################## Core Instruction Access ######################### */
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/**
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@ -533,10 +536,10 @@ __STATIC_INLINE __ASM void __FPU_Enable(void)
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ENDIF
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//Initialise FPSCR to a known state
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VMRS R2,FPSCR
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LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
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AND R2,R2,R3
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VMSR FPSCR,R2
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VMRS R1,FPSCR
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LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
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AND R1,R1,R2
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VMSR FPSCR,R1
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BX LR
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}
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@ -1,11 +1,11 @@
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/**************************************************************************//**
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* @file cmsis_armclang.h
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* @brief CMSIS compiler specific macros, functions, instructions
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* @version V1.0.2
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* @date 10. January 2018
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* @version V1.1.1
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* @date 15. May 2019
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -102,6 +102,9 @@
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __COMPILER_BARRIER
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#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
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#endif
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/* ########################## Core Instruction Access ######################### */
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/**
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@ -214,7 +217,23 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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\param [in] value Value to count the leading zeros
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\return number of leading zeros in value
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*/
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#define __CLZ (uint8_t)__builtin_clz
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__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
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{
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/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
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__builtin_clz(0) is undefined behaviour, so handle this case specially.
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This guarantees ARM-compatible results if happening to compile on a non-ARM
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target, and ensures the compiler doesn't decide to activate any
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optimisations using the logic "value was passed to __builtin_clz, so it
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is non-zero".
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ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
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single CLZ instruction.
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*/
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if (value == 0U)
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{
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return 32U;
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}
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return __builtin_clz(value);
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}
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/**
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\brief LDR Exclusive (8 bit)
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@ -295,6 +314,68 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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*/
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#define __USAT __builtin_arm_usat
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/* ################### Compiler specific Intrinsics ########################### */
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/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
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Access to dedicated SIMD instructions
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@{
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*/
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#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
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#define __QADD8 __builtin_arm_qadd8
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#define __QSUB8 __builtin_arm_qsub8
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#define __QADD16 __builtin_arm_qadd16
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#define __SHADD16 __builtin_arm_shadd16
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#define __QSUB16 __builtin_arm_qsub16
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#define __SHSUB16 __builtin_arm_shsub16
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#define __QASX __builtin_arm_qasx
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#define __SHASX __builtin_arm_shasx
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#define __QSAX __builtin_arm_qsax
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#define __SHSAX __builtin_arm_shsax
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#define __SXTB16 __builtin_arm_sxtb16
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#define __SMUAD __builtin_arm_smuad
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#define __SMUADX __builtin_arm_smuadx
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#define __SMLAD __builtin_arm_smlad
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#define __SMLADX __builtin_arm_smladx
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#define __SMLALD __builtin_arm_smlald
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#define __SMLALDX __builtin_arm_smlaldx
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#define __SMUSD __builtin_arm_smusd
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#define __SMUSDX __builtin_arm_smusdx
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#define __SMLSDX __builtin_arm_smlsdx
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__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
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{
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int32_t result;
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__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
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{
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int32_t result;
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__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
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((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
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#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
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((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
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__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
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{
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int32_t result;
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__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
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return(result);
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}
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#endif /* (__ARM_FEATURE_DSP == 1) */
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/* ########################### Core Function Access ########################### */
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@ -375,8 +456,8 @@ __STATIC_FORCEINLINE uint32_t __get_SP_usr()
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"MRS %0, cpsr \n"
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"CPS #0x1F \n" // no effect in USR mode
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"MOV %1, sp \n"
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"MSR cpsr_c, %2 \n" // no effect in USR mode
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"ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
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"MSR cpsr_c, %0 \n" // no effect in USR mode
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"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
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);
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return result;
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}
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@ -391,8 +472,8 @@ __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
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"MRS %0, cpsr \n"
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"CPS #0x1F \n" // no effect in USR mode
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"MOV sp, %1 \n"
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"MSR cpsr_c, %2 \n" // no effect in USR mode
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"ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
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"MSR cpsr_c, %0 \n" // no effect in USR mode
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"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
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);
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}
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@ -493,10 +574,11 @@ __STATIC_INLINE void __FPU_Enable(void)
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#endif
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//Initialise FPSCR to a known state
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" VMRS R2,FPSCR \n"
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" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
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" AND R2,R2,R3 \n"
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" VMSR FPSCR,R2 "
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" VMRS R1,FPSCR \n"
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" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
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" AND R1,R1,R2 \n"
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" VMSR FPSCR,R1 "
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: : : "cc", "r1", "r2"
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);
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}
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@ -98,6 +98,10 @@
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __COMPILER_BARRIER
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#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
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#define __COMPILER_BARRIER() (void)0
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#endif
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/*
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@ -144,6 +148,10 @@
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#ifndef __PACKED
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#define __PACKED __packed__
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#endif
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#ifndef __COMPILER_BARRIER
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#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
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#define __COMPILER_BARRIER() (void)0
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#endif
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/*
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@ -190,6 +198,10 @@
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#ifndef __PACKED
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#define __PACKED @packed
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#endif
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#ifndef __COMPILER_BARRIER
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#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
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#define __COMPILER_BARRIER() (void)0
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#endif
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#else
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@ -1,11 +1,11 @@
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/**************************************************************************//**
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* @file cmsis_gcc.h
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* @brief CMSIS compiler specific macros, functions, instructions
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* @version V1.0.2
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* @date 09. April 2018
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* @version V1.2.0
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* @date 17. May 2019
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -37,8 +37,9 @@
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#endif
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/* CMSIS compiler specific defines */
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#ifndef __ASM
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#define __ASM asm
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#define __INLINE inline
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@ -104,6 +105,123 @@
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#ifndef __ALIGNED
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#define __ALIGNED(x) __attribute__((aligned(x)))
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#endif
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#ifndef __COMPILER_BARRIER
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#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
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#endif
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__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
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{
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int32_t result;
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__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
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{
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union llreg_u{
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uint32_t w32[2];
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uint64_t w64;
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} llr;
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llr.w64 = acc;
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#ifndef __ARMEB__ /* Little endian */
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__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
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#else /* Big endian */
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__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
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#endif
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return(llr.w64);
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}
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__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
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{
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int32_t result;
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__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
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((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
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__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
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{
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uint32_t result;
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__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
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return(result);
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}
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__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
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{
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uint32_t result;
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__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
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return(result);
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}
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__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
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{
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union llreg_u{
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uint32_t w32[2];
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uint64_t w64;
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} llr;
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llr.w64 = acc;
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#ifndef __ARMEB__ /* Little endian */
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__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
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#else /* Big endian */
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__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
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#endif
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return(llr.w64);
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}
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__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
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{
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int32_t result;
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__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
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return(result);
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}
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/* ########################## Core Instruction Access ######################### */
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/**
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@ -171,7 +289,7 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
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#else
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uint32_t result;
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__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
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return result;
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#endif
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}
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@ -204,7 +322,7 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
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#else
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int16_t result;
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__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
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return result;
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#endif
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}
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@ -267,7 +385,23 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
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\param [in] value Value to count the leading zeros
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\return number of leading zeros in value
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*/
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#define __CLZ (uint8_t)__builtin_clz
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__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
|
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{
|
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/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
|
||||
__builtin_clz(0) is undefined behaviour, so handle this case specially.
|
||||
This guarantees ARM-compatible results if happening to compile on a non-ARM
|
||||
target, and ensures the compiler doesn't decide to activate any
|
||||
optimisations using the logic "value was passed to __builtin_clz, so it
|
||||
is non-zero".
|
||||
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
|
||||
single CLZ instruction.
|
||||
*/
|
||||
if (value == 0U)
|
||||
{
|
||||
return 32U;
|
||||
}
|
||||
return __builtin_clz(value);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
|
|
@ -667,10 +801,11 @@ __STATIC_INLINE void __FPU_Enable(void)
|
|||
#endif
|
||||
|
||||
//Initialise FPSCR to a known state
|
||||
" VMRS R2,FPSCR \n"
|
||||
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
||||
" AND R2,R2,R3 \n"
|
||||
" VMSR FPSCR,R2 "
|
||||
" VMRS R1,FPSCR \n"
|
||||
" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
||||
" AND R1,R1,R2 \n"
|
||||
" VMSR FPSCR,R1 "
|
||||
: : : "cc", "r1", "r2"
|
||||
);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h
|
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||
* @version V5.0.6
|
||||
* @date 02. March 2018
|
||||
* @version V5.0.7
|
||||
* @date 15. May 2019
|
||||
******************************************************************************/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2018 IAR Systems
|
||||
// Copyright (c) 2018-2019 Arm Limited
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
|
|
@ -69,6 +70,10 @@
|
|||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
|
@ -109,7 +114,12 @@
|
|||
#endif
|
||||
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#if __ICCARM_V8
|
||||
#define __RESTRICT __restrict
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __RESTRICT restrict
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_INLINE
|
||||
|
|
@ -542,10 +552,12 @@ void __FPU_Enable(void)
|
|||
#endif
|
||||
|
||||
//Initialise FPSCR to a known state
|
||||
" VMRS R2,FPSCR \n"
|
||||
" MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
||||
" AND R2,R2,R3 \n"
|
||||
" VMSR FPSCR,R2 \n");
|
||||
" VMRS R1,FPSCR \n"
|
||||
" MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
||||
" AND R1,R1,R2 \n"
|
||||
" VMSR FPSCR,R1 \n"
|
||||
: : : "cc", "r1", "r2"
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_ca.h
|
||||
* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
|
||||
* @version V1.0.1
|
||||
* @date 07. May 2018
|
||||
* @version V1.0.2
|
||||
* @date 12. November 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2009-2018 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -28,13 +28,12 @@
|
|||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CA_H_GENERIC
|
||||
#define __CORE_CA_H_GENERIC
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
|
|
@ -59,7 +58,7 @@
|
|||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#if defined __ARM_FP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue