jaseg
|
89fa266e8f
|
Fix some DRC errors
A bunch of errors remain, but those are all not actually errors.
|
2023-07-14 10:50:29 +02:00 |
|
jaseg
|
a0b4f1382d
|
Prepare outputs for v1 release
|
2023-07-13 13:31:15 +02:00 |
|
jaseg
|
562b3ef4f8
|
Readying v1.0 PCB export
|
2023-07-13 12:40:22 +02:00 |
|
jaseg
|
ce410fcb26
|
Mesh zones WIP
|
2023-07-12 19:43:50 +02:00 |
|
jaseg
|
5af3f8a7b9
|
Layout WIP
|
2023-07-11 18:56:16 +02:00 |
|
jaseg
|
2327d932d3
|
autolayout WIP
|
2023-07-07 20:19:52 +02:00 |
|
jaseg
|
17b7c04960
|
Routing WIP
|
2023-07-07 13:24:15 +02:00 |
|
jaseg
|
fdc7e857e0
|
Layout WIP
|
2023-07-06 20:19:03 +02:00 |
|
jaseg
|
c1ef657e9d
|
PCB placed
|
2023-07-06 14:56:34 +02:00 |
|
jaseg
|
3a2d13fa62
|
layout script WIP
|
2023-07-05 18:20:44 +02:00 |
|
jaseg
|
c9744004ea
|
Initial commit
|
2023-07-05 17:29:05 +02:00 |
|