Add HSM datasheet sources
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3 changed files with 52 additions and 12 deletions
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@ -264,11 +264,11 @@ voltage differential.
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The connecting order of turns was optimized at the assembly level by stacking coils in a particular
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way~\cite{flemingPrinciplesElectricWave1910} and at the component level by winding coils in a particular way to minimize
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the voltage differential between adjacent turns---a technique that is still used to this
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day~\cite{lopeFirstSelfresonantFrequency2021}. The main winding optimization in the first category concerns winding the
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day~\cite{lopeFirstSelfResonant2021}. The main winding optimization in the first category concerns winding the
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turns of a cylindrical multilayer inductor not layer by layer, but instead layering them diagonally, effectively
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connecting adjacent turns in a diagonal zigzag pattern. Then as now, wound inductors applying this technique were not
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feasible to manufacture reliably by machine, but the technique can be closely replicated in PCB inductors as shown in
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\textcite{leePrintedSpiralWinding2011}. The main limiting factors in a PCB implementation are the requirement for a
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\textcite{leePrintedSpiralWinding2011a}. The main limiting factors in a PCB implementation are the requirement for a
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large number of vias inside the inductor's turns limiting the achievable turn count\footnote{In PCBs, as opposed to
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integrated circuits (ICs), vias limit the achievable turn count when they need to be placed in-line inside the turns as
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opposed to on the inside or outside because a PCB's minimum trace/space widths are usually much smaller than the
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@ -366,7 +366,7 @@ two core observations:
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\end{description}
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Setting the inversion count to $k=1$ in our proposed scheme yields the conventional two-layer counterwound
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scheme~\cite{lopeFirstSelfresonantFrequency2021,sproHighVoltageInsulationDesign2021,leePrintedSpiralWinding2011}.
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scheme~\cite{lopeFirstSelfResonant2021,sproHighVoltageInsulationDesign2021,leePrintedSpiralWinding2011a}.
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\begin{figure}
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\begin{center}
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@ -1,7 +1,5 @@
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\chaptertitle{Case Study: Multiparty Computation in Scalable Hardware Security Modules}
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\section{Fast MPC and Slow HSMs}
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Multiparty Computation (MPC) is a cryptographic construct that allows several networked parties to jointly perform a
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computation in such a way that the inputs to the computation remain private to the parties providing them, and no single
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party must be trusted for the computation to produce the correct result. Conceptually, MPC is similar to a secret
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@ -34,17 +32,23 @@ output\footnote{
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protocol.
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}.
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\section{Fast MPC and Slow HSMs}
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MPC is a uniquely powerful cryptographic primitive, yet it has still not found widespread practical adoption. This is
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because MPC is extremely resource-intensive to run. MPC protocols exist on a continuum trading off between extreme
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memory and bandwidth requirements on one end and intense computational requirements on the other end. At a first glance,
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MPC and Hardware Security Modules look like they would complement each other well, but HSMs cannot keep up with the
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intense computational requirements posed by MPC.
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Commercially available HSMs are quoted to perform between X and Y\todo{Look up number range} individual cryptographic
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operations per second. Meanwhile, an MPC protocol doing something as simple as a single AES encryption, corresponding to
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X\todo{look up numbers} logic gates or Y\todo{look up numbers} x86-64 instructions, requires
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\emph{millions}\todo{Validate and add citation} of cryptographic operations when performed in MPC. As a result, applying
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conventional HSMs to MPC at any practical scale is infeasible by multiple orders of magnitude.
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Using P-256 curve ECC key generation as a benchmark, commercially available HSMs are quoted to perform between 3500 and
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22000 cryptographic operations per second~\cite{
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kumarIBMZ16Performance2025,
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ThalesLunaNetwork2024,
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Utrust_GP_HSM_Se_Series_Datasheet_ENpdf,
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}. Meanwhile, an MPC protocol doing something as simple as a single AES encryption, corresponding to 7000 logic
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gates~\cite{wangGlobalScaleSecureMultiparty2017}, requires tens of thousands of cryptographic operations when performed
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in MPC. As a result, applying conventional HSMs to MPC at any practical scale is infeasible by multiple orders of
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magnitude. Literature on MPC commonly uses server hardware as a platform for benchmarks.
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HSMs are slow compared to contemporary computers because they are limited in their power dissipation, and power
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dissipation is largely proportional to processing speed. In the limited fields where HSMs have found commercial
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@ -126,7 +130,7 @@ the logical value $0$ and one $w_i^1$ for the value $1$. The mapping from logic
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randomly by the generator, and unknown to the evaluator~\cite{
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yaoHowGenerateExchange1986,
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beaverComplexitySecureProtocols1990,
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evansPragmaticIntroductionSecure
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evansPragmaticIntroductionSecure,
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}.
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Gates are represented in Yao's GC as truth tables with one row for every combination of input wire values. Each row of
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@ -165,7 +169,7 @@ Practically useful functions such as AES encryption have circuit implementations
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thousands of gates, meaning these costs quickly escalate for practical problem sizes.
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\cite{
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boyarNewCombinationalLogic2010,
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songhoriTinyGarbleHighlyCompressed2015
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songhoriTinyGarbleHighlyCompressed2015,
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}
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% FIXME This entire connecting section
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36
main.bib
36
main.bib
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@ -2442,6 +2442,13 @@
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file = {/home/jaseg/Sync/Research/Zotero/2022_Götte_Scheuermann_Can’t Touch This.pdf}
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}
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@online{Goutimacocom84813320240417,
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title = {Go.Utimaco.Com/l/848133/2024-04-17/3ld3sv/848133/{{1713340754fcnmfM7d}}/u.trust\_{{GP}}\_{{HSM}}\_{{Se}}\_{{Series}}\_{{Datasheet}}\_{{EN}}.Pdf},
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url = {https://go.utimaco.com/l/848133/2024-04-17/3ld3sv/848133/1713340754fcnmfM7d/u.trust_GP_HSM_Se_Series_Datasheet_EN.pdf},
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urldate = {2025-10-27},
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file = {/home/jaseg/Zotero/storage/FZ7VSMEV/u.trust_GP_HSM_Se_Series_Datasheet_EN.html}
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}
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@online{greenbergSignalMoreEncrypted2024,
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title = {Signal {{Is More Than Encrypted Messaging}}. {{Under Meredith Whittaker}}, {{It}}’s {{Out}} to {{Prove Surveillance Capitalism Wrong}}},
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author = {Greenberg, Andy},
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@ -3759,6 +3766,17 @@
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file = {/home/jaseg/Sync/Research/Zotero/2012_Kryjak et al_FPGA implementation of camera tamper detection in real-time.pdf}
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}
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@misc{kumarIBMZ16Performance2025,
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title = {{{IBM}} Z16 {{Performance}} of {{Cryptographic Operations}}: {{Cryptographic Hardware}}: {{CPACF}}, {{CEX8S}} with {{Quantum-Safe CRYSTALS}} Algorithms},
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author = {Kumar, Dinesh},
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date = {2025-03},
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url = {https://www.ibm.com/docs/en/cryptocards?topic=4770-performance},
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urldate = {2025-10-27},
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langid = {english},
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organization = {IBM},
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file = {/home/jaseg/Zotero/storage/NNWPQWCX/Kumar - (Cryptographic Hardware CPACF, CEX8S with Quantum.pdf}
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}
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@article{kvk2019,
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title = {Internet of Things Based Monitoring of Large Rotor Vibration with a Microelectromechanical Systems Accelerometer},
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author = {Koene, Ivar and Viitala, Raine and Kuosmanen, Petri},
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@ -6845,6 +6863,15 @@ Archive 2: https://web.archive.org/web/20250510104017/https://de.linkedin.com/pu
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urldate = {2021-07-08}
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}
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@misc{ThalesLunaNetwork2024,
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title = {Thales {{Luna Network HSM Product Brief}}},
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date = {2024-10},
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url = {https://cpl.thalesgroup.com/sites/default/files/content/product_briefs/luna-sa-network-attached-hsm-pb.pdf},
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urldate = {2025-10-27},
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organization = {Thales},
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file = {/home/jaseg/Zotero/storage/62IF4C9R/luna-sa-network-attached-hsm-pb.pdf}
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}
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@article{tobisch2020,
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title = {Electromagnetic Enclosure {{PUF}} for Tamper Proofing Commodity Hardware and Other Applications},
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author = {Tobisch, Johannes and Zenger, Christian and Paar, Christof},
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@ -6998,6 +7025,15 @@ Archive 2: https://web.archive.org/web/20250510104017/https://de.linkedin.com/pu
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file = {/home/jaseg/Sync/Research/Zotero/2019_Technology_Security Requirements for Cryptographic Modules.pdf}
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}
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@misc{Utrust_GP_HSM_Se_Series_Datasheet_ENpdf,
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title = {U.Trust {{General Purpose HSM Se-Series Datasheet}}},
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date = {2025-04},
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url = {https://utimaco.com/resources/downloads/data-sheets/utrust-general-purpose-hsm-se-series-datasheet},
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urldate = {2025-10-27},
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organization = {utimaco},
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file = {/home/jaseg/Zotero/storage/FV32WI5N/u.trust_GP_HSM_Se_Series_Datasheet_EN.pdf}
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}
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@inproceedings{uzunCryptographicKeyDerivation2021,
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title = {Cryptographic {{Key Derivation}} from {{Biometric Inferences}} for {{Remote Authentication}}},
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booktitle = {Proceedings of the 2021 {{ACM Asia Conference}} on {{Computer}} and {{Communications Security}}},
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