SMPC WIP
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@ -73,6 +73,31 @@ of our design.
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\section{The Fundamentals of Multiparty Computation}
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Secure Multiparty Computation can be separated into two broad classes of approaches: Garbled Circuits, and Secret
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Sharing-based techniques. Garbled Circuit techniques model the computation as a circuit of binary logic components such
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as logic gates. They are well-suited for implementing cryptographic primitives such as conventional symmetric ciphers
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such as AES or hash functions such as the SHA-2 series. Secret Sharing-based techniques model computation as an
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arithmetic circuit made from components such as arithmetic operations. While they can also work in binary, they often
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support operations on larger finite fields. Secret sharing-based techniques are efficient processing integer numbers,
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but can have higher overhead in processing using many bitwise operations such as ciphers or cryptographic hash
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functions.
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\subsection{Security Models in MPC}
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MPC schemes are usually evaluated assuming one of three adversary levels: \emph{Semi-Honest}, \emph{Covert} or
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\emph{Malicious} adversaries. A \emph{Semi-Honest} adversary is an adversary that follows the protocol as specified, but
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that outside the protocol's execution may collude arbitrarily with other parties to reveal the secret inputs of other
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parties. A \emph{Covert} adversary is an adversary that additionally may cheat during the protocol's execution, but only
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in ways that cannot be detected by other parties. Finally, a \emph{Malicious} adversary is one that can deviate from
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the protocol's execution arbitrarily~\cite{aumannSecurityCovertAdversaries2010}. The covert adversary model most closely
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captures the requirements of a real-world scenario where a small number of cooperating parties runs the protocol, since
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in such settings cheating parties can easily be excluded once identified. The malicious adversary model captures
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real-world settings where parties do not have stable identities such as peer-to-peer settings. The semi-honest model is
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mostly interesting as a research tool since protocols assuming a semi-honest adversary can often be upgraded to covert
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or malicious security at some performance tradeoff. In a practical setting, a semi-honest secure MPC protocol would not
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provide additional security over just having one party run the computation except in some situations where inadvertent
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side-channel leakage is a concern.
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\subsection{Fundamental Primitives}
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\subsubsection{Secret Sharing}
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\subsubsection{Oblivious Transfer}
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@ -88,7 +113,6 @@ of our design.
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\subsubsection{OT extensions}
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\subsubsection{Constant-Round MPC}
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\subsection{Security Models in MPC}
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\subsection{Performance}
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@ -96,6 +120,10 @@ of our design.
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\subsection{Solutions}
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\subsection{Hardware Security Applied to MPC}
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Hardware security primitives can be applied in several roles in an MPC protocol.
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\section{A High-Performance IHSM for MPC Applications}
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\subsection{MPC in HSMs}
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@ -108,7 +136,7 @@ see that a single, modern server-class CPU is sufficient for an useful amount of
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A naive implementation might attempt to implement MPC using an HSM by simply offloading all cryptographic operations to
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the HSM. In practice, this is not a workable solution due to the slow processing speed of conventional HSMs.
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Conventional HSMs commonly use smartphone-class SoCs, which lag behind server CPUs in processing speed by several orders
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of magniude.
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of magnitude.
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\todo{Cite some HSM/MPC papers here.}
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In the near term, absent radical developments in either MPC theory or in the speed and power efficiency of processing
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238
main.bib
238
main.bib
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@ -278,7 +278,7 @@
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isbn = {978-1-4503-4139-4}
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}
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@inproceedings{arpPrivacyThreatsUltrasonic2017a,
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@inproceedings{arpPrivacyThreatsUltrasonic2017,
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title = {Privacy {{Threats}} through {{Ultrasonic Side Channels}} on {{Mobile Devices}}},
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booktitle = {2017 {{IEEE European Symposium}} on {{Security}} and {{Privacy}} ({{EuroS}}\&{{P}})},
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author = {Arp, Daniel and Quiring, Erwin and Wressnegger, Christian and Rieck, Konrad},
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@ -337,6 +337,25 @@
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file = {/home/jaseg/Zotero/storage/5RWQFXAC/Attema et al. - 2022 - Efficient Compiler to Covert Security with Public .pdf}
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}
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@article{aumannSecurityCovertAdversaries2010,
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title = {Security {{Against Covert Adversaries}}: {{Efficient Protocols}} for {{Realistic Adversaries}}},
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shorttitle = {Security {{Against Covert Adversaries}}},
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author = {Aumann, Yonatan and Lindell, Yehuda},
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date = {2010-04},
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journaltitle = {Journal of Cryptology},
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shortjournal = {J Cryptol},
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volume = {23},
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number = {2},
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pages = {281--343},
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issn = {0933-2790, 1432-1378},
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doi = {10.1007/s00145-009-9040-7},
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url = {http://link.springer.com/10.1007/s00145-009-9040-7},
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urldate = {2025-08-13},
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abstract = {In the setting of secure multiparty computation, a set of mutually distrustful parties wish to securely compute some joint function of their private inputs. The computation should be carried out in a secure way, meaning that no coalition of corrupted parties should be able to learn more than specified or somehow cause the result to be “incorrect.” Typically, corrupted parties are either assumed to be semi-honest (meaning that they follow the protocol specification) or malicious (meaning that they may deviate arbitrarily from the protocol). However, in many settings, the assumption regarding semi-honest behavior does not suffice and security in the presence of malicious adversaries is excessive and expensive to achieve.},
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langid = {english},
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file = {/home/jaseg/Zotero/storage/95AERGSY/Aumann and Lindell - 2010 - Security Against Covert Adversaries Efficient Pro.pdf}
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}
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@article{awuahNovelCoilDesign2023,
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title = {Novel Coil Design and Analysis for High-Power Wireless Power Transfer with Enhanced {{Q-factor}}},
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author = {Awuah, Charles Marfo and Danuor, Patrick and Moon, Jung-Ick and Jung, Young-Bae},
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@ -375,6 +394,25 @@
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file = {/home/jaseg/Sync/Research/Zotero/Azuma et al_2015_All-photonic quantum repeaters.pdf}
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}
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@incollection{bahmaniSecureMultipartyComputation2017,
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title = {Secure {{Multiparty Computation}} from {{SGX}}},
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booktitle = {Financial {{Cryptography}} and {{Data Security}}},
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author = {Bahmani, Raad and Barbosa, Manuel and Brasser, Ferdinand and Portela, Bernardo and Sadeghi, Ahmad-Reza and Scerri, Guillaume and Warinschi, Bogdan},
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editor = {Kiayias, Aggelos},
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date = {2017},
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volume = {10322},
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pages = {477--497},
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publisher = {Springer International Publishing},
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location = {Cham},
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doi = {10.1007/978-3-319-70972-7_27},
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url = {https://link.springer.com/10.1007/978-3-319-70972-7_27},
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urldate = {2025-08-13},
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abstract = {Isolated Execution Environments (IEE) offered by novel commodity hardware such as Intel’s SGX deployed in Skylake processors permit executing software in a protected environment that shields it from a malicious operating system; it also permits a remote user to obtain strong interactive attestation guarantees on both the code running in an IEE and its input/output behaviour. In this paper we show how IEEs provide a new path to constructing general secure multiparty computation (MPC) protocols. Our protocol is intuitive and elegant: it uses code within an IEE to play the role of a trusted third party (TTP), and the attestation guarantees of SGX to bootstrap secure communications between participants and the TTP. In our protocol the load of communications and computations on participants only depends on the size of each party’s inputs and outputs and is thus small and independent from the intricacy of the functionality to be computed. The remaining computational load– essentially that of computing the functionality – is moved to an untrusted party running an IEE-enabled machine, an appealing feature for Cloud-based scenarios. However, as often the case even with the simplest cryptographic protocols, we found that there is a large gap between this intuitively appealing solution and a protocol with rigorous security guarantees. We bridge this gap through a comprehensive set of results that include: i. a detailed construction of a protocol for secure computation for arbitrary functionalities; ii. formal security definitions for the security of the overall protocol and that of its components; and iii. a modular security analysis of our protocol that relies on a novel notion of labeled attested computation. We implemented and extensively evaluated our solution on SGX-enabled hardware, providing detailed measurements of our protocol as well as comparisons with software-only MPC solutions. Furthermore, we show the cost induced by using constant-time, i.e., timing side channel resilient, code in our implementation.},
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isbn = {978-3-319-70971-0 978-3-319-70972-7},
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langid = {english},
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file = {/home/jaseg/Zotero/storage/N9G2Z329/Bahmani et al. - 2017 - Secure Multiparty Computation from SGX.pdf}
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}
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@inproceedings{baiBatCommEnablingInaudible2020,
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title = {{{BatComm}}: Enabling Inaudible Acoustic Communication with High-Throughput for Mobile Devices},
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shorttitle = {{{BatComm}}},
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@ -1185,6 +1223,24 @@
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file = {/home/jaseg/Sync/Research/Zotero/2010_Choi et al_Quantum key distribution on a 10Gb-s WDM-PON.pdf}
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}
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@article{choiSecureMultipartyComputation2019,
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title = {Secure {{Multiparty Computation}} and {{Trusted Hardware}}: {{Examining Adoption Challenges}} and {{Opportunities}}},
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shorttitle = {Secure {{Multiparty Computation}} and {{Trusted Hardware}}},
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author = {Choi, Joseph I. and Butler, Kevin R. B.},
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date = {2019},
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journaltitle = {Security and Communication Networks},
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volume = {2019},
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number = {1},
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pages = {1368905},
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issn = {1939-0122},
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doi = {10.1155/2019/1368905},
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url = {https://onlinelibrary.wiley.com/doi/abs/10.1155/2019/1368905},
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urldate = {2025-08-13},
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abstract = {When two or more parties need to compute a common result while safeguarding their sensitive inputs, they use secure multiparty computation (SMC) techniques such as garbled circuits. The traditional enabler of SMC is cryptography, but the significant number of cryptographic operations required results in these techniques being impractical for most real-time, online computations. Trusted execution environments (TEEs) provide hardware-enforced isolation of code and data in use, making them promising candidates for making SMC more tractable. This paper revisits the history of improvements to SMC over the years and considers the possibility of coupling trusted hardware with SMC. This paper also addresses three open challenges: (1) defeating malicious adversaries, (2) mobile-friendly TEE-supported SMC, and (3) a more general coupling of trusted hardware and privacy-preserving computation.},
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langid = {english},
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file = {/home/jaseg/Sync/Research/Zotero/Choi_Butler_2019_Secure Multiparty Computation and Trusted Hardware.pdf;/home/jaseg/Zotero/storage/RWQRWK7A/1368905.html}
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}
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@incollection{choudhuriComplexitySecureComputation2020,
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title = {The {{Round Complexity}} of {{Secure Computation Against Covert Adversaries}}},
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booktitle = {Security and {{Cryptography}} for {{Networks}}},
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@ -1329,7 +1385,7 @@
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file = {/home/jaseg/Sync/Research/Zotero/Couteau et al_2021_Silver.pdf}
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}
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@article{cuellarStaticFatigueLifetime1987,
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@article{cuellarStaticFatigueLifetime1987a,
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title = {Static Fatigue Lifetime of Optical Fibers in Bending},
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author = {Cuellar, E. and Roberts, D. and Middleman, L.},
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date = {1987-01-01},
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@ -2177,11 +2233,10 @@
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file = {/home/jaseg/Zotero/storage/PSGQDYRQ/Grisafi et al. - PISTIS Trusted Computing Architecture for Low-end.pdf}
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}
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@standard{GrobkonzeptEPAFuer2023,
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@article{GrobkonzeptEPAFuer2023,
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title = {Grobkonzept ePA für alle},
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date = {2023-12-13},
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langid = {ngerman},
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version = {1.0.0},
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file = {/home/jaseg/Zotero/storage/XRXV6BY6/Grobkonzept ePA für alle.pdf}
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}
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@ -2648,16 +2703,16 @@
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@online{IEEEXploreFullTexta,
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title = {{{IEEE Xplore Full-Text PDF}}:},
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url = {https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6520632},
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||||
url = {https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=8558378},
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urldate = {2024-09-10},
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file = {/home/jaseg/Zotero/storage/PQYCW7K7/stamp.html}
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file = {/home/jaseg/Zotero/storage/HJJK32NF/stamp.html}
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||||
}
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||||
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@online{IEEEXploreFullTextb,
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title = {{{IEEE Xplore Full-Text PDF}}:},
|
||||
url = {https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=8558378},
|
||||
url = {https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6520632},
|
||||
urldate = {2024-09-10},
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||||
file = {/home/jaseg/Zotero/storage/HJJK32NF/stamp.html}
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||||
file = {/home/jaseg/Zotero/storage/PQYCW7K7/stamp.html}
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||||
}
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@www{ika2002,
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@ -3325,11 +3380,11 @@
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issn = {2511-9044, 2511-9044},
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doi = {10.1002/qute.201800011},
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url = {http://arxiv.org/abs/1703.09278},
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urldate = {2024-05-27},
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urldate = {2024-05-02},
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abstract = {Quantum key distribution using weak coherent states and homodyne detection is a promising candidate for practical quantum-cryptographic implementations due to its compatibility with existing telecom equipment and high detection efficiencies. However, despite the actual simplicity of the protocol, the security analysis of this method is rather involved compared to discrete-variable QKD. In this article we review the theoretical foundations of continuous-variable quantum key distribution (CV-QKD) with Gaussian modulation and rederive the essential relations from scratch in a pedagogical way. The aim of this paper is to be as comprehensive and self-contained as possible in order to be well intelligible even for readers with little pre-knowledge on the subject. Although the present article is a theoretical discussion of CV-QKD, its focus lies on practical implementations, taking into account various kinds of hardware imperfections and suggesting practical methods to perform the security analysis subsequent to the key exchange. Apart from a review of well known results, this manuscript presents a set of new original noise models which are helpful to get an estimate of how well a given set of hardware will perform in practice.},
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langid = {english},
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keywords = {Quantum Physics},
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file = {/home/jaseg/Zotero/storage/I7UL2SKX/Laudenbach et al. - 2018 - Continuous-Variable Quantum Key Distribution with .pdf}
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file = {/home/jaseg/Zotero/storage/A2BQHUUW/Laudenbach et al. - 2018 - Continuous-Variable Quantum Key Distribution with .pdf}
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}
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@article{laudenbachContinuousVariableQuantumKey2018a,
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@ -3347,11 +3402,11 @@
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issn = {2511-9044, 2511-9044},
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doi = {10.1002/qute.201800011},
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url = {http://arxiv.org/abs/1703.09278},
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urldate = {2024-05-02},
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urldate = {2024-05-27},
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abstract = {Quantum key distribution using weak coherent states and homodyne detection is a promising candidate for practical quantum-cryptographic implementations due to its compatibility with existing telecom equipment and high detection efficiencies. However, despite the actual simplicity of the protocol, the security analysis of this method is rather involved compared to discrete-variable QKD. In this article we review the theoretical foundations of continuous-variable quantum key distribution (CV-QKD) with Gaussian modulation and rederive the essential relations from scratch in a pedagogical way. The aim of this paper is to be as comprehensive and self-contained as possible in order to be well intelligible even for readers with little pre-knowledge on the subject. Although the present article is a theoretical discussion of CV-QKD, its focus lies on practical implementations, taking into account various kinds of hardware imperfections and suggesting practical methods to perform the security analysis subsequent to the key exchange. Apart from a review of well known results, this manuscript presents a set of new original noise models which are helpful to get an estimate of how well a given set of hardware will perform in practice.},
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langid = {english},
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keywords = {Quantum Physics},
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file = {/home/jaseg/Zotero/storage/A2BQHUUW/Laudenbach et al. - 2018 - Continuous-Variable Quantum Key Distribution with .pdf}
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file = {/home/jaseg/Zotero/storage/I7UL2SKX/Laudenbach et al. - 2018 - Continuous-Variable Quantum Key Distribution with .pdf}
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}
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||||
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@article{laudenbachContinuousVariableQuantumKey2018b,
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@ -3435,7 +3490,7 @@
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file = {/home/jaseg/Zotero/storage/QSDA9K48/Hall - (72) Inventors Alan Henry Leek, Frisco, TX (US);.pdf}
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||||
}
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||||
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@article{leePrintedSpiralWinding2011a,
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@article{leePrintedSpiralWinding2011,
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title = {Printed {{Spiral Winding Inductor With Wide Frequency Bandwidth}}},
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author = {Lee, Chi Kwan and Su, Y. P. and Ron Hui, S. Y.},
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date = {2011-10},
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@ -3637,7 +3692,7 @@
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file = {/home/jaseg/Zotero/storage/WBSKAYAN/Long et al. - 2024 - EM Eye Characterizing Electromagnetic Side-channe.pdf}
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}
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@article{lopeFirstSelfResonant2021,
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@article{lopeFirstSelfresonantFrequency2021,
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title = {First Self‐resonant Frequency of Power Inductors Based on Approximated Corrected Stray Capacitances},
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author = {Lope, Ignacio and Carretero, Claudio and Acero, Jesus},
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date = {2021-02},
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@ -3744,6 +3799,43 @@
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file = {/home/jaseg/Zotero/storage/4PI9MSMM/Lu et al. - 2021 - Correlated Randomness Teleportation via Semi-trust.pdf}
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}
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@incollection{luCorrelatedRandomnessTeleportation2021a,
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title = {Correlated {{Randomness Teleportation}} via {{Semi-trusted Hardware}}—{{Enabling Silent Multi-party Computation}}},
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booktitle = {Computer {{Security}} – {{ESORICS}} 2021},
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author = {Lu, Yibiao and Zhang, Bingsheng and Zhou, Hong-Sheng and Liu, Weiran and Zhang, Lei and Ren, Kui},
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editor = {Bertino, Elisa and Shulman, Haya and Waidner, Michael},
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date = {2021},
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volume = {12973},
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pages = {699--720},
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publisher = {Springer International Publishing},
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location = {Cham},
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doi = {10.1007/978-3-030-88428-4_34},
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url = {https://link.springer.com/10.1007/978-3-030-88428-4_34},
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urldate = {2025-08-13},
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abstract = {With the advancement of the trusted execution environment (TEE) technologies, hardware-supported secure computing becomes increasingly popular due to its efficiency. During the protocol execution, typically, the players need to contact a third-party server for remote attestation, ensuring the validity of the involved trusted hardware component, such as Intel SGX, as well as the integrity of the computation result. When the hardware manufacturer is not fully trusted, sensitive information may be leaked to the third-party server through backdoors, steganography, and kleptography, etc. In this work, we introduce a new security notion called semi-trusted hardware model, where the adversary is allowed to passively or maliciously corrupt the hardware. Therefore, she can learn the input of the hardware component and might also tamper its output. We then show how to utilize such semi-trusted hardwares for correlated randomness teleportation. When the semi-trusted hardware is instantiated by Intel SGX, to generate 10k random OT’s, our protocol is 24X and 450X faster than the EMP-IKNP-ROT in the LAN and WAN setting, respectively. When SGX is used to teleport Garbled circuits, the resulting two-party computation protocol is 5.3-5.7X and 43-47X faster than the EMP-SH2PC in the LAN and WAN setting, respectively, for the AES-128, SHA-256, and SHA-512 evaluation. We also show how to achieve malicious security with little overhead.},
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isbn = {978-3-030-88427-7 978-3-030-88428-4},
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langid = {english},
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file = {/home/jaseg/Zotero/storage/PZAMVZ3L/Lu et al. - 2021 - Correlated Randomness Teleportation via Semi-trust.pdf}
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}
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||||
@article{mahmodSRAMHasNo2025,
|
||||
title = {{{SRAM Has No Chill}}: {{Exploiting Power Domain Separation}} to {{Steal On-Chip Secrets}}},
|
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shorttitle = {{{SRAM Has No Chill}}},
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||||
author = {Mahmod, Jubayer and Hicks, Matthew},
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date = {2025-08},
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journaltitle = {Communications of the ACM},
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||||
shortjournal = {Commun. ACM},
|
||||
volume = {68},
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number = {8},
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||||
pages = {82--90},
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||||
issn = {0001-0782, 1557-7317},
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||||
doi = {10.1145/3725845},
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||||
url = {https://dl.acm.org/doi/10.1145/3725845},
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urldate = {2025-07-29},
|
||||
abstract = {The widespread use of embedded systems has increased the risk of physical memory disclosure attacks. A notable example is the cold boot attack, where attackers exploit DRAM’s temperature-dependent data retention property. At low temperatures, DRAM cells temporarily retain their state after power loss, allowing sensitive data to be recovered. Cold boot attacks can expose system secrets, bypassing defenses like disk encryption. To counter this threat, developers store sensitive data in on-chip SRAM. Unlike DRAM, on-chip SRAM is isolated from external access and, due to its low capacitance, loses data almost immediately when powered off, making it robust against such attacks. While SRAM protects against traditional cold boot attacks, we show that there is another way to retain information in on-chip SRAM across power cycles. This paper presents Volt Boot , an attack that demonstrates a vulnerability of on-chip SRAM due to the physical separation common in modern system-on-chip power distribution networks. Volt Boot leverages asymmetrical power states (for example, on vs. off) to force SRAM state retention across power cycles, eliminating the need for traditional cold boot attack enablers, such as low-temperature or intrinsic data retention time. Using three modern ARM Cortex-A SOCs, we demonstrate the effectiveness of the attack in caches, registers, and iRAMs. Unlike other forms of SRAM data retention attacks, Volt Boot retrieves data with 100\% accuracy—without any complex post-processing.},
|
||||
langid = {english}
|
||||
}
|
||||
|
||||
@article{maierContributionSystemDesign2019,
|
||||
title = {Contribution to the {{System Design}} of {{Contactless Energy Transfer Systems}}},
|
||||
author = {Maier, David and Heinrich, Jörg and Zimmer, Marco and Maier, Marcel and Parspour, Nejila},
|
||||
|
|
@ -4788,18 +4880,7 @@
|
|||
file = {/home/jaseg/Zotero/storage/CCJFZZ34/Paving the Way to Full Security in eHealth – Ensur.pdf}
|
||||
}
|
||||
|
||||
@standard{pcisecuritystandardscouncilPaymentCardIndustry2021,
|
||||
title = {Payment {{Card Industry PIN Transaction Security Hardware Security Module Modular Security Requirements}}},
|
||||
author = {{PCI Security Standards Council}},
|
||||
date = {2021-12},
|
||||
url = {https://docs-prv.pcisecuritystandards.org/PTS/Standard/PCI_HSM_Security_Requirements_v4.pdf},
|
||||
urldate = {2025-04-08},
|
||||
abstract = {HSMs (Hardware Security Modules) play a critical role in helping to ensure the confidentiality and/or data integrity of financial transactions. Therefore, to help engender trust in the legitimacy of the financial transactions being supported, it is imperative that HSMs are appropriately secure during their entire lifecycle. This includes manufacturing, shipment, use, and decommissioning. The purpose of this document is to provide guidance and direction for appropriately designing HSMs to meet the security needs of the financial payments industry, and for protecting those HSMs up to the point of initial deployment. Other security requirements apply at the point of deployment for the management of HSMs involved with financial payments industry. This document provides vendors with a list of all the security requirements against which their products will be evaluated in order to obtain Payment Card Industry (PCI) PIN Transaction Security (PTS) Hardware Security Module (HSM) device approval. HSMs may support a variety of payment-processing and cardholder-authentication applications and processes. The processes relevant to the full set of requirements outlined in this document are: ▪ PIN processing ▪ 3-D Secure ▪ Card verification ▪ Card production and personalization ▪ EFTPOS ▪ ATM interchange ▪ Cash-card reloading ▪ Data integrity ▪ Chip-card transaction processing ▪ Key generation ▪ Key injection There are many other applications and processes that may utilize general-purpose HSMs, and which may necessitate the adoption of all or a subset of the requirements listed in this document. However, this document does not aim to develop a standard for general-purpose HSMs for use outside of applications such as those listed above that are in support of a variety of payment-processing and cardholder- authentication applications and processes for the financial payments industry.},
|
||||
version = {4.0},
|
||||
file = {/home/jaseg/Zotero/storage/CZF34DDM/PCI_HSM_Security_Requirements_v4.pdf}
|
||||
}
|
||||
|
||||
@misc{pcisecuritystandardscouncilPaymentCardIndustry2021a,
|
||||
@misc{pcisecuritystandardscouncilPaymentCardIndustry2021,
|
||||
title = {Payment {{Card Industry PIN Transaction Security Hardware Security Module Modular Derived Test Requirements}}},
|
||||
author = {{PCI Security Standards Council}},
|
||||
date = {2021-12},
|
||||
|
|
@ -5272,6 +5353,76 @@
|
|||
keywords = {Capacitor,Cold electronics,Insulators,Relative permittivity}
|
||||
}
|
||||
|
||||
@patent{salleMultilayerSecurityWrap2015,
|
||||
type = {patentus},
|
||||
title = {Multilayer Security Wrap},
|
||||
author = {Salle, Vincent Daniel Jean and WARD, Dominic John and EDMONDS, Martin Wallace and Zhang, Libing},
|
||||
holder = {{Johnson Electric SA}},
|
||||
date = {2015-12-08},
|
||||
number = {9209139B2},
|
||||
url = {https://patents.google.com/patent/US9209139B2/en?q=(payment+OR+security)&assignee=johnson+electric},
|
||||
urldate = {2025-08-13},
|
||||
langid = {english},
|
||||
keywords = {conductive,screen,security,security screen,terminals},
|
||||
file = {/home/jaseg/Zotero/storage/DXN96WSL/Salle et al. - 2015 - Multilayer security wrap.pdf}
|
||||
}
|
||||
|
||||
@patent{salleSecurityWrap2015,
|
||||
type = {patentus},
|
||||
title = {Security Wrap},
|
||||
author = {Salle, Vincent Daniel Jean and WARD, Dominic John and EDMONDS, Martin Wallace and Zhang, Libing},
|
||||
holder = {{Johnson Electric SA}},
|
||||
date = {2015-12-29},
|
||||
number = {9224280B2},
|
||||
url = {https://patents.google.com/patent/US9224280B2/en?q=(payment+OR+security)&assignee=johnson+electric},
|
||||
urldate = {2025-08-13},
|
||||
langid = {english},
|
||||
keywords = {conductive,pattern,security,security wrap,substrate},
|
||||
file = {/home/jaseg/Zotero/storage/FQSYNFXG/Salle et al. - 2015 - Security wrap.pdf}
|
||||
}
|
||||
|
||||
@patent{salleSecurityWrapBreakable2017,
|
||||
type = {patentus},
|
||||
title = {Security Wrap with Breakable Conductors},
|
||||
author = {Salle, Vincent Daniel Jean and WARD, Dominic John and EDMONDS, Martin Wallace and Zhang, Libing},
|
||||
holder = {{Johnson Electric SA}},
|
||||
date = {2017-02-21},
|
||||
number = {9576450B2},
|
||||
url = {https://patents.google.com/patent/US9576450B2/en?q=(payment+OR+security)&assignee=johnson+electric},
|
||||
urldate = {2025-08-13},
|
||||
langid = {english},
|
||||
keywords = {layer,screen,security,substrate,wrap},
|
||||
file = {/home/jaseg/Sync/Research/Zotero/Salle et al_2017_Security wrap with breakable conductors.pdf}
|
||||
}
|
||||
|
||||
@patent{salleSecurityWrapTearable2017,
|
||||
type = {patentus},
|
||||
title = {Security Wrap with Tearable Substrate},
|
||||
author = {Salle, Vincent Daniel Jean and EDMONDS, Martin Wallace},
|
||||
holder = {{Johnson Electric SA}},
|
||||
date = {2017-08-01},
|
||||
number = {9721199B2},
|
||||
url = {https://patents.google.com/patent/US9721199B2/en?q=(payment+OR+security)&assignee=johnson+electric},
|
||||
urldate = {2025-08-13},
|
||||
langid = {english},
|
||||
keywords = {conductor,point,screen,security,substrate},
|
||||
file = {/home/jaseg/Sync/Research/Zotero/Salle_EDMONDS_2017_Security wrap with tearable substrate.pdf}
|
||||
}
|
||||
|
||||
@patent{salleStackableSecurityWraps2017,
|
||||
type = {patentus},
|
||||
title = {Stackable Security Wraps},
|
||||
author = {Salle, Vincent Daniel Jean},
|
||||
holder = {{Johnson Electric SA}},
|
||||
date = {2017-08-08},
|
||||
number = {9730314B2},
|
||||
url = {https://patents.google.com/patent/US9730314B2/en?q=(payment+OR+security)&assignee=johnson+electric},
|
||||
urldate = {2025-08-13},
|
||||
langid = {english},
|
||||
keywords = {conductive,screen,security,terminals,wrap},
|
||||
file = {/home/jaseg/Sync/Research/Zotero/Salle_2017_Stackable security wraps.pdf}
|
||||
}
|
||||
|
||||
@article{samiAdvancingTrustworthinessSysteminPackage2024,
|
||||
title = {Advancing {{Trustworthiness}} in {{System-in-Package}}: {{A Novel Root-of-Trust Hardware Security Module}} for {{Heterogeneous Integration}}},
|
||||
shorttitle = {Advancing {{Trustworthiness}} in {{System-in-Package}}},
|
||||
|
|
@ -5400,6 +5551,12 @@
|
|||
file = {/home/jaseg/Sync/Research/Zotero/Sculley et al_Machine Learning.pdf}
|
||||
}
|
||||
|
||||
@online{SecureFlexPaymentTerminal,
|
||||
title = {Secure-{{Flex}}™ for {{Payment Terminal Security}} | {{Johnson Electric}}},
|
||||
url = {https://www.johnsonelectric.com/en/solutions/secure-flex-for-payment-terminal-security},
|
||||
urldate = {2025-08-13}
|
||||
}
|
||||
|
||||
@article{selmkeApplicationTwoPhotonAbsorption2022,
|
||||
title = {On the Application of {{Two-Photon Absorption}} for {{Laser Fault Injection}} Attacks: {{Pushing}} the Physical Boundaries for {{Laser-based Fault Injection}}},
|
||||
shorttitle = {On the Application of {{Two-Photon Absorption}} for {{Laser Fault Injection}} Attacks},
|
||||
|
|
@ -5734,14 +5891,6 @@ Archive 2: https://web.archive.org/web/20250510104017/https://de.linkedin.com/pu
|
|||
file = {/home/jaseg/Sync/Research/Zotero/2021_Sozio et al_Patchable Hardware Security Module (PHaSM) for Extending FPGA Root-of-Trust.pdf;/home/jaseg/Zotero/storage/D5BLNRV7/9707698.html}
|
||||
}
|
||||
|
||||
@standard{SpezifikationFachmodulEPA2023,
|
||||
title = {Spezifikation Fachmodul ePA},
|
||||
date = {2023-04-03},
|
||||
langid = {ngerman},
|
||||
version = {1.53.0},
|
||||
file = {/home/jaseg/Zotero/storage/J79W78KS/Spezifikation Fachmodul ePA.pdf}
|
||||
}
|
||||
|
||||
@article{sproHighVoltageInsulationDesign2021,
|
||||
title = {High-{{Voltage Insulation Design}} of {{Coreless}}, {{Planar PCB Transformers}} for {{Multi-MHz Power Supplies}}},
|
||||
author = {Spro, Ole Christian and Mauseth, Frank and Peftitsis, Dimosthenis},
|
||||
|
|
@ -5864,7 +6013,7 @@ Archive 2: https://web.archive.org/web/20250510104017/https://de.linkedin.com/pu
|
|||
file = {/home/jaseg/Zotero/storage/XURXLX9C/Takeoka et al. - 2014 - Fundamental rate-loss tradeoff for optical quantum.pdf}
|
||||
}
|
||||
|
||||
@incollection{TamperResistance2020a,
|
||||
@incollection{TamperResistance2020,
|
||||
title = {Tamper {{Resistance}}},
|
||||
booktitle = {Security {{Engineering}}},
|
||||
date = {2020},
|
||||
|
|
@ -7162,6 +7311,25 @@ Archive 2: https://web.archive.org/web/20250510104017/https://de.linkedin.com/pu
|
|||
isbn = {978-1-4503-8610-4}
|
||||
}
|
||||
|
||||
@inproceedings{zhouPPMLACHighPerformance2022a,
|
||||
title = {{{PPMLAC}}: High Performance Chipset Architecture for Secure Multi-Party Computation},
|
||||
shorttitle = {{{PPMLAC}}},
|
||||
booktitle = {Proceedings of the 49th {{Annual International Symposium}} on {{Computer Architecture}}},
|
||||
author = {Zhou, Xing and Xu, Zhilei and Wang, Cong and Gao, Mingyu},
|
||||
date = {2022-06-18},
|
||||
pages = {87--101},
|
||||
publisher = {ACM},
|
||||
location = {New York New York},
|
||||
doi = {10.1145/3470496.3527392},
|
||||
url = {https://dl.acm.org/doi/10.1145/3470496.3527392},
|
||||
urldate = {2025-08-13},
|
||||
abstract = {Privacy issue is a main concern restricting data sharing and crossorganization collaborations. While Privacy-Preserving Machine Learning techniques such as Multi-Party Computations (MPC), Homomorphic Encryption, and Federated Learning are proposed to solve this problem, no solution exists with both strong security and high performance to run large-scale, complex machine learning models. This paper presents PPMLAC, a novel chipset architecture to accelerate MPC, which combines MPC’s strong security and hardware’s high performance, eliminates the communication bottleneck from MPC, and achieves several orders of magnitudes speed up over software-based MPC. It is carefully designed to only rely on a minimum set of simple hardware components in the trusted domain, thus is robust against side-channel attacks and malicious adversaries. Our FPGA prototype can run mainstream large-scale ML models like ResNet in near real-time under a practical network environment with non-negligible latency, which is impossible for existing MPC solutions.},
|
||||
eventtitle = {{{ISCA}} '22: {{The}} 49th {{Annual International Symposium}} on {{Computer Architecture}}},
|
||||
isbn = {978-1-4503-8610-4},
|
||||
langid = {english},
|
||||
file = {/home/jaseg/Zotero/storage/N6XAKEXE/Zhou et al. - 2022 - PPMLAC high performance chipset architecture for .pdf}
|
||||
}
|
||||
|
||||
@inproceedings{zhouPrintListenerUncoveringVulnerability2024,
|
||||
title = {{{PrintListener}}: {{Uncovering}} the {{Vulnerability}} of {{Fingerprint Authentication}} via the {{Finger Friction Sound}}},
|
||||
shorttitle = {{{PrintListener}}},
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue