jaseg
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e7a9304cc7
|
Exponential timing working with slight inaccuracies in lower ranges
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2016-12-20 00:04:03 +01:00 |
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jaseg
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a22d51cee2
|
Clocking working
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2016-12-19 23:13:38 +01:00 |
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jaseg
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be17ff0ddf
|
All timings done
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2016-12-19 22:14:56 +01:00 |
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jaseg
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9006665462
|
Basic PWM working
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2016-12-19 21:09:01 +01:00 |
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jaseg
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8e8d860137
|
fnord
|
2016-12-19 02:38:38 +01:00 |
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jaseg
|
b04d8b94aa
|
Add first firmware foo
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2016-12-19 02:32:36 +01:00 |
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↑←↑↓→↓→←↑
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b0d17eb4ae
|
Update .gitignore to include Altium Designer history
|
2016-12-14 21:04:19 +01:00 |
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↑←↑↓→↓→←↑
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94640bdefc
|
WIP, add export
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2016-12-14 20:07:13 +01:00 |
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↑←↑↓→↓→←↑
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90bcfa2087
|
It has become quite a mess
|
2016-11-23 16:19:34 +01:00 |
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↑←↑↓→↓→←↑
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e817a8a4fa
|
Add connectors
|
2016-11-23 13:10:02 +01:00 |
|
↑←↑↓→↓→←↑
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87c874251f
|
layouting along
|
2016-11-21 11:53:33 +01:00 |
|
↑←↑↓→↓→←↑
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225300fd94
|
:octocat: Added .gitattributes & .gitignore files
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2016-11-17 08:45:53 +01:00 |
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