211 lines
6.1 KiB
C
211 lines
6.1 KiB
C
/* Megumin LED display firmware
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* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "global.h"
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#define RTC_INITIALIZED_REGISTER_HIGH BKP->DR1
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#define RTC_INITIALIZED_REGISTER_LOW BKP->DR2
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#define REBOOT_REGISTER BKP->DR3
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#define DAY_SECONDS (24*3600)
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void RTC_IRQHandler(void);
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uint32_t pcg32_random_r() {
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// *Really* minimal PCG32 code / (c) 2014 M.E. O'Neill / pcg-random.org
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// Licensed under Apache License 2.0 (NO WARRANTY, etc. see website)
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static uint64_t state = 0xbc422715d3aef60f;
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static uint64_t inc = 0x6605e3bc6d1a869b;
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uint64_t oldstate = state;
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// Advance internal state
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state = oldstate * 6364136223846793005ULL + (inc|1);
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// Calculate output function (XSH RR), uses old state for max ILP
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uint32_t xorshifted = ((oldstate >> 18u) ^ oldstate) >> 27u;
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uint32_t rot = oldstate >> 59u;
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return (xorshifted >> rot) | (xorshifted << ((-rot) & 31));
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}
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unsigned char dumb_random() {
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static unsigned char x=0x66, a=0x05, b=0xe3, c=0xbc;
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x++; //x is incremented every round and is not affected by any other variable
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a = (a ^ c ^ x); //note the mix of addition and XOR
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b = (b + a); //And the use of very few instructions
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c = (((c + (b >> 1)) ^ a)); // the AES S-Box Operation ensures an even distributon of entropy
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return (c);
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}
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void rtc_write(volatile uint32_t *reg, uint32_t val) {
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while (!(RTC->CRL & RTC_CRL_RTOFF)) ;
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RTC->CRL |= RTC_CRL_CNF;
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reg[0] = val>>16;
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reg[1] = val&0xffff;
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RTC->CRL &= ~RTC_CRL_CNF;
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while (!(RTC->CRL & RTC_CRL_RTOFF)) ;
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}
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void rtc_alarm_reset(void) {
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RTC->CRL &= ~RTC_CRL_ALRF;
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}
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void rtc_init(void) {
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RTC->CRH = RTC_CRH_ALRIE;
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/* Cold boot config */
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if (((RTC_INITIALIZED_REGISTER_HIGH<<16) | RTC_INITIALIZED_REGISTER_LOW) != COMPILE_TIME) {
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/* RTC clock config */
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RCC->BDCR = RCC_BDCR_RTCEN | (1<<RCC_BDCR_RTCSEL_Pos) | RCC_BDCR_LSEON;
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while (!(RCC->BDCR & RCC_BDCR_LSERDY)) ;
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rtc_write(&RTC->PRLH, 32768-1);
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rtc_write(&RTC->CNTH, COMPILE_TIME);
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RTC_INITIALIZED_REGISTER_HIGH = COMPILE_TIME>>16;
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RTC_INITIALIZED_REGISTER_LOW = COMPILE_TIME&0xffff;
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REBOOT_REGISTER = 0;
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}
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/* Synchronize RTC registers from backup domain */
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RTC->CRL &= ~RTC_CRL_RSF;
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}
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void rtc_set_alarm_sec(uint32_t value) {
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rtc_write(&RTC->ALRH, value);
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}
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uint32_t rtc_time(void) {
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/* Wait for register synchronization after bootup */
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while (!(RTC->CRL & RTC_CRL_RSF)) ;
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return RTC->CNTH<<16 | RTC->CNTL;
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}
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void rtc_set_alarm_rel_sec(uint32_t value) {
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rtc_set_alarm_sec(rtc_time() + value);
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}
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int main(void){
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/* We're starting out from HSI@8MHz */
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SystemCoreClockUpdate();
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SCB->SCR &= (~SCB_SCR_SLEEPONEXIT_Msk) & (~SCB_SCR_SLEEPDEEP_Msk); /* Disable for now */
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for (int i=0; i<50000; i++)
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asm volatile ("nop");
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/* Turn on lots of neat things */
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RCC->APB2ENR |= RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPBEN;
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RCC->APB1ENR |= RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN;
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PWR->CR = PWR_CR_DBP;
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GPIOC->CRH |=
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(0<<GPIO_CRH_CNF13_Pos) | (2<<GPIO_CRH_MODE13_Pos); /* PC13 - LED */
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GPIOB->CRH =
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(0<<GPIO_CRH_CNF8_Pos) | (2<<GPIO_CRH_MODE8_Pos); /* PB8 - MOSFET */
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GPIOC->ODR |= 1<<13; /* LED */
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GPIOB->ODR &= ~(1<<8); /* MOSFET */
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rtc_init();
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rtc_alarm_reset();
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NVIC_ClearPendingIRQ(RTC_IRQn);
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//NVIC_EnableIRQ(RTC_IRQn);
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//NVIC_SetPriority(RTC_IRQn, 1);
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rtc_set_alarm_rel_sec(1);
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if (!(PWR->CSR & PWR_CSR_WUF)) /* This reset wasn't caused by the RTC alarm */
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REBOOT_REGISTER++;
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SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
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//SCB->SCR &= (~SCB_SCR_SLEEPONEXIT_Msk) & (~SCB_SCR_SLEEPDEEP_Msk);
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//PWR->CR &= (~PWR_CR_PDDS) & (~PWR_CR_LPDS);
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while (42) {
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RTC_IRQHandler();
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PWR->CR |= PWR_CR_CWUF; /* This has 2 cycles latency, thus the NOPs */
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("wfe");
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}
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//while (42)
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// asm volatile ("wfi");
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}
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void RTC_IRQHandler(void) {
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rtc_alarm_reset();
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rtc_set_alarm_rel_sec(1);
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uint32_t now = rtc_time();
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bool switch_on = false;
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if (REBOOT_REGISTER > 1) { /* We have rebooted since initial bring-up */
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/* Give status indication and active output as fail-safe */
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if ((now&3) == 0) {
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GPIOC->ODR &= ~(1<<13);
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for (int i=0; i<5000; i++)
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asm volatile ("nop");
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GPIOC->ODR |= 1<<13;
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}
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switch_on = true;
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} else {
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switch_on = (now >= TARGET_DATE - (DAY_SECONDS*24) && now < TARGET_DATE);
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}
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if (switch_on && (now/2) % 3 == 0) {
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GPIOB->ODR |= 1<<8;
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/* Go to sleep mode to keep GPIO active */
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PWR->CR &= ~PWR_CR_PDDS;
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SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); /* Use deep sleep mode */
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} else {
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GPIOB->ODR &= ~(1<<8);
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/* Go to standby mode to reduce power consumption */
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PWR->CR = PWR_CR_PDDS;
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Use deep sleep mode */
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}
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GPIOC->ODR &= ~(1<<13);
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for (int i=0; i<5000; i++)
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asm volatile ("nop");
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GPIOC->ODR |= 1<<13;
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}
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void gdb_dump(void) {
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/* debugger hook */
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}
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void NMI_Handler(void) {
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asm volatile ("bkpt");
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}
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void HardFault_Handler(void) __attribute__((naked));
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void HardFault_Handler() {
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asm volatile ("bkpt");
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}
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void SVC_Handler(void) {
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asm volatile ("bkpt");
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}
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void PendSV_Handler(void) {
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asm volatile ("bkpt");
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}
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void SysTick_Handler(void) {
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asm volatile ("bkpt");
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}
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