8 commits

Author	SHA1	Message	Date
jaseg	9a02d3530f	Finish silk layout	2026-01-08 01:12:47 +01:00
jaseg	ff01a6430c	Add wiring cutouts	2026-01-07 21:03:49 +01:00
jaseg	f237068850	Prettify routing	2026-01-07 20:57:58 +01:00
jaseg	1c91e36075	Layout routing topology done	2026-01-07 20:38:31 +01:00
jaseg	92827fe03d	Layout WIP	2026-01-07 18:52:01 +01:00
jaseg	5794ff93d1	Layout WIP	2026-01-07 01:38:55 +01:00
jaseg	777ff87260	Layout WIP	2026-01-06 14:49:58 +01:00
jaseg	8e892d0ba7	Add PCB design	2026-01-05 17:02:52 +01:00