146 lines
4 KiB
C
146 lines
4 KiB
C
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wstrict-aliasing"
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#include <stm32f1xx.h>
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#pragma GCC diagnostic pop
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#include <system_stm32f1xx.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <8b10b.h>
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/* Part number: STM32F030F4C6 */
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static volatile unsigned int sys_time;
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uint32_t get_tick() {
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return SysTick->VAL;
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}
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static volatile struct {
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int current_symbol, next_symbol;
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struct state_8b10b_enc st;
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} txstate;
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#define NO_SYMBOL (DECODER_RETURN_CODE_LAST + 1)
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int main(void) {
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/* External crystal: 8MHz */
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR&RCC_CR_HSERDY));
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/* Sysclk = HCLK = 48MHz */
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RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_PLLMULL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE1_Msk & ~RCC_CFGR_PPRE2_Msk &
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~RCC_CFGR_HPRE_Msk))
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| (10<<RCC_CFGR_PLLMULL_Pos) | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | (4<<RCC_CFGR_PPRE1_Pos) |
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(4<<RCC_CFGR_PPRE2_Pos);
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR&RCC_CR_PLLRDY));
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/* Switch to PLL */
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RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
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//RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_PPRE1_Msk & ~RCC_CFGR_PPRE2_Msk))
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// | (4<<RCC_CFGR_PPRE1_Pos) | (4<<RCC_CFGR_PPRE2_Pos);
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SystemCoreClockUpdate();
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_TIM1EN;
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GPIOA->CRH =
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(2<<GPIO_CRH_CNF8_Pos) | (1<<GPIO_CRH_MODE8_Pos); /* PA8 - low side */
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GPIOB->CRH =
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(2<<GPIO_CRH_CNF13_Pos) | (1<<GPIO_CRH_MODE13_Pos); /* PB13 - high side */
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GPIOC->CRH =
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(0<<GPIO_CRH_CNF13_Pos) | (1<<GPIO_CRH_MODE13_Pos); /* PC13 - LED */
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/* TIM1 running off 24MHz APB2 clk, T=41.667ns */
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TIM1->CR1 = 0; /* Disable ARR preload (double-buffering) */
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TIM1->PSC = 24-1; /* Prescaler 24 -> f=1MHz/T=1us */
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TIM1->DIER = TIM_DIER_UIE; /* Enable update (overflow) interrupt */
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TIM1->CCMR1 = 6<<TIM_CCMR1_OC1M_Pos | TIM_CCMR1_OC1PE; /* Configure output compare unit 1 to PWM mode 1, enable CCR1
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preload */
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TIM1->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1E; /* Confiugre CH1 to complementary outputs */
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TIM1->BDTR = TIM_BDTR_MOE | (0xc0 | (63-32))<<TIM_BDTR_DTG_Pos; /* Enable MOE on next update event, i.e. on initial timer load.
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Set dead-time to 100us. */
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TIM1->CR1 |= TIM_CR1_CEN;
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TIM1->ARR = 1000-1; /* Set f=1.0kHz/T=1.0ms */
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xfr_8b10b_encode_reset(&txstate.st);
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txstate.current_symbol = txstate.next_symbol = xfr_8b10b_encode(&txstate.st, K28_1) | 1<<10;
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TIM1->EGR |= TIM_EGR_UG;
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NVIC_EnableIRQ(TIM1_UP_IRQn);
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NVIC_SetPriority(TIM1_UP_IRQn, 3<<4);
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uint8_t txbuf[128];
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int txpos = -1;
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/* FIXME test code */
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for (int i=0; i<sizeof(txbuf); i++)
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txbuf[i] = i;
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/* FIXME end test code */
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while (42) {
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if (txstate.next_symbol == -NO_SYMBOL) {
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if (txpos == -1)
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txstate.next_symbol = xfr_8b10b_encode(&txstate.st, K28_1);
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else
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txstate.next_symbol = xfr_8b10b_encode(&txstate.st, txbuf[txpos]);
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txpos++;
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if (txpos == sizeof(txbuf))
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txpos = -1;
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}
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}
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}
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void TIM1_UP_IRQHandler() {
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TIM1->SR &= ~TIM_SR_UIF;
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int sym = txstate.current_symbol;
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int bit = sym&1;
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sym >>= 1;
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if (sym == 1) { /* last bit shifted out */
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sym = txstate.next_symbol | 1<<10;
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txstate.next_symbol = -NO_SYMBOL;
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}
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txstate.current_symbol = sym;
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TIM1->CCR1 = bit ? 0xffff : 0x0000;
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}
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void NMI_Handler(void) {
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}
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void HardFault_Handler(void) __attribute__((naked));
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void HardFault_Handler() {
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asm volatile ("bkpt");
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}
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void SVC_Handler(void) {
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}
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void PendSV_Handler(void) {
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}
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void SysTick_Handler(void) {
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sys_time++;
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}
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void _init(void) {
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}
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void MemManage_Handler(void) __attribute__((naked));
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void MemManage_Handler() {
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asm volatile ("bkpt");
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}
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void BusFault_Handler(void) __attribute__((naked));
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void BusFault_Handler() {
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asm volatile ("bkpt");
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}
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