248 lines
7.6 KiB
C
248 lines
7.6 KiB
C
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wstrict-aliasing"
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#include <stm32f0xx.h>
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#pragma GCC diagnostic pop
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#include <system_stm32f0xx.h>
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#include <stm32f0xx_ll_spi.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <8b10b.h>
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/* Part number: STM32F030F4C6 */
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static volatile unsigned int sys_time;
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uint32_t get_tick() {
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return SysTick->VAL;
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}
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static volatile struct {
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int current_symbol, next_symbol;
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struct state_8b10b_enc st;
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} txstate;
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#define NO_SYMBOL (DECODER_RETURN_CODE_LAST + 1)
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unsigned char random() {
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static unsigned char x, a, b, c;
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x++; //x is incremented every round and is not affected by any other variable
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a = (a ^ c ^ x); //note the mix of addition and XOR
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b = (b + a); //And the use of very few instructions
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c = ((c + ((b >> 1) ^ a))); // the AES S-Box Operation ensures an even distributon of entropy
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return c;
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}
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enum STATUS_LEDS {
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STATUS_LED_COMM = 1,
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STATUS_LED_ERROR = 2,
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STATUS_LED_LOAD = 4,
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STATUS_LED_OPERATION = 8,
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STATUS_LED_J5_GREEN = 16,
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STATUS_LED_J5_YELLOW = 32,
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STATUS_LED_J4_GREEN = 64,
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STATUS_LED_J4_YELLOW = 128
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};
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static void set_status_leds(uint8_t val) {
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/* Reset strobe. Will be set in systick handler */
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GPIOA->BRR = 1<<4;
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//for (int i=0; i<100; i++)
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// asm volatile ("nop");
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/* Workaround for *nasty* hardware behavior: If SPI data width is configured as 8 bit but DR is written as 16
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* bit, SPI actually sends 16 clock cycles. Thus, we have to make sure the compiler emits a 8-bit write here.
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* Thanks, TI! */
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*((volatile uint8_t *)&(SPI1->DR)) = val ^ 0x0f; /* Invert LEDs connected to VCC instead of GND */
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}
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int main(void) {
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR&RCC_CR_HSERDY));
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RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk;
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RCC->CFGR |= ((6-2)<<RCC_CFGR_PLLMUL_Pos) | RCC_CFGR_PLLSRC_HSE_PREDIV; /* PLL x6 -> 48.0MHz */
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR&RCC_CR_PLLRDY));
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RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
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RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN | RCC_APB1ENR_PWREN | RCC_APB1ENR_I2C1EN;
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RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN| RCC_APB2ENR_DBGMCUEN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_SPI1EN;
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SystemCoreClockUpdate();
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SysTick_Config(SystemCoreClock/100); /* 10ms interval */
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NVIC_EnableIRQ(SysTick_IRQn);
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NVIC_SetPriority(SysTick_IRQn, 3<<5);
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GPIOA->MODER |=
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(3<<GPIO_MODER_MODER0_Pos) /* PA0 - Vboot to ADC */
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| (2<<GPIO_MODER_MODER1_Pos) /* PA1 - RS485 DE */
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| (2<<GPIO_MODER_MODER2_Pos) /* PA2 - RS485 TX */
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| (2<<GPIO_MODER_MODER3_Pos) /* PA3 - RS485 RX */
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| (1<<GPIO_MODER_MODER4_Pos) /* PA4 - Strobe/Vin to ADC. CAUTION: This pin is dual-use */
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| (2<<GPIO_MODER_MODER5_Pos) /* PA5 - SCK */
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| (2<<GPIO_MODER_MODER6_Pos) /* PA6 - CTRL_A to TIM 3 ch 1 */
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| (2<<GPIO_MODER_MODER7_Pos) /* PA7 - MOSI */
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| (2<<GPIO_MODER_MODER9_Pos) /* PA9 - SCL */
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| (2<<GPIO_MODER_MODER10_Pos);/* PA10 - SDA */
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GPIOA->OSPEEDR =
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(3<<GPIO_OSPEEDR_OSPEEDR4_Pos);
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GPIOA->AFR[0] =
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(1<<GPIO_AFRL_AFSEL1_Pos) /* PA1 */
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| (1<<GPIO_AFRL_AFSEL2_Pos) /* PA2 */
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| (1<<GPIO_AFRL_AFSEL3_Pos) /* PA3 */
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| (1<<GPIO_AFRL_AFSEL6_Pos); /* PA6 */
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GPIOA->AFR[1] =
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(4<<GPIO_AFRH_AFSEL9_Pos) /* PA9 */
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| (4<<GPIO_AFRH_AFSEL10_Pos);/* PA10 */
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GPIOA->ODR = 0; /* Set PA4 ODR to 0 */
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GPIOB->MODER |=
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(2<<GPIO_MODER_MODER1_Pos); /* PB1 - CTRL_B to TIM 3 ch 4 */
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GPIOB->AFR[0] = (1<<GPIO_AFRL_AFSEL1_Pos); /* PB1 */
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/* FIXME USART config */
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/* FIXME ADC config */
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/* FIXME I2C config */
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/* SPI config. SPI1 is used to control the shift register controlling the eight status LEDs. */
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SPI1->CR2 = (7<<SPI_CR2_DS_Pos);
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/* Baud rate PCLK/128 -> 375.0kHz */
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SPI1->CR1 =
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SPI_CR1_SSM
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| SPI_CR1_SSI
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| (6<<SPI_CR1_BR_Pos)
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| SPI_CR1_MSTR;
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SPI1->CR1 |= SPI_CR1_SPE;
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/* TIM3 running off 48MHz APB1 clk, T=20.833ns */
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TIM3->CR1 = 0; /* Disable ARR preload (double-buffering) */
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TIM3->PSC = 48-1; /* Prescaler 48 -> f=1MHz/T=1us */
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TIM3->DIER = TIM_DIER_UIE; /* Enable update (overflow) interrupt */
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TIM3->CCMR1 = 6<<TIM_CCMR1_OC1M_Pos | TIM_CCMR1_OC1PE; /* Configure output compare unit 1 to PWM mode 1, enable CCR1
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preload */
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TIM3->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1E; /* Confiugre CH1 to complementary outputs */
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TIM3->BDTR = TIM_BDTR_MOE | (0xc0 | (63-32))<<TIM_BDTR_DTG_Pos; /* Enable MOE on next update event, i.e. on initial timer load.
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Set dead-time to 100us. */
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TIM3->CR1 |= TIM_CR1_CEN;
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TIM3->ARR = 800-1; /* Set f=2.5kHz/T=0.4ms */
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xfr_8b10b_encode_reset(&txstate.st);
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txstate.current_symbol = txstate.next_symbol = xfr_8b10b_encode(&txstate.st, K28_1) | 1<<10;
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TIM3->EGR |= TIM_EGR_UG;
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NVIC_EnableIRQ(TIM3_IRQn);
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NVIC_SetPriority(TIM3_IRQn, 3<<4);
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uint8_t txbuf[3] = {0x01, 0x05, 0x01};
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int txpos = -1;
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/* FIXME test code */
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//for (int i=0; i<sizeof(txbuf)/sizeof(txbuf[0]); i++)
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// txbuf[i] = i;
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/* FIXME end test code */
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int i = 0;
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while (42) {
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if (txstate.next_symbol == -NO_SYMBOL) {
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if (txpos == -1)
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txstate.next_symbol = xfr_8b10b_encode(&txstate.st, -K28_1);
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else
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txstate.next_symbol = xfr_8b10b_encode(&txstate.st, txbuf[txpos]);
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txpos++;
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if (txpos >= sizeof(txbuf)/sizeof(txbuf[0])) {
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txpos = -1;
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i++;
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if (i == 5) {
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//txbuf[2] = random();
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//txbuf[2] <<= 1;
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//if (!txbuf[2] & 0xff)
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// txbuf[2] = 0x01;
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i = 0;
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}
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}
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}
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}
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}
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int flipbits(int in) {
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return
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(in&0x200)>>9 |
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(in&0x100)>>7 |
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(in&0x080)>>5 |
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(in&0x040)>>3 |
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(in&0x020)>>1 |
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(in&0x010)<<1 |
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(in&0x008)<<3 |
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(in&0x004)<<5 |
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(in&0x002)<<7 |
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(in&0x001)<<9;
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}
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void TIM3_IRQHandler() {
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TIM3->SR &= ~TIM_SR_UIF;
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int sym = txstate.current_symbol;
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int bit = sym&1;
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sym >>= 1;
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if (sym == 1) { /* last bit shifted out */
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if (txstate.next_symbol == -NO_SYMBOL) /*FIXME debug code*/
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//asm volatile("bkpt");
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sym = flipbits(txstate.next_symbol) | 1<<10;
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txstate.next_symbol = -NO_SYMBOL;
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}
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txstate.current_symbol = sym;
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TIM3->CCR1 = bit ? 0xffff : 0x0000;
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}
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void NMI_Handler(void) {
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}
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void HardFault_Handler(void) __attribute__((naked));
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void HardFault_Handler() {
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asm volatile ("bkpt");
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}
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void SVC_Handler(void) {
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}
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void PendSV_Handler(void) {
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}
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void SysTick_Handler(void) {
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static int bit = 0;
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bit = !bit;
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sys_time++;
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/* This is a hack. We could use the SPI interrupt here if that didn't fire at the start instead of end of transmission.... -.- */
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if (bit)
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set_status_leds((sys_time & (1<<6)) ? STATUS_LED_OPERATION : 0);
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else
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GPIOA->BSRR = 1<<4;
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}
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void _init(void) {
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}
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void MemManage_Handler(void) __attribute__((naked));
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void MemManage_Handler() {
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asm volatile ("bkpt");
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}
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void BusFault_Handler(void) __attribute__((naked));
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void BusFault_Handler() {
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asm volatile ("bkpt");
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}
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