309 lines
13 KiB
C
309 lines
13 KiB
C
/* Megumin LED display firmware
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* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "adc.h"
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#include <stdbool.h>
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#include <stdlib.h>
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#define DETECTOR_CHANNEL a
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volatile uint16_t adc_buf[ADC_BUFSIZE];
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volatile struct adc_state adc_state = {0};
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#define st adc_state
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volatile struct adc_measurements adc_data;
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static void adc_dma_init(int burstlen, bool enable_interrupt);
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static void adc_timer_init(int psc, int ivl);
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/* Mode that can be used for debugging */
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void adc_configure_scope_mode(uint8_t channel_mask, int sampling_interval_ns) {
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/* The constant SAMPLE_FAST (0) when passed in as sampling_interval_ns is handled specially in that we turn the ADC
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to continuous mode to get the highest possible sampling rate. */
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/* First, disable trigger timer, DMA and ADC in case we're reconfiguring on the fly. */
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TIM1->CR1 &= ~TIM_CR1_CEN;
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ADC1->CR &= ~ADC_CR_ADSTART;
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DMA1_Channel1->CCR &= ~DMA_CCR_EN;
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/* keep track of current mode in global variable */
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st.adc_mode = ADC_SCOPE;
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adc_dma_init(sizeof(adc_buf)/sizeof(adc_buf[0]), true);
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/* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */
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ADC1->CFGR2 = (2<<ADC_CFGR2_CKMODE_Pos); /* Use PCLK/4=12MHz */
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/* Sampling time 13.5 ADC clock cycles -> total conversion time 2.17us*/
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ADC1->SMPR = (2<<ADC_SMPR_SMP_Pos);
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/* Setup DMA and triggering */
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if (sampling_interval_ns == SAMPLE_FAST) /* Continuous trigger */
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ADC1->CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_CONT;
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else /* Trigger from timer 1 Channel 4 */
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ADC1->CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | (2<<ADC_CFGR1_EXTEN_Pos) | (1<<ADC_CFGR1_EXTSEL_Pos);
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ADC1->CHSELR = channel_mask;
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/* Perform self-calibration */
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ADC1->CR |= ADC_CR_ADCAL;
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while (ADC1->CR & ADC_CR_ADCAL)
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;
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/* Enable conversion */
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ADC1->CR |= ADC_CR_ADEN;
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ADC1->CR |= ADC_CR_ADSTART;
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if (sampling_interval_ns == SAMPLE_FAST)
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return; /* We don't need the timer to trigger in continuous mode. */
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/* An ADC conversion takes 1.1667us, so to be sure we don't get data overruns we limit sampling to every 1.5us.
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Since we don't have a spare PLL to generate the ADC sample clock and re-configuring the system clock just for this
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would be overkill we round to 250ns increments. The minimum sampling rate is about 60Hz due to timer resolution. */
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int cycles = sampling_interval_ns > 1500 ? sampling_interval_ns/250 : 6;
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if (cycles > 0xffff)
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cycles = 0xffff;
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adc_timer_init(12/*250ns/tick*/, cycles);
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}
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/* FIXME figure out the proper place to configure this. */
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#define ADC_TIMER_INTERVAL_US 20
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/* Regular operation receiver mode. */
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void adc_configure_monitor_mode(const struct command_if_def *cmd_if) {
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/* First, disable trigger timer, DMA and ADC in case we're reconfiguring on the fly. */
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TIM1->CR1 &= ~TIM_CR1_CEN;
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ADC1->CR &= ~ADC_CR_ADSTART;
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DMA1_Channel1->CCR &= ~DMA_CCR_EN;
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/* keep track of current mode in global variable */
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st.adc_mode = ADC_MONITOR;
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for (int i=0; i<NCH; i++)
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st.adc_aggregate[i] = 0;
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st.mean_aggregator[0] = st.mean_aggregator[1] = st.mean_aggregator[2] = 0;
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st.mean_aggregate_ctr = 0;
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st.det_st.hysteresis_mv = 6000;
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/* base_cycles * the ADC timer interval (20us) must match the driver's AC period. */
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st.det_st.base_interval_cycles = 40; /* 40 * 20us = 800us/1.25kHz */
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st.det_st.sync = 0;
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st.det_st.last_bit = 0;
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st.det_st.committed_len_ctr = st.det_st.len_ctr = 0;
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xfr_8b10b_reset((struct state_8b10b_dec *)&st.det_st.rx8b10b);
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reset_receiver((struct proto_rx_st *)&st.det_st.rx_st, cmd_if);
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adc_dma_init(NCH, true);
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/* Setup DMA and triggering: Trigger from Timer 1 Channel 4 */
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ADC1->CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | (2<<ADC_CFGR1_EXTEN_Pos) | (1<<ADC_CFGR1_EXTSEL_Pos);
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/* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */
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ADC1->CFGR2 = (2<<ADC_CFGR2_CKMODE_Pos); /* Use PCLK/4=12MHz */
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/* Sampling time 13.5 ADC clock cycles -> total conversion time 2.17us*/
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ADC1->SMPR = (2<<ADC_SMPR_SMP_Pos);
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/* Internal VCC and temperature sensor channels */
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ADC1->CHSELR = ADC_CHSELR_CHSEL0 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL16 | ADC_CHSELR_CHSEL17;
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/* Enable internal voltage reference and temperature sensor */
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ADC->CCR = ADC_CCR_TSEN | ADC_CCR_VREFEN;
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/* Perform ADC calibration */
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ADC1->CR |= ADC_CR_ADCAL;
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while (ADC1->CR & ADC_CR_ADCAL)
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;
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/* Enable ADC */
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ADC1->CR |= ADC_CR_ADEN;
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ADC1->CR |= ADC_CR_ADSTART;
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/* Initialize the timer. Set the divider to get a nice round microsecond tick. The interval must be long enough to
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* comfortably fit all conversions inside. There should be some margin since the ADC runs off its own internal RC
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* oscillator and will drift w.r.t. the system clock. 20us is a nice value when four channels are selected (A, B,
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* T and V).
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*/
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adc_timer_init(SystemCoreClock/1000000/*1.0us/tick*/, 20/* us */);
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}
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static void adc_dma_init(int burstlen, bool enable_interrupt) {
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/* Configure DMA 1 Channel 1 to get rid of all the data */
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DMA1_Channel1->CPAR = (unsigned int)&ADC1->DR;
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DMA1_Channel1->CMAR = (unsigned int)&adc_buf;
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DMA1_Channel1->CNDTR = burstlen;
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DMA1_Channel1->CCR = (0<<DMA_CCR_PL_Pos);
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DMA1_Channel1->CCR |=
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DMA_CCR_CIRC /* circular mode so we can leave it running indefinitely */
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| (1<<DMA_CCR_MSIZE_Pos) /* 16 bit */
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| (1<<DMA_CCR_PSIZE_Pos) /* 16 bit */
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| DMA_CCR_MINC
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| (enable_interrupt ? DMA_CCR_TCIE : 0); /* Enable transfer complete interrupt. */
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if (enable_interrupt) {
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/* triggered on transfer completion. We use this to process the ADC data */
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NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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NVIC_SetPriority(DMA1_Channel1_IRQn, 2<<5);
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} else {
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NVIC_DisableIRQ(DMA1_Channel1_IRQn);
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DMA1->IFCR |= DMA_IFCR_CGIF1;
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}
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DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */
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}
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static void adc_timer_init(int psc, int ivl) {
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TIM1->BDTR = TIM_BDTR_MOE; /* MOE is needed even though we only "output" a chip-internal signal TODO: Verify this. */
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TIM1->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */
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TIM1->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */
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TIM1->CCR4 = 1; /* Trigger at start of timer cycle */
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/* Set prescaler and interval */
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TIM1->PSC = psc-1;
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TIM1->ARR = ivl-1;
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/* Preload all values */
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TIM1->EGR |= TIM_EGR_UG;
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TIM1->CR1 = TIM_CR1_ARPE;
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/* And... go! */
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TIM1->CR1 |= TIM_CR1_CEN;
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}
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/* This acts as a no-op that provides a convenient point to set a breakpoint for the debug scope logic */
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static void gdb_dump(void) {
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}
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/* Called on reception of a bit. This feeds the bit to the 8b10b state machine. When the 8b10b state machine recognizes
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* a received symbol, this in turn calls receive_symbol. Since this is called at sampling time roughly halfway into a
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* bit being received, receive_symbol is called roughly half-way through the last bit of the symbol, just before the
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* symbol's end.
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*/
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void receive_bit(struct bit_detector_st *st, int bit) {
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int symbol = xfr_8b10b_feed_bit((struct state_8b10b_dec *)&st->rx8b10b, bit);
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if (symbol == -K28_1)
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st->sync = 1;
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if (symbol == -DECODING_IN_PROGRESS)
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return;
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if (symbol == -DECODING_ERROR)
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st->sync = 0;
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/* Fall through so we also pass the error to receive_symbol */
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GPIOA->BSRR = 1<<9; /* debug */
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receive_symbol(&st->rx_st, symbol);
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GPIOA->BRR = 1<<9; /* debug */
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/* Exceedingly handy piece of debug code: The Debug Scope 2000 (TM) */
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/*
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static int debug_buf_pos = 0;
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if (st->sync) {
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if (debug_buf_pos < NCH) {
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debug_buf_pos = NCH;
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} else {
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adc_buf[debug_buf_pos++] = symbol;
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if (debug_buf_pos >= sizeof(adc_buf)/sizeof(adc_buf[0])) {
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debug_buf_pos = 0;
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st->sync = 0;
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gdb_dump();
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for (int i=0; i<sizeof(adc_buf)/sizeof(adc_buf[0]); i++)
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adc_buf[i] = -255;
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}
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}
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}
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*/
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}
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/* From a series of detected line levels, extract discrete bits. This self-synchronizes to signal transitions. This
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* expects base_interval_cycles to be set correctly. When a bit is detected, this calls receive_bit(st, bit). The call
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* to receive_bit happens at the sampling point about half-way through the bit being received.
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*/
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void bit_detector(struct bit_detector_st *st, int a) {
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int new_bit = st->last_bit;
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int diff = a-5500; /* FIXME extract constants */
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if (diff < - st->hysteresis_mv/2)
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new_bit = 0;
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else if (diff > st->hysteresis_mv/2)
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new_bit = 1;
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else
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blank(); /* Safety, in case we get an unexpected transition */
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st->len_ctr++;
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if (new_bit != st->last_bit) { /* On transition */
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st->last_bit = new_bit;
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st->len_ctr = 0;
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st->committed_len_ctr = st->base_interval_cycles>>1; /* Commit first half of bit */
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} else if (st->len_ctr >= st->committed_len_ctr) {
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/* The line stayed constant for a longer interval than the commited length. Interpret this as a transmitted bit.
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*
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* +-- Master clock edges -->| - - - - |<-- One bit period
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* | | |
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* 1 X X X X X X X X
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* ____/^^^^*^^^^\_______________________________________/^^^^*^^^^^^^^^*^^^^\__________________________________
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* 0 v ^ v ^
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* | | | |
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* | +-------------------------------+ +---------+
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* | | |
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* At this point, commit 1/2 bit (until here). This When we arrive at the committed value, commit next
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* happens in the block above. full bit as we're now right in the middle of the
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* first bit. This happens in the line below.
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*/
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/* Commit second half of this and first half of possible next bit */
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st->committed_len_ctr += st->base_interval_cycles;
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receive_bit(st, st->last_bit);
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}
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}
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void DMA1_Channel1_IRQHandler(void) {
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GPIOA->BSRR = 1<<5;
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/* ISR timing measurement for debugging */
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//int start = SysTick->VAL;
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/* Clear the interrupt flag */
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DMA1->IFCR |= DMA_IFCR_CGIF1;
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if (st.adc_mode == ADC_SCOPE)
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return;
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/* FIXME This code section currently is a mess since I left it as soon as it worked. Re-work this and try to get
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* back all the useful monitoring stuff, in particular temperature. */
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/* This has been copied from the code examples to section 12.9 ADC>"Temperature sensor and internal reference
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* voltage" in the reference manual with the extension that we actually measure the supply voltage instead of
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* hardcoding it. This is not strictly necessary since we're running off a bored little LDO but it's free and
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* the current supply voltage is a nice health value.
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*/
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// FIXME DEBUG adc_data.vcc_mv = (3300 * VREFINT_CAL)/(st.adc_aggregate[VREF_CH]);
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int64_t vcc = 3300;
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/* FIXME debug
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int64_t vcc = adc_data.vcc_mv;
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int64_t read = st.adc_aggregate[TEMP_CH] * 10 * 10000;
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int64_t cal = TS_CAL1 * 10 * 10000;
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adc_data.temp_celsius_tenths = 300 + ((read/4096 * vcc) - (cal/4096 * 3300))/43000;
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*/
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/* Calculate the line voltage from the measured ADC voltage and the used resistive divider ratio */
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const long vmeas_r_total = VMEAS_R_HIGH + VMEAS_R_LOW;
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//int a = adc_data.vmeas_a_mv = (st.adc_aggregate[VMEAS_A]*(vmeas_r_total * vcc / VMEAS_R_LOW)) >> 12;
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int a = adc_data.vmeas_a_mv = (adc_buf[VMEAS_A]*13300) >> 12;
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bit_detector((struct bit_detector_st *)&st.det_st, a);
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/* ISR timing measurement for debugging */
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/*
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int end = SysTick->VAL;
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int tdiff = start - end;
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if (tdiff < 0)
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tdiff += SysTick->LOAD;
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st.dma_isr_duration = tdiff;
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*/
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GPIOA->BRR = 1<<5;
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}
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