103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
/* Megumin LED display firmware
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* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "global.h"
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volatile unsigned int sys_time = 0;
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volatile unsigned int sys_time_seconds = 0;
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int main(void) {
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR&RCC_CR_HSERDY));
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RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk;
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RCC->CFGR |= (2<<RCC_CFGR_PLLMUL_Pos) | RCC_CFGR_PLLSRC_HSE_PREDIV; /* PLL x4 -> 32.0MHz */
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RCC->CFGR2 &= ~RCC_CFGR2_PREDIV_Msk;
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RCC->CFGR2 |= RCC_CFGR2_PREDIV_DIV2; /* prediv :2 -> 4.0MHz */
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR&RCC_CR_PLLRDY));
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RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
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SystemCoreClockUpdate();
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/* Turn on lots of neat things */
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_FLITFEN;
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RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_DBGMCUEN | RCC_APB2ENR_TIM1EN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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GPIOA->MODER |=
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(3<<GPIO_MODER_MODER0_Pos) /* PA0 - Vmeas_A */
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| (3<<GPIO_MODER_MODER1_Pos) /* PA1 - Vmeas_B */
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| (1<<GPIO_MODER_MODER2_Pos) /* PA2 - LOAD */
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| (1<<GPIO_MODER_MODER3_Pos) /* PA3 - CH0 */
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| (1<<GPIO_MODER_MODER4_Pos) /* PA4 - CH3 */
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| (0<<GPIO_MODER_MODER5_Pos) /* PA5 - TP1 */
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| (1<<GPIO_MODER_MODER6_Pos) /* PA6 - CH2 */
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| (1<<GPIO_MODER_MODER7_Pos) /* PA7 - CH1 */
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| (0<<GPIO_MODER_MODER9_Pos) /* PA9 - TP2 */
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| (0<<GPIO_MODER_MODER10_Pos);/* PA10 - TP3 */
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/* Set shift register IO GPIO output speed */
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GPIOA->OSPEEDR |=
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(2<<GPIO_OSPEEDR_OSPEEDR2_Pos) /* LOAD */
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| (2<<GPIO_OSPEEDR_OSPEEDR3_Pos) /* CH0 */
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| (2<<GPIO_OSPEEDR_OSPEEDR4_Pos) /* CH3 */
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| (2<<GPIO_OSPEEDR_OSPEEDR6_Pos) /* CH2 */
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| (2<<GPIO_OSPEEDR_OSPEEDR7_Pos); /* CH1 */
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SysTick_Config(SystemCoreClock/1000); /* 1ms interval */
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void set_outputs(uint8_t val) {
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int a=!!(val&1), b=!!(val&2), c=!!(val&4), d=!!(val&8);
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GPIOA->ODR &= ~(!a<<3 | !b<<7 | c<<6 | d<<4);
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GPIOA->ODR |= a<<3 | b<<7 | !c<<6 | !d<<4;
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}
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while (42) {
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#define FOO 500000
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for (int i=0; i<FOO; i++) ;
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set_outputs(0x1);
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for (int i=0; i<FOO; i++) ;
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set_outputs(0x2);
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for (int i=0; i<FOO; i++) ;
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set_outputs(0x4);
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for (int i=0; i<FOO; i++) ;
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set_outputs(0x8);
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}
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}
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void NMI_Handler(void) {
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}
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void HardFault_Handler(void) __attribute__((naked));
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void HardFault_Handler() {
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asm volatile ("bkpt");
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}
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void SVC_Handler(void) {
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}
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void PendSV_Handler(void) {
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}
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void SysTick_Handler(void) {
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static int n = 0;
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sys_time++;
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if (n++ == 1000) {
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n = 0;
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sys_time_seconds++;
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}
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}
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