236 lines
6.9 KiB
C
236 lines
6.9 KiB
C
// Inter-integrated circuit (I2C) management
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#include "i2c.h"
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// I2C timeout, about 2ms
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#define I2C_TIMEOUT 200U
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// Maximum NBYTES value
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#define I2C_NBYTES_MAX 255U
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// Count rough delay for timeouts
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static uint32_t i2c_calc_delay(uint32_t delay) {
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uint32_t cnt;
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if (SystemCoreClock > 1000000U) {
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cnt = (delay * ((SystemCoreClock / 1000000U) + 1U));
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} else {
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cnt = (((delay / 100U) + 1U) * ((SystemCoreClock / 10000U) + 1U));
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}
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return cnt;
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}
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// Check if target device is ready for communication
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// input:
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// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
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// devAddr - target device address
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// trials - number of trials (must not be zero)
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// return:
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// I2C_ERROR if there was a timeout during I2C operations, I2C_SUCCESS otherwise
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I2CSTATUS i2c_is_device_ready(I2C_TypeDef* I2Cx, uint8_t devAddr, uint32_t trials) {
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volatile uint32_t wait;
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uint32_t delay_val = i2c_calc_delay(I2C_TIMEOUT);
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uint32_t reg;
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while (trials--) {
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// Clear all flags
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I2Cx->ICR = I2C_ICR_ALL;
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// Generate START
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i2c_genstart(I2Cx, devAddr);
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// Wait for STOP, NACK or BERR
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wait = delay_val;
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while (!((reg = I2Cx->ISR) & (I2C_ISR_STOPF | I2C_ISR_NACKF | I2C_ISR_BERR)) && --wait);
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if (wait == 0) { return I2C_ERROR; }
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// Wait while STOP flag is reset
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wait = delay_val;
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while (!(I2Cx->ISR & I2C_ISR_STOPF) && --wait);
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if (wait == 0) { return I2C_ERROR; }
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// Clear the NACK, STOP and BERR flags
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I2Cx->ICR = I2C_ICR_STOPCF | I2C_ICR_NACKCF | I2C_ICR_BERRCF;
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// Check for BERR flag
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if (reg & I2C_ISR_BERR) {
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// Misplaced START/STOP? Perform a software reset of I2C
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i2c_disable(I2Cx);
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i2c_enable(I2Cx);
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} else {
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// Device responded if NACK flag is not set
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if (!(reg & I2C_ISR_NACKF)) { return I2C_SUCCESS; }
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}
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}
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return I2C_ERROR;
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}
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// Transmit an amount of data in master mode
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// input:
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// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
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// pBbuf - pointer to the data buffer
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// nbytes - number of bytes to transmit
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// devAddr - address of target device
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// flags - options for transmission, combination of I2C_TX_xx values:
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// I2C_TX_NOSTART - don't generate START condition
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// I2C_TX_NOSTOP - don't generate STOP condition
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// I2C_TX_CONT - this flag indicates that transmission will be continued
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// e.g. by calling this function again with NOSTART flag
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// zero value - generate both START and STOP conditions
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// return:
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// I2C_ERROR if there was a timeout during I2C operations, I2C_SUCCESS otherwise
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I2CSTATUS i2c_transmit(I2C_TypeDef* I2Cx, const uint8_t *pBuf, uint32_t nbytes, uint8_t devAddr, uint32_t flags) {
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uint32_t reg;
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uint32_t tx_count;
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uint32_t delay_val = i2c_calc_delay(I2C_TIMEOUT);
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volatile uint32_t wait;
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// Clear all flags
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I2Cx->ICR = I2C_ICR_ALL;
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// Everything regarding to the transmission is in the CR2 register
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reg = I2Cx->CR2;
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reg &= ~I2C_CR2_ALL;
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// Slave device address
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reg |= (devAddr & I2C_CR2_SADD);
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// Whether it need to generate START condition
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if (!(flags & I2C_TX_NOSTART)) { reg |= I2C_CR2_START; }
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// Whether it need to generate STOP condition
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if ((flags & I2C_TX_CONT) || (nbytes > I2C_NBYTES_MAX)) {
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reg |= I2C_CR2_RELOAD;
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} else {
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if (!(flags & I2C_TX_NOSTOP)) { reg |= I2C_CR2_AUTOEND; }
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}
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// Transfer length
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tx_count = (nbytes > I2C_NBYTES_MAX) ? I2C_NBYTES_MAX : nbytes;
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nbytes -= tx_count;
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reg |= tx_count << I2C_CR2_NBYTES_Pos;
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// Write a composed value to the I2C register
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I2Cx->CR2 = reg;
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// Transmit data
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while (tx_count) {
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// Wait until either TXIS or NACK flag is set
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wait = delay_val;
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while (!((reg = I2Cx->ISR) & (I2C_ISR_TXIS | I2C_ISR_NACKF)) && --wait);
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if ((reg & I2C_ISR_NACKF) || (wait == 0)) { return I2C_ERROR; }
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// Transmit byte
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I2Cx->TXDR = *pBuf++;
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tx_count--;
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if ((tx_count == 0) && (nbytes != 0)) {
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// Wait until TCR flag is set (Transfer Complete Reload)
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wait = delay_val;
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while (!(I2Cx->ISR & I2C_ISR_TCR) && --wait);
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if (wait == 0) { return I2C_ERROR; }
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// Configure next (or last) portion transfer
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reg = I2Cx->CR2;
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reg &= ~(I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND);
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if ((flags & I2C_TX_CONT) || (nbytes > I2C_NBYTES_MAX)) {
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reg |= I2C_CR2_RELOAD;
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} else {
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if (!(flags & I2C_TX_NOSTOP)) { reg |= I2C_CR2_AUTOEND; }
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}
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tx_count = (nbytes > I2C_NBYTES_MAX) ? I2C_NBYTES_MAX : nbytes;
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nbytes -= tx_count;
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reg |= tx_count << I2C_CR2_NBYTES_Pos;
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I2Cx->CR2 = reg;
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}
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}
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// End of transmission
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wait = delay_val;
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while (!(I2Cx->ISR & (I2C_ISR_TC | I2C_ISR_TCR | I2C_ISR_STOPF)) && --wait);
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return (wait) ? I2C_SUCCESS : I2C_ERROR;
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}
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// Receive an amount of data in master mode
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// input:
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// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
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// buf - pointer to the data buffer
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// nbytes - number of bytes to receive
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// devAddr - address of target device
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// return:
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// I2C_ERROR if there was a timeout during I2C operations, I2C_SUCCESS otherwise
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I2CSTATUS i2c_receive(I2C_TypeDef* I2Cx, uint8_t *pBuf, uint32_t nbytes, uint8_t devAddr) {
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uint32_t reg;
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uint32_t rx_count;
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uint32_t delay_val = i2c_calc_delay(I2C_TIMEOUT);
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volatile uint32_t wait;
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// Clear all flags
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I2Cx->ICR = I2C_ICR_ALL;
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// Everything regarding to the transmission is in the CR2 register
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reg = I2Cx->CR2;
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reg &= ~I2C_CR2_ALL;
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// Configure slave device address, enable START condition and set direction to READ
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reg |= (devAddr & I2C_CR2_SADD) | I2C_CR2_START | I2C_CR2_RD_WRN;
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// Transfer length
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if (nbytes > I2C_NBYTES_MAX) {
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rx_count = I2C_NBYTES_MAX;
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reg |= I2C_CR2_RELOAD;
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} else {
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rx_count = nbytes;
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reg |= I2C_CR2_AUTOEND;
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}
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reg |= rx_count << I2C_CR2_NBYTES_Pos;
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nbytes -= rx_count;
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// Write a composed value to the I2C register
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I2Cx->CR2 = reg;
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// Receive data
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while (rx_count) {
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// Wait until either RXNE or NACK flag is set
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wait = delay_val;
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while (!((reg = I2Cx->ISR) & (I2C_ISR_RXNE | I2C_ISR_NACKF)) && --wait);
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if ((reg & I2C_ISR_NACKF) || (wait == 0)) { return I2C_ERROR; }
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// Read received data
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*pBuf++ = I2Cx->RXDR;
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rx_count--;
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if ((rx_count == 0) && (nbytes != 0)) {
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// Wait until TCR flag is set (Transfer Complete Reload)
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wait = delay_val;
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while (!(I2Cx->ISR & I2C_ISR_TCR) && --wait);
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if (wait == 0) { return I2C_ERROR; }
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// Configure next (or last) portion transfer
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reg = I2Cx->CR2;
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reg &= ~(I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_RELOAD);
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if (nbytes > I2C_NBYTES_MAX) {
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rx_count = I2C_NBYTES_MAX;
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reg |= I2C_CR2_RELOAD;
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} else {
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rx_count = nbytes;
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reg |= I2C_CR2_AUTOEND;
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}
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reg |= rx_count << I2C_CR2_NBYTES_Pos;
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nbytes -= rx_count;
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I2Cx->CR2 = reg;
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}
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}
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// Wait for the STOP flag
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wait = delay_val;
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while (!(I2Cx->ISR & I2C_ISR_STOPF) && --wait);
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return (wait) ? I2C_SUCCESS : I2C_ERROR;
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}
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