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new driver blinkenlights

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This commit is contained in:
jaseg 2023-08-27 22:31:09 +02:00
parent 7c2cb09fad
commit ec28fcd9f9
94 changed files with 230899 additions and 129328 deletions
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51902
center-control/center.kicad_pcb
View file

File diff suppressed because it is too large Load diff

4
center-control/center.kicad_prl
View file

@ -2,7 +2,7 @@
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"auto_track_width": false,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
@ -65,7 +65,7 @@
36,
39
],
"visible_layers": "ffcffff_ffffffff",
"visible_layers": "ffeffff_ffffffff",
"zone_display_mode": 0
},
"meta": {

21
center-control/center.kicad_pro
View file

@ -57,10 +57,12 @@
}
],
"drc_exclusions": [
"clearance|180095001|115440000|46b665bc-ec0c-494f-bc83-df770871abd3|bcb40fa3-b41b-411d-b561-9bd80d99e072",
"clearance|180850000|115440000|bcb40fa3-b41b-411d-b561-9bd80d99e072|46b665bc-ec0c-494f-bc83-df770871abd3",
"courtyards_overlap|195765866|108222151|00000000-0000-0000-0000-00005de7bda7|00000000-0000-0000-0000-00005de9b522",
"text_thickness|193350000|117925000|e1e8791b-f102-4509-9948-1986c49e1265|00000000-0000-0000-0000-000000000000"
"courtyards_overlap|196360001|102626502|00000000-0000-0000-0000-00005de9b522|99d59f94-0300-4758-95c1-fe9bbbbfa783",
"courtyards_overlap|197763171|110797068|00000000-0000-0000-0000-00005de9b522|c4833d2e-2c9e-4440-8866-6140984cca80",
"text_thickness|152631995|101175000|00000000-0000-0000-0000-00005de93595|00000000-0000-0000-0000-000000000000",
"text_thickness|156049472|101175000|00000000-0000-0000-0000-00005de935c0|00000000-0000-0000-0000-000000000000",
"text_thickness|178000000|68444662|e1e8791b-f102-4509-9948-1986c49e1265|00000000-0000-0000-0000-000000000000",
"unresolved_variable|206814520|80002996|002cb8c7-b00a-4e5f-a820-e69219752984|00000000-0000-0000-0000-000000000000"
],
"meta": {
"filename": "board_design_settings.json",
@ -100,16 +102,16 @@
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "ignore",
"silk_over_copper": "error",
"silk_over_copper": "ignore",
"silk_overlap": "ignore",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"solder_mask_bridge": "ignore",
"starved_thermal": "ignore",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_dangling": "ignore",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
@ -534,8 +536,11 @@
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""

99
center-control/center.kicad_sch
View file

@ -1763,6 +1763,8 @@
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@ -3149,17 +3147,17 @@
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(effects (font (size 1.27 1.27)) (justify right) hide)
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@ -3297,6 +3304,9 @@
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@ -3518,7 +3528,7 @@
(property "Value" "0" (at 71.12 189.23 90)
(effects (font (size 1.27 1.27)))
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(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder" (at 68.58 191.77 0)
(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder" (at 68.58 191.77 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (at 68.58 191.77 0)
@ -3681,16 +3691,16 @@
)
)
(symbol (lib_id "center-rescue:R-Device") (at 198.12 101.6 270) (unit 1)
(symbol (lib_id "center-rescue:R-Device") (at 198.12 101.6 270) (mirror x) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid 00000000-0000-0000-0000-00005deb5134)
(property "Reference" "R4" (at 198.12 96.3422 90)
(property "Reference" "R4" (at 198.12 106.8578 90)
(effects (font (size 1.27 1.27)))
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(property "Value" "30mR 1/4W" (at 198.12 98.6536 90)
(property "Value" "30mR 1/4W" (at 198.12 104.5464 90)
(effects (font (size 1.27 1.27)))
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(property "Footprint" "Resistor_SMD:R_1210_3225Metric" (at 198.12 99.822 90)
(property "Footprint" "Resistor_SMD:R_1210_3225Metric" (at 198.12 103.378 90)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (at 198.12 101.6 0)
@ -3756,13 +3766,7 @@
(property "Datasheet" "~" (at 254 95.25 0)
(effects (font (size 1.27 1.27)) hide)
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(property "Mfg" "Eaton" (at 254 95.25 0)
(effects (font (size 1.27 1.27)) hide)
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(property "PN" "DR127-470" (at 254 95.25 0)
(effects (font (size 1.27 1.27)) hide)
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(property "Reichelt" "EATON DR127-470" (at 254 95.25 0)
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(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid edfc54e1-8ddf-43a9-beea-f0293e91e992))
@ -3839,7 +3843,7 @@
(property "Value" "300k" (at 281.178 101.473 0)
(effects (font (size 1.27 1.27)) (justify left))
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(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder" (at 277.622 100.33 90)
(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder" (at 277.622 100.33 90)
(effects (font (size 1.27 1.27)) hide)
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(property "Datasheet" "~" (at 279.4 100.33 0)
@ -3865,7 +3869,7 @@
(property "Value" "20k" (at 281.178 114.173 0)
(effects (font (size 1.27 1.27)) (justify left))
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(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder" (at 277.622 113.03 90)
(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder" (at 277.622 113.03 90)
(effects (font (size 1.27 1.27)) hide)
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(property "Datasheet" "~" (at 279.4 113.03 0)
@ -3942,7 +3946,7 @@
(property "Value" "4k7" (at 275.8186 222.123 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder" (at 274.32 220.98 0)
(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder" (at 274.32 220.98 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (at 274.32 220.98 0)
@ -3975,13 +3979,13 @@
(effects (font (size 1.27 1.27)) hide)
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(property "Mfg" "Rubycon" (at 181.61 115.57 90)
(effects (font (size 1.27 1.27)) (justify left))
(effects (font (size 1.27 1.27)) (justify left) hide)
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(property "LCSC" "C324050" (at 176.53 104.14 0)
(effects (font (size 1.27 1.27)) hide)
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(property "PN" "63YXF220MFFCT810X20" (at 184.15 115.57 90)
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@ -4009,6 +4013,9 @@
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(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder" (at 233.68 94.742 90)
(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder" (at 233.68 94.742 90)
(effects (font (size 1.27 1.27)) hide)
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@ -4131,7 +4141,7 @@
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(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder" (at 207.01 220.98 0)
(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder" (at 207.01 220.98 0)
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@ -4232,7 +4242,7 @@
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(property "Footprint" "Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder" (at 207.01 177.8 0)
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@ -4258,7 +4268,7 @@
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@ -4534,6 +4544,9 @@
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86585
center-control/fp-info-cache
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File diff suppressed because it is too large Load diff

8151
center-led/center.kicad_pcb
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3454
corner/corner.kicad_pcb
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627
corner/gerber/corner-B.Cu.gbr
View file

@ -1,627 +0,0 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.0.1)*
G04 #@! TF.CreationDate,2018-11-27T11:01:09+09:00*
G04 #@! TF.ProjectId,corner,636F726E65722E6B696361645F706362,rev?*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Copper,L2,Bot,Signal*
G04 #@! TF.FilePolarity,Positive*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.0.1)) date Tue Nov 27 11:01:09 2018*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 #@! TA.AperFunction,SMDPad,CuDef*
%ADD10C,2.800000*%
G04 #@! TD*
G04 #@! TA.AperFunction,Conductor*
%ADD11C,2.800000*%
G04 #@! TD*
G04 #@! TA.AperFunction,SMDPad,CuDef*
%ADD12O,5.000000X2.800000*%
G04 #@! TD*
G04 #@! TA.AperFunction,SMDPad,CuDef*
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G04 #@! TD*
G04 #@! TA.AperFunction,ComponentPad*
%ADD14R,3.600000X1.800000*%
G04 #@! TD*
G04 #@! TA.AperFunction,ComponentPad*
%ADD15O,3.600000X1.800000*%
G04 #@! TD*
G04 #@! TA.AperFunction,Conductor*
%ADD16C,0.254000*%
G04 #@! TD*
G04 APERTURE END LIST*
D10*
G04 #@! TO.P,J2,2*
G04 #@! TO.N,/B*
X163253070Y-59829084D03*
D11*
G04 #@! TD*
G04 #@! TO.N,/B*
G04 #@! TO.C,J2*
X163915067Y-60707583D02*
X162591073Y-58950585D01*
D10*
G04 #@! TO.P,J2,1*
G04 #@! TO.N,/A*
X166846930Y-57120916D03*
D11*
G04 #@! TD*
G04 #@! TO.N,/A*
G04 #@! TO.C,J2*
X167508927Y-57999415D02*
X166184933Y-56242417D01*
D12*
G04 #@! TO.P,J1,1*
G04 #@! TO.N,/D*
X174700000Y-42150000D03*
G04 #@! TO.P,J1,2*
G04 #@! TO.N,/A*
X174700000Y-46650000D03*
G04 #@! TD*
D13*
G04 #@! TO.P,J3,1*
G04 #@! TO.N,/C*
X156550000Y-64600000D03*
G04 #@! TO.P,J3,2*
G04 #@! TO.N,/B*
X152050000Y-64600000D03*
G04 #@! TD*
D14*
G04 #@! TO.P,J4,1*
G04 #@! TO.N,/C*
X153000000Y-46000000D03*
D15*
G04 #@! TO.P,J4,2*
G04 #@! TO.N,/A*
X153000000Y-51080000D03*
G04 #@! TD*
D16*
G04 #@! TO.N,/D*
G36*
X185224413Y-35721984D02*
X185224412Y-39383066D01*
X185210013Y-39455454D01*
X185267058Y-39742237D01*
X185429500Y-39985349D01*
X185429507Y-39985359D01*
X185672629Y-40147808D01*
X185959412Y-40204853D01*
X186002934Y-40196196D01*
X186002934Y-43873000D01*
X165256934Y-43873000D01*
X165256934Y-42710000D01*
X169930074Y-42710000D01*
X170000000Y-42723909D01*
X170069925Y-42710000D01*
X170069926Y-42710000D01*
X170277028Y-42668805D01*
X170511881Y-42511881D01*
X170668805Y-42277028D01*
X170723909Y-42000000D01*
X170710000Y-41930074D01*
X170710000Y-39069926D01*
X170723909Y-39000000D01*
X170668805Y-38722972D01*
X170511881Y-38488119D01*
X170277028Y-38331195D01*
X170069926Y-38290000D01*
X170000000Y-38276091D01*
X169930075Y-38290000D01*
X165256934Y-38290000D01*
X165256934Y-35721978D01*
X185224413Y-35721984D01*
X185224413Y-35721984D01*
G37*
X185224413Y-35721984D02*
X185224412Y-39383066D01*
X185210013Y-39455454D01*
X185267058Y-39742237D01*
X185429500Y-39985349D01*
X185429507Y-39985359D01*
X185672629Y-40147808D01*
X185959412Y-40204853D01*
X186002934Y-40196196D01*
X186002934Y-43873000D01*
X165256934Y-43873000D01*
X165256934Y-42710000D01*
X169930074Y-42710000D01*
X170000000Y-42723909D01*
X170069925Y-42710000D01*
X170069926Y-42710000D01*
X170277028Y-42668805D01*
X170511881Y-42511881D01*
X170668805Y-42277028D01*
X170723909Y-42000000D01*
X170710000Y-41930074D01*
X170710000Y-39069926D01*
X170723909Y-39000000D01*
X170668805Y-38722972D01*
X170511881Y-38488119D01*
X170277028Y-38331195D01*
X170069926Y-38290000D01*
X170000000Y-38276091D01*
X169930075Y-38290000D01*
X165256934Y-38290000D01*
X165256934Y-35721978D01*
X185224413Y-35721984D01*
G04 #@! TO.N,/A*
G36*
X164494934Y-35721978D02*
X164494934Y-38483565D01*
X164488119Y-38488119D01*
X164331195Y-38722972D01*
X164276091Y-39000000D01*
X164290000Y-39069926D01*
X164290001Y-41930070D01*
X164276091Y-42000000D01*
X164331195Y-42277028D01*
X164488119Y-42511881D01*
X164494934Y-42516435D01*
X164494934Y-44000000D01*
X164543270Y-44243004D01*
X164680921Y-44449013D01*
X164886930Y-44586664D01*
X165129934Y-44635000D01*
X185873000Y-44635000D01*
X185873000Y-48723145D01*
X185672629Y-48763001D01*
X185429507Y-48925450D01*
X185267058Y-49168572D01*
X185210013Y-49455355D01*
X185224413Y-49527748D01*
X185224412Y-51653088D01*
X174335731Y-62541759D01*
X174316312Y-62551126D01*
X174232855Y-62644635D01*
X174196412Y-62681078D01*
X174184743Y-62698542D01*
X174121611Y-62769278D01*
X174104240Y-62819022D01*
X174074967Y-62862833D01*
X174056471Y-62955821D01*
X174025214Y-63045331D01*
X174028202Y-63097938D01*
X174017923Y-63149615D01*
X174036419Y-63242603D01*
X174041796Y-63337260D01*
X174064688Y-63384718D01*
X174074967Y-63436396D01*
X174127639Y-63515226D01*
X174136766Y-63534147D01*
X174167790Y-63575315D01*
X174195613Y-63616956D01*
X171489588Y-66330583D01*
X171405436Y-66264725D01*
X163296317Y-56103901D01*
X163043004Y-55913336D01*
X162800000Y-55865000D01*
X161135000Y-55865000D01*
X161135000Y-55000000D01*
X161098625Y-54788166D01*
X160971992Y-54575207D01*
X158721992Y-52075207D01*
X158493004Y-51913336D01*
X158250000Y-51865000D01*
X151763026Y-51865000D01*
X151135000Y-51236974D01*
X151135000Y-50763026D01*
X153013026Y-48885000D01*
X156750000Y-48885000D01*
X156993004Y-48836664D01*
X157199013Y-48699013D01*
X158949013Y-46949013D01*
X159086664Y-46743004D01*
X159135000Y-46500000D01*
X159135000Y-35721977D01*
X164494934Y-35721978D01*
X164494934Y-35721978D01*
G37*
X164494934Y-35721978D02*
X164494934Y-38483565D01*
X164488119Y-38488119D01*
X164331195Y-38722972D01*
X164276091Y-39000000D01*
X164290000Y-39069926D01*
X164290001Y-41930070D01*
X164276091Y-42000000D01*
X164331195Y-42277028D01*
X164488119Y-42511881D01*
X164494934Y-42516435D01*
X164494934Y-44000000D01*
X164543270Y-44243004D01*
X164680921Y-44449013D01*
X164886930Y-44586664D01*
X165129934Y-44635000D01*
X185873000Y-44635000D01*
X185873000Y-48723145D01*
X185672629Y-48763001D01*
X185429507Y-48925450D01*
X185267058Y-49168572D01*
X185210013Y-49455355D01*
X185224413Y-49527748D01*
X185224412Y-51653088D01*
X174335731Y-62541759D01*
X174316312Y-62551126D01*
X174232855Y-62644635D01*
X174196412Y-62681078D01*
X174184743Y-62698542D01*
X174121611Y-62769278D01*
X174104240Y-62819022D01*
X174074967Y-62862833D01*
X174056471Y-62955821D01*
X174025214Y-63045331D01*
X174028202Y-63097938D01*
X174017923Y-63149615D01*
X174036419Y-63242603D01*
X174041796Y-63337260D01*
X174064688Y-63384718D01*
X174074967Y-63436396D01*
X174127639Y-63515226D01*
X174136766Y-63534147D01*
X174167790Y-63575315D01*
X174195613Y-63616956D01*
X171489588Y-66330583D01*
X171405436Y-66264725D01*
X163296317Y-56103901D01*
X163043004Y-55913336D01*
X162800000Y-55865000D01*
X161135000Y-55865000D01*
X161135000Y-55000000D01*
X161098625Y-54788166D01*
X160971992Y-54575207D01*
X158721992Y-52075207D01*
X158493004Y-51913336D01*
X158250000Y-51865000D01*
X151763026Y-51865000D01*
X151135000Y-51236974D01*
X151135000Y-50763026D01*
X153013026Y-48885000D01*
X156750000Y-48885000D01*
X156993004Y-48836664D01*
X157199013Y-48699013D01*
X158949013Y-46949013D01*
X159086664Y-46743004D01*
X159135000Y-46500000D01*
X159135000Y-35721977D01*
X164494934Y-35721978D01*
G04 #@! TO.N,/C*
G36*
X158373000Y-35721977D02*
X158373000Y-46447394D01*
X156697394Y-48123000D01*
X152750000Y-48123000D01*
X152701399Y-48132667D01*
X152660197Y-48160197D01*
X150410197Y-50410197D01*
X150382667Y-50451399D01*
X150373000Y-50500000D01*
X150373000Y-51500000D01*
X150382667Y-51548601D01*
X150410197Y-51589803D01*
X150965659Y-52145265D01*
X150993327Y-52186673D01*
X151034735Y-52214341D01*
X151410197Y-52589803D01*
X151451399Y-52617333D01*
X151500000Y-52627000D01*
X158193439Y-52627000D01*
X160373000Y-55048735D01*
X160373000Y-64947394D01*
X157447394Y-67873000D01*
X154627000Y-67873000D01*
X154627000Y-63500000D01*
X154617333Y-63451399D01*
X154589803Y-63410197D01*
X153987125Y-62807519D01*
X153966928Y-62705982D01*
X153517153Y-62032847D01*
X152844018Y-61583072D01*
X152050000Y-61425132D01*
X151255983Y-61583072D01*
X150822076Y-61873000D01*
X145723270Y-61873000D01*
X145723270Y-55000000D01*
X148276091Y-55000000D01*
X148290000Y-55069926D01*
X148290001Y-59930069D01*
X148276091Y-60000000D01*
X148331195Y-60277028D01*
X148488119Y-60511881D01*
X148722972Y-60668805D01*
X148930074Y-60710000D01*
X148930075Y-60710000D01*
X149000000Y-60723909D01*
X149069926Y-60710000D01*
X151930074Y-60710000D01*
X152000000Y-60723909D01*
X152069925Y-60710000D01*
X152069926Y-60710000D01*
X152277028Y-60668805D01*
X152511881Y-60511881D01*
X152668805Y-60277028D01*
X152723909Y-60000000D01*
X152710000Y-59930074D01*
X152710000Y-55069926D01*
X152723909Y-55000000D01*
X152668805Y-54722972D01*
X152511881Y-54488119D01*
X152277028Y-54331195D01*
X152069926Y-54290000D01*
X152000000Y-54276091D01*
X151930075Y-54290000D01*
X149069925Y-54290000D01*
X149000000Y-54276091D01*
X148930074Y-54290000D01*
X148722972Y-54331195D01*
X148488119Y-54488119D01*
X148331195Y-54722972D01*
X148276091Y-55000000D01*
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X153930075Y-44710000D01*
X154000000Y-44723909D01*
X154277028Y-44668805D01*
X154511881Y-44511881D01*
X154668805Y-44277028D01*
X154710000Y-44069926D01*
X154710000Y-44069925D01*
X154723909Y-44000000D01*
X154710000Y-43930074D01*
X154710000Y-39069926D01*
X154723909Y-39000000D01*
X154668805Y-38722972D01*
X154511881Y-38488119D01*
X154277028Y-38331195D01*
X154069926Y-38290000D01*
X154069925Y-38290000D01*
X154000000Y-38276091D01*
X153930074Y-38290000D01*
X149069926Y-38290000D01*
X149000000Y-38276091D01*
X148930075Y-38290000D01*
X148930074Y-38290000D01*
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X148488119Y-38488119D01*
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X145723270Y-39000000D01*
X145723270Y-35721973D01*
X158373000Y-35721977D01*
X158373000Y-35721977D01*
G37*
X158373000Y-35721977D02*
X158373000Y-46447394D01*
X156697394Y-48123000D01*
X152750000Y-48123000D01*
X152701399Y-48132667D01*
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X150965659Y-52145265D01*
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X151034735Y-52214341D01*
X151410197Y-52589803D01*
X151451399Y-52617333D01*
X151500000Y-52627000D01*
X158193439Y-52627000D01*
X160373000Y-55048735D01*
X160373000Y-64947394D01*
X157447394Y-67873000D01*
X154627000Y-67873000D01*
X154627000Y-63500000D01*
X154617333Y-63451399D01*
X154589803Y-63410197D01*
X153987125Y-62807519D01*
X153966928Y-62705982D01*
X153517153Y-62032847D01*
X152844018Y-61583072D01*
X152050000Y-61425132D01*
X151255983Y-61583072D01*
X150822076Y-61873000D01*
X145723270Y-61873000D01*
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X148290001Y-59930069D01*
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X148331195Y-60277028D01*
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X148722972Y-60668805D01*
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X149069926Y-60710000D01*
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X152069925Y-60710000D01*
X152069926Y-60710000D01*
X152277028Y-60668805D01*
X152511881Y-60511881D01*
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X152723909Y-60000000D01*
X152710000Y-59930074D01*
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X152723909Y-55000000D01*
X152668805Y-54722972D01*
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X149000000Y-54276091D01*
X148930074Y-54290000D01*
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X148488119Y-54488119D01*
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X149000000Y-44723909D01*
X149069925Y-44710000D01*
X153930075Y-44710000D01*
X154000000Y-44723909D01*
X154277028Y-44668805D01*
X154511881Y-44511881D01*
X154668805Y-44277028D01*
X154710000Y-44069926D01*
X154710000Y-44069925D01*
X154723909Y-44000000D01*
X154710000Y-43930074D01*
X154710000Y-39069926D01*
X154723909Y-39000000D01*
X154668805Y-38722972D01*
X154511881Y-38488119D01*
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G04 #@! TO.N,/B*
G36*
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X162738869Y-56627000D01*
X170929991Y-66890575D01*
X170929991Y-66890575D01*
G37*
X170929991Y-66890575D02*
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X168077724Y-69707653D01*
X168006990Y-69644529D01*
X167957245Y-69627161D01*
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X167678329Y-69551134D01*
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X167533654Y-69559358D01*
X167439004Y-69564738D01*
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X149986304Y-75671343D01*
X149823855Y-75428221D01*
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537
corner/gerber/corner-F.Cu.gbr
View file

@ -1,537 +0,0 @@
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X148178571Y-57571428D01*
X148178571Y-57785714D01*
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X147607142Y-57285714D02*
X147678571Y-57428571D01*
X147678571Y-57714285D01*
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X147678571Y-56571428D02*
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X147464285Y-55214285D01*
X147607142Y-55142857D01*
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X147678571Y-54857142D01*
D11*
X169157142Y-55714285D02*
X171442857Y-55714285D01*
X170300000Y-56857142D02*
X170300000Y-54571428D01*
X159207142Y-65364285D02*
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X174807142Y-38164285D02*
X177092857Y-38164285D01*
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D10*
X153678571Y-36678571D02*
X154250000Y-36678571D01*
X153892857Y-36178571D02*
X153892857Y-37464285D01*
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X159178571Y-36678571D01*
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X159178571Y-37678571D01*
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X160607142Y-37678571D02*
X160464285Y-37607142D01*
X160392857Y-37535714D01*
X160321428Y-37392857D01*
X160321428Y-36964285D01*
X160392857Y-36821428D01*
X160464285Y-36750000D01*
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X160821428Y-36678571D01*
X160964285Y-36750000D01*
X161035714Y-36821428D01*
X161107142Y-36964285D01*
X161107142Y-37392857D01*
X161035714Y-37535714D01*
X160964285Y-37607142D01*
X160821428Y-37678571D01*
X160607142Y-37678571D01*
X161535714Y-36678571D02*
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X161750000Y-36178571D02*
X161750000Y-37464285D01*
X161821428Y-37607142D01*
X161964285Y-37678571D01*
X162107142Y-37678571D01*
X162392857Y-36678571D02*
X162964285Y-36678571D01*
X162607142Y-36178571D02*
X162607142Y-37464285D01*
X162678571Y-37607142D01*
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X163464285Y-37535714D01*
X163392857Y-37392857D01*
X163392857Y-36964285D01*
X163464285Y-36821428D01*
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X163678571Y-36678571D01*
X163892857Y-36678571D01*
X164035714Y-36750000D01*
X164107142Y-36821428D01*
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X164178571Y-37392857D01*
X164107142Y-37535714D01*
X164035714Y-37607142D01*
X163892857Y-37678571D01*
X163678571Y-37678571D01*
X164821428Y-37678571D02*
X164821428Y-36678571D01*
X164821428Y-36821428D02*
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X165678571Y-36678571D01*
X165892857Y-36678571D01*
X166035714Y-36750000D01*
X166107142Y-36892857D01*
X166107142Y-37678571D01*
D12*
G04 #@! TO.C,J3*
X174700000Y-44900000D02*
X174700000Y-43900000D01*
X196700000Y-40400000D02*
X174700000Y-40400000D01*
X174700000Y-48400000D02*
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X189700000Y-48400000D02*
X189700000Y-40400000D01*
X189700000Y-40400000D02*
X186700000Y-48400000D01*
X186700000Y-48400000D02*
X186700000Y-40400000D01*
X188700000Y-40400000D02*
X186700000Y-45900000D01*
X186700000Y-43400000D02*
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X188700000Y-48400000D02*
X189700000Y-45900000D01*
X187700000Y-48400000D02*
X189700000Y-43400000D01*
D13*
G04 #@! TO.C,J4*
X154280000Y-43380000D02*
X144920000Y-43380000D01*
X144920000Y-43380000D02*
X144920000Y-53700000D01*
X144920000Y-53700000D02*
X154280000Y-53700000D01*
X154280000Y-43380000D02*
X154280000Y-44950000D01*
X154280000Y-53700000D02*
X154280000Y-52130000D01*
X154280000Y-47050000D02*
X154280000Y-50030000D01*
X148200000Y-43380000D02*
X148200000Y-53700000D01*
X155600000Y-46300000D02*
X155000000Y-46000000D01*
X155000000Y-46000000D02*
X155600000Y-45700000D01*
X155600000Y-45700000D02*
X155600000Y-46300000D01*
D12*
G04 #@! TO.C,J2*
X169679053Y-71264522D02*
X174875861Y-69852718D01*
X170280868Y-72063157D02*
X172879272Y-71357255D01*
X173070416Y-67456811D02*
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22
driver/driver.kicad_pcb
View file

@ -278,6 +278,7 @@
(at 83.2 42.35)
(descr "Connector Headers with Friction Lock, 22-27-2021, http://www.molex.com/pdm_docs/sd/022272021_sd.pdf")
(tags "connector molex kk_6410 22-27-2021")
(property "LCSC" "C158012")
(property "Sheetfile" "driver.kicad_sch")
(property "Sheetname" "")
(property "Stock" "yes")
@ -360,7 +361,7 @@
(at 180.5 44.8)
(descr "Shielded, 2 LED, https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJHSE538X.pdf")
(tags "RJ45 8p8c ethernet cat5")
(property "LCSC" "C133529")
(property "LCSC" "C386759")
(property "Mfg" "Ckmtw")
(property "PN" "C133529")
(property "Sheetfile" "driver.kicad_sch")
@ -658,6 +659,7 @@
(at 141.95 77.45 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(property "LCSC" "C29936")
(property "Sheetfile" "driver.kicad_sch")
(property "Sheetname" "")
(property "Stock" "yes")
@ -758,6 +760,7 @@
(at 113.4 54.4 180)
(descr "Connector Headers with Friction Lock, 22-27-2041, http://www.molex.com/pdm_docs/sd/022272021_sd.pdf")
(tags "connector molex kk_6410 22-27-2041")
(property "LCSC" "C144395")
(property "Sheetfile" "driver.kicad_sch")
(property "Sheetname" "")
(property "Stock" "yes")
@ -1015,6 +1018,7 @@
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(property "BOM ignore" "yes")
(property "DNP" "DNP")
(property "Sheetfile" "driver.kicad_sch")
(property "Sheetname" "")
(property "Stock" "")
@ -1042,6 +1046,7 @@
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(property "BOM ignore" "yes")
(property "DNP" "DNP")
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(property "Sheetname" "")
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@ -1069,6 +1074,7 @@
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(tags "mounting hole 3.2mm no annular m3")
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(property "DNP" "DNP")
(property "Sheetfile" "driver.kicad_sch")
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@ -1096,6 +1102,7 @@
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(property "BOM ignore" "yes")
(property "DNP" "DNP")
(property "Sheetfile" "driver.kicad_sch")
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(property "Stock" "")
@ -1222,7 +1229,7 @@
(at 160.65 44.8)
(descr "Shielded, 2 LED, https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJHSE538X.pdf")
(tags "RJ45 8p8c ethernet cat5")
(property "LCSC" "C133529")
(property "LCSC" "C386759")
(property "Mfg" "Ckmtw")
(property "PN" "C133529")
(property "Sheetfile" "driver.kicad_sch")
@ -4657,6 +4664,7 @@
(at 129.25 74.8)
(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
(property "LCSC" "C29936")
(property "Sheetfile" "driver.kicad_sch")
(property "Sheetname" "")
(property "Stock" "yes")
@ -5638,7 +5646,7 @@
(at 121.6 119.6)
(descr "MSOP, 8 Pin (https://www.jedec.org/system/files/docs/mo-187F.pdf variant AA), generated with kicad-footprint-generator ipc_gullwing_generator.py")
(tags "MSOP SO")
(property "LCSC" "C94847")
(property "LCSC" "C2837470")
(property "Mfg" "Microchip")
(property "PN" "MCP9808-E/MS")
(property "Sheetfile" "driver.kicad_sch")
@ -5968,6 +5976,7 @@
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(property "BOM ignore" "yes")
(property "DNP" "DNP")
(property "Sheetfile" "driver.kicad_sch")
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@ -6065,6 +6074,7 @@
(at 161.2 57.4 90)
(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
(property "LCSC" "C29936")
(property "Sheetfile" "driver.kicad_sch")
(property "Sheetname" "")
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@ -6458,6 +6468,7 @@
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(property "BOM ignore" "yes")
(property "DNP" "DNP")
(property "Sheetfile" "driver.kicad_sch")
(property "Sheetname" "")
(property "Stock" "")
@ -7840,6 +7851,7 @@
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(property "BOM ignore" "yes")
(property "DNP" "DNP")
(property "Sheetfile" "driver.kicad_sch")
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@ -7922,6 +7934,7 @@
(at 149.895 60.409491 90)
(descr "https://power.murata.com/pub/data/power/ncl/kdc_mee1.pdf")
(tags "murata dc-dc transformer")
(property "LCSC" "C512041")
(property "Sheetfile" "driver.kicad_sch")
(property "Sheetname" "")
(property "ki_description" "1W, 1000 VDC isolated DC/DC converter, 12V input, 5V output, SIP")
@ -9981,6 +9994,7 @@
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(property "DNP" "DNP")
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(property "ki_description" "Generic connector, double row, 02x04, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)")
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(property "Stock" "")

5
driver/driver.kicad_pro
View file

@ -58,12 +58,14 @@
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8
driver/driver.kicad_sch
View file

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3786
driver/gerber/driver-B_Cu.gbr
View file

File diff suppressed because it is too large Load diff

584
driver/gerber/driver-B_Mask.gbr
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256
driver/gerber/driver-F_Paste.gbr
View file

@ -1,12 +1,12 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.99.0-unknown*
G04 #@! TF.CreationDate,2023-05-27T12:11:34+02:00*
G04 #@! TF.CreationDate,2023-06-01T13:12:26+02:00*
G04 #@! TF.ProjectId,driver,64726976-6572-42e6-9b69-6361645f7063,rev?*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Paste,Top*
G04 #@! TF.FilePolarity,Positive*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 7.99.0-unknown) date 2023-05-27 12:11:34*
G04 Created by KiCad (PCBNEW 7.99.0-unknown) date 2023-06-01 13:12:26*
%MOMM*%
%LPD*%
G01*
@ -37,37 +37,37 @@ G04 Aperture macros list*
0 create outline with 4 corners*
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G04 Aperture macros list end*
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M02*

6466
driver/gerber/driver-F_SilkS.gbr
View file

File diff suppressed because it is too large Load diff

4
driver/gerber/driver-NPTH.drl
View file

@ -1,7 +1,7 @@
M48
; DRILL file {KiCad 7.99.0-unknown} date Sat 27 May 2023 12:11:36 PM CEST
; DRILL file {KiCad 7.99.0-unknown} date Thu 01 Jun 2023 01:12:21 PM CEST
; FORMAT={-:-/ absolute / inch / decimal}
; #@! TF.CreationDate,2023-05-27T12:11:36+02:00
; #@! TF.CreationDate,2023-06-01T13:12:21+02:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,7.99.0-unknown
; #@! TF.FileFunction,NonPlated,1,2,NPTH
FMAT,2

8
driver/gerber/driver-PTH.drl
View file

@ -1,7 +1,7 @@
M48
; DRILL file {KiCad 7.99.0-unknown} date Sat 27 May 2023 12:11:36 PM CEST
; DRILL file {KiCad 7.99.0-unknown} date Thu 01 Jun 2023 01:12:21 PM CEST
; FORMAT={-:-/ absolute / inch / decimal}
; #@! TF.CreationDate,2023-05-27T12:11:36+02:00
; #@! TF.CreationDate,2023-06-01T13:12:21+02:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,7.99.0-unknown
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T11
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1
driver_fw/.clang
View file

@ -1 +0,0 @@
flags = -g -Wall -std=gnu11 -O0 -fdump-rtl-expand -Wno-discarded-qualifiers -mlittle-endian -mcpu=cortex-m0 -mthumb -DSTM32F030x6 -DHSE_VALUE=8000000 -DMAC_ADDR=0xdeadbeef -I/home/user/resource/STM32Cube_FW_F0_V1.9.0/Drivers/CMSIS/Device/ST/STM32F0xx/Include -I/home/user/resource/STM32Cube_FW_F0_V1.9.0/Drivers/CMSIS/Include -I/home/user/resource/STM32Cube_FW_F0_V1.9.0/Drivers/STM32F0xx_HAL_Driver/Inc -Iconfig -I../common

15
driver_fw/.gitignore vendored
View file

@ -1,13 +1,2 @@
*.elf
*.o
*.expand
*.hex
*.lst
*.map
*.bin
*.pp
sources.c
sources.tar.xz
sources.tar.xz.zip
8b10b_test_decode
8b10b_test_encode
venv
build

227
driver_fw/Makefile
View file

@ -1,73 +1,192 @@
CUBE_PATH ?= $(wildcard ~)/ref/stm32cube/STM32CubeF0
CMSIS_PATH ?= $(CUBE_PATH)/Drivers/CMSIS
CMSIS_DEV_PATH ?= $(CMSIS_PATH)/Device/ST/STM32F0xx
HAL_PATH ?= $(CUBE_PATH)/Drivers/STM32F0xx_HAL_Driver
MAC_ADDR ?= 0xdeadbeef
########################################################################################################################
# Dependency directories
########################################################################################################################
CC := arm-none-eabi-gcc
LD := arm-none-eabi-ld
OBJCOPY := arm-none-eabi-objcopy
OBJDUMP := arm-none-eabi-objdump
SIZE := arm-none-eabi-size
MUSL_DIR ?= upstream/musl
CFLAGS = -g -Wall -std=gnu11 -O0 -fdump-rtl-expand -Wno-discarded-qualifiers
CFLAGS += -mlittle-endian -mcpu=cortex-m0 -mthumb
#CFLAGS += -ffunction-sections -fdata-sections
LDFLAGS = -nostartfiles
#LDFLAGS += -specs=rdimon.specs -DSEMIHOSTING
LDFLAGS += -Wl,-Map=main.map -nostdlib
#LDFLAGS += -Wl,--gc-sections
LIBS = -lgcc
#LIBS += -lrdimon
########################################################################################################################
# Algorithm parameters
########################################################################################################################
# Technically we're using an STM32F030F4, but apart from the TSSOP20 package that one is largely identical to the
# STM32F030*6 and there is no separate device header provided for it, so we're faking a *6 device here. This is
# even documented in stm32f0xx.h. Thanks ST!
CFLAGS += -DSTM32F030x6 -DHSE_VALUE=8000000 -DMAC_ADDR=$(MAC_ADDR)
# - none -
LDFLAGS += -Tstm32_flash.ld
CFLAGS += -I$(CMSIS_DEV_PATH)/Include -I$(CMSIS_PATH)/Include -I$(HAL_PATH)/Inc -Iconfig -I../common
#LDFLAGS += -L$(CMSIS_PATH)/Lib/GCC -larm_cortexM0l_math
########################################################################################################################
# High-level build parameters
########################################################################################################################
SOURCES = main.c startup_stm32f030x6.s system_stm32f0xx.c base.c $(HAL_PATH)/Src/stm32f0xx_ll_utils.c cmsis_exports.c \
../common/8b10b.c serial.c mac.c i2c.c lcd1602.c mcp9801.c ina226.c mini-printf.c
DEBUG ?= 1
OPT ?= 0
###################################################
BUILDDIR ?= build
BINARY := main.elf
LDSCRIPT := generic_stm32.ld
DEVICE := STM32G070RB
.PHONY: program clean
all: main.elf
########################################################################################################################
# Sources
########################################################################################################################
.clang:
echo flags = $(CFLAGS) > .clang
ASM_SOURCES := startup.s
cmsis_exports.c: $(CMSIS_DEV_PATH)/Include/stm32f030x6.h $(CMSIS_PATH)/Include/core_cm0.h
python3 gen_cmsis_exports.py $^ > $@
C_SOURCES := src/main.c
%.o: %.c
$(CC) -c $(CFLAGS) -o $@ $^
# $(CC) -E $(CFLAGS) -o $(@:.o=.pp) $^
CPP_SOURCES := # - none -
%.o: %.s
$(CC) -c $(CFLAGS) -o $@ $^
# $(CC) -E $(CFLAGS) -o $(@:.o=.pp) $^
MUSL_SOURCES := # - none -
MUSL_SOURCES := $(addprefix $(MUSL_DIR)/src/,$(MUSL_SOURCES))
C_SOURCES += $(MUSL_SOURCES)
########################################################################################################################
# Low-level build parameters
########################################################################################################################
PREFIX ?= arm-none-eabi-
HOSTCC := gcc
CC := $(PREFIX)gcc
CPP := $(PREFIX)cpp
CXX := $(PREFIX)g++
LD := $(PREFIX)gcc
AR := $(PREFIX)ar
AS := $(PREFIX)as
SIZE := $(PREFIX)size
NM := $(PREFIX)nm
OBJCOPY := $(PREFIX)objcopy
OBJDUMP := $(PREFIX)objdump
GDB := $(PREFIX)gdb
HOST_CC ?= $(HOST_PREFIX)gcc
HOST_CXX ?= $(HOST_PREFIX)g++
HOST_LD ?= $(HOST_PREFIX)gcc
HOST_AR ?= $(HOST_PREFIX)ar
HOST_AS ?= $(HOST_PREFIX)as
HOST_OBJCOPY ?= $(HOST_PREFIX)objcopy
HOST_OBJDUMP ?= $(HOST_PREFIX)objdump
PYTHON3 ?= python3
DOT ?= dot
MUSL_DIR_ABS := $(abspath $(MUSL_DIR))
CMSIS_DEVICE_DIR_ABS := $(abspath $(CMSIS_DEVICE_DIR))
DEVICE_FAMILY := $(shell echo $(DEVICE) | grep -Eio 'STM32[a-z]{1,2}[0-9]'|cut -c 6-)
DEVICE_DEFINES := -DSTM32$(DEVICE_FAMILY) $(addprefix -D,$(shell cat stm32_buildinfo.defines))
ARCH_FLAGS ?= -mthumb -mcpu=cortex-m0 -mfloat-abi=soft
SYSTEM_FLAGS ?= -nostdlib -ffreestanding -nostartfiles
COMMON_CFLAGS += -I$(abspath include)
COMMON_CFLAGS += -I$(BUILDDIR)
CFLAGS += -I$(abspath tools/musl_include_shims)
CFLAGS += -I$(abspath upstream/libusb_stm32/inc)
CFLAGS += -I$(CMSIS_DEVICE_DIR_ABS)/Include
CFLAGS += $(ARCH_FLAGS) $(SYSTEM_FLAGS)
CFLAGS += -fno-common -ffunction-sections -fdata-sections
COMMON_CFLAGS += -O$(OPT) -std=gnu2x -g
COMMON_CFLAGS += $(DEVICE_DEFINES)
COMMON_CFLAGS += -DDEBUG=$(DEBUG)
HOST_CFLAGS += $(COMMON_CFLAGS)
# for musl
CFLAGS += -Dhidden=
SIM_CFLAGS += -lm -DSIMULATION
SIM_CFLAGS += -Wall -Wextra -Wpedantic -Wshadow -Wimplicit-function-declaration -Wundef -Wno-unused-parameter
INT_CFLAGS += -Wall -Wextra -Wpedantic -Wshadow -Wimplicit-function-declaration -Wundef -Wno-unused-parameter
INT_CFLAGS += -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes
CXXFLAGS += -Os -g
CXXFLAGS += $(ARCH_FLAGS) $(SYSTEM_FLAGS)
CXXFLAGS += -fno-common -ffunction-sections -fdata-sections
CXXFLAGS += -Wall -Wextra -Wshadow -Wundef -Wredundant-decls
CXXFLAGS += -I.
LDFLAGS += $(ARCH_FLAGS) $(SYSTEM_FLAGS)
LIBS += -lgcc
#LDFLAGS += -Wl,--gc-sections
LINKMEM_FLAGS ?= --trim-stubs=startup.o --trace-sections .isr_vector --highlight-subdirs $(BUILDDIR)
OBJS := $(addprefix $(BUILDDIR)/,$(C_SOURCES:.c=.o) $(CXX_SOURCES:.cpp=.o) $(ASM_SOURCES:.s=.o))
ALL_OBJS := $(OBJS)
ALL_OBJS += $(BUILDDIR)/system.o
# Add generated source here.
########################################################################################################################
# Rules
########################################################################################################################
all: binsize
.PHONY: binsize
binsize: $(BUILDDIR)/$(BINARY) $(BUILDDIR)/$(BINARY:.elf=-symbol-sizes.pdf)
$(LD) -T$(LDSCRIPT) $(LDFLAGS) -Wl,--print-memory-usage -o /dev/null $(ALL_OBJS) $(LIBS)
@echo
@echo "▐▬▬▬▌ SyMbOL sIzE HiGhScORe LiSt ▐▬▬▬▌"
$(NM) --print-size --size-sort --radix=d $< | tail -n 20
.PRECIOUS: $(BUILDDIR)/$(BINARY)
$(BUILDDIR)/$(BINARY) $(BUILDDIR)/$(BINARY:.elf=.map) &: $(ALL_OBJS)
$(LD) -T$(LDSCRIPT) $(LDFLAGS) -o $@ -Wl,-Map=$(BUILDDIR)/$(BINARY:.elf=.map) $(ALL_OBJS) $(LIBS)
build/$(BINARY:.elf=-symbol-sizes.dot): $(ALL_OBJS)
$(PYTHON3) tools/linkmem.py $(LINKMEM_FLAGS) $(LD) -T$(LDSCRIPT) $(LDFLAGS) $^ $(LIBS) > $@
%.pdf: %.dot
$(DOT) -T pdf $< -o $@
%.dot: %.elf
r2 -a arm -qc 'aa;agC' $< 2>/dev/null >$@
r2 -a arm -qc 'aa;agRd' $< 2>/dev/null >$@
main.elf: $(SOURCES)
$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS)
$(OBJCOPY) -O ihex $@ $(@:.elf=.hex)
$(OBJCOPY) -O binary $@ $(@:.elf=.bin)
$(OBJDUMP) -St $@ >$(@:.elf=.lst)
$(SIZE) $@
program: main.elf openocd.cfg
openocd -f openocd.cfg -c "program $< verify reset exit"
$(BUILDDIR)/src/%.o: src/%.s
mkdir -p $(@D)
$(CC) $(COMMON_CFLAGS) $(CFLAGS) $(INT_CFLAGS) -o $@ -c $<
$(BUILDDIR)/src/%.o: src/%.c
mkdir -p $(@D)
$(CC) $(COMMON_CFLAGS) $(CFLAGS) $(INT_CFLAGS) -o $@ -c $<
$(BUILDDIR)/src/%.o: src/%.cpp
mkdir -p $(@D)
$(CXX) $(CXXFLAGS) -o $@ -c $<
$(BUILDDIR)/%.o: %.c
mkdir -p $(@D)
$(CC) $(COMMON_CFLAGS) $(CFLAGS) $(EXT_CFLAGS) -o $@ -c $<
$(BUILDDIR)/%.o: %.s
mkdir -p $(@D)
$(CC) $(COMMON_CFLAGS) $(CFLAGS) $(EXT_CFLAGS) -o $@ -c $<
venv:
test -d venv || python3 -m venv --system-site-packages venv
source venv/bin/activate && pip install cxxfilt pyelftools libarchive matplotlib
clean:
rm -f **.o **.pp
rm -f main.elf main.hex main.bin main.map main.lst
rm -f **.expand
rm -rf $(BUILDDIR)/src
rm -f $(BUILDDIR)/**.o
rm -f $(BUILDDIR)/$(BINARY)
rm -f $(BUILDDIR)/$(BINARY:.elf=.map)
rm -f $(BUILDDIR)/$(BINARY:.elf=-symbol-sizes.dot)
rm -f $(BUILDDIR)/$(BINARY:.elf=-symbol-sizes.pdf)
rm -f $(BUILDDIR)/crc32_test
rm -f $(BUILDDIR)/microcobs_test_sg
rm -f $(BUILDDIR)/microcobs_test
rm -f $(BUILDDIR)/microcobs_decode_test
mrproper: clean
rm -rf build
.PHONY: clean mrproper
-include $(OBJS:.o=.d)

28
driver_fw/base.c
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@ -1,28 +0,0 @@
#include <unistd.h>
int __errno = 0;
void *_impure_ptr = NULL;
void __sinit(void) {
}
void *memset(void *s, int c, size_t n) {
char *end = (char *)s + n;
for (char *p = (char *)s; p < end; p++)
*p = (char)c;
return s;
}
size_t strlen(const char *s) {
const char *start = s;
while (*s++);
return s - start - 1;
}
char *strcpy(char *dst, const char *src) {
char *p = dst;
while (*src)
*p++ = *src++;
return dst;
}

48
driver_fw/cmsis_exports.c
View file

@ -1,48 +0,0 @@
#ifndef __GENERATED_CMSIS_HEADER_EXPORTS__
#define __GENERATED_CMSIS_HEADER_EXPORTS__
#include <stm32f030x6.h>
/* stm32f030x6.h */
TIM_TypeDef *tim3 = TIM3;
TIM_TypeDef *tim14 = TIM14;
RTC_TypeDef *rtc = RTC;
WWDG_TypeDef *wwdg = WWDG;
IWDG_TypeDef *iwdg = IWDG;
I2C_TypeDef *i2c1 = I2C1;
PWR_TypeDef *pwr = PWR;
SYSCFG_TypeDef *syscfg = SYSCFG;
EXTI_TypeDef *exti = EXTI;
ADC_TypeDef *adc1 = ADC1;
ADC_Common_TypeDef *adc1_common = ADC1_COMMON;
ADC_Common_TypeDef *adc = ADC;
TIM_TypeDef *tim1 = TIM1;
SPI_TypeDef *spi1 = SPI1;
USART_TypeDef *usart1 = USART1;
TIM_TypeDef *tim16 = TIM16;
TIM_TypeDef *tim17 = TIM17;
DBGMCU_TypeDef *dbgmcu = DBGMCU;
DMA_TypeDef *dma1 = DMA1;
DMA_Channel_TypeDef *dma1_channel1 = DMA1_Channel1;
DMA_Channel_TypeDef *dma1_channel2 = DMA1_Channel2;
DMA_Channel_TypeDef *dma1_channel3 = DMA1_Channel3;
DMA_Channel_TypeDef *dma1_channel4 = DMA1_Channel4;
DMA_Channel_TypeDef *dma1_channel5 = DMA1_Channel5;
FLASH_TypeDef *flash = FLASH;
OB_TypeDef *ob = OB;
RCC_TypeDef *rcc = RCC;
CRC_TypeDef *crc = CRC;
GPIO_TypeDef *gpioa = GPIOA;
GPIO_TypeDef *gpiob = GPIOB;
GPIO_TypeDef *gpioc = GPIOC;
GPIO_TypeDef *gpiod = GPIOD;
GPIO_TypeDef *gpiof = GPIOF;
#include <core_cm0.h>
/* core_cm0.h */
SCB_Type *scb = SCB;
SysTick_Type *systick = SysTick;
NVIC_Type *nvic = NVIC;
#endif//__GENERATED_CMSIS_HEADER_EXPORTS__

30
driver_fw/gen_cmsis_exports.py
View file

@ -1,30 +0,0 @@
#!/usr/bin/env python3
import re
import os
if __name__ == '__main__':
import argparse
parser = argparse.ArgumentParser()
parser.add_argument('cmsis_device_header', nargs='+', type=argparse.FileType('rb'))
args = parser.parse_args()
print('#ifndef __GENERATED_CMSIS_HEADER_EXPORTS__')
print('#define __GENERATED_CMSIS_HEADER_EXPORTS__')
print()
for header in args.cmsis_device_header:
lines = header.readlines()
name = os.path.basename(header.name)
print('#include <{}>'.format(name))
print()
print('/* {} */'.format(name))
for l in lines:
match = re.match(b'^#define (\w+)\s+\W*(\w+_TypeDef|\w+_Type).*$', l)
if match:
inst, typedef = match.groups()
inst, typedef = inst.decode(), typedef.decode()
print('{} *{} = {};'.format(typedef, inst.lower(), inst))
print()
print('#endif//__GENERATED_CMSIS_HEADER_EXPORTS__')

125
driver_fw/generic_stm32.ld Normal file
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@ -0,0 +1,125 @@
/* Entry Point */
ENTRY(Reset_Handler)
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
INCLUDE memory_map.ldi
}
/* Highest address of the user mode stack */
PROVIDE(_estack = ORIGIN(RAM) + LENGTH(RAM));
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
.ARM.attributes 0 : { *(.ARM.attributes) }
}

58
driver_fw/global.h
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@ -1,58 +0,0 @@
/* Megumin LED display firmware
* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __GLOBAL_H__
#define __GLOBAL_H__
/* Workaround for sub-par ST libraries */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
#include <stm32f0xx.h>
#include <stm32f0xx_ll_utils.h>
#include <stm32f0xx_ll_spi.h>
#pragma GCC diagnostic pop
#include <system_stm32f0xx.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <unistd.h>
/* Microcontroller part number: STM32F030F4P6 */
/* Things used for module status reporting. */
#define FIRMWARE_VERSION 1
#define HARDWARE_VERSION 3
#define TS_CAL1 (*(uint16_t *)0x1FFFF7B8)
#define VREFINT_CAL (*(uint16_t *)0x1FFFF7BA)
#define STATUS_LED_DURATION_MS 200
#define TICK_MS 10
extern volatile unsigned int sys_time_tick;
extern volatile unsigned int sys_time_ms;
extern volatile unsigned int sys_time_s;
extern unsigned int frame_duration_us;
extern volatile uint8_t global_brightness;
void trigger_error_led(void);
void trigger_comm_led(void);
#endif/*__GLOBAL_H__*/

236
driver_fw/i2c.c
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@ -1,236 +0,0 @@
// Inter-integrated circuit (I2C) management
#include "i2c.h"
// I2C timeout, about 2ms
#define I2C_TIMEOUT 200U
// Maximum NBYTES value
#define I2C_NBYTES_MAX 255U
// Count rough delay for timeouts
static uint32_t i2c_calc_delay(uint32_t delay) {
uint32_t cnt;
if (SystemCoreClock > 1000000U) {
cnt = (delay * ((SystemCoreClock / 1000000U) + 1U));
} else {
cnt = (((delay / 100U) + 1U) * ((SystemCoreClock / 10000U) + 1U));
}
return cnt;
}
// Check if target device is ready for communication
// input:
// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
// devAddr - target device address
// trials - number of trials (must not be zero)
// return:
// I2C_ERROR if there was a timeout during I2C operations, I2C_SUCCESS otherwise
I2CSTATUS i2c_is_device_ready(I2C_TypeDef* I2Cx, uint8_t devAddr, uint32_t trials) {
volatile uint32_t wait;
uint32_t delay_val = i2c_calc_delay(I2C_TIMEOUT);
uint32_t reg;
while (trials--) {
// Clear all flags
I2Cx->ICR = I2C_ICR_ALL;
// Generate START
i2c_genstart(I2Cx, devAddr);
// Wait for STOP, NACK or BERR
wait = delay_val;
while (!((reg = I2Cx->ISR) & (I2C_ISR_STOPF | I2C_ISR_NACKF | I2C_ISR_BERR)) && --wait);
if (wait == 0) { return I2C_ERROR; }
// Wait while STOP flag is reset
wait = delay_val;
while (!(I2Cx->ISR & I2C_ISR_STOPF) && --wait);
if (wait == 0) { return I2C_ERROR; }
// Clear the NACK, STOP and BERR flags
I2Cx->ICR = I2C_ICR_STOPCF | I2C_ICR_NACKCF | I2C_ICR_BERRCF;
// Check for BERR flag
if (reg & I2C_ISR_BERR) {
// Misplaced START/STOP? Perform a software reset of I2C
i2c_disable(I2Cx);
i2c_enable(I2Cx);
} else {
// Device responded if NACK flag is not set
if (!(reg & I2C_ISR_NACKF)) { return I2C_SUCCESS; }
}
}
return I2C_ERROR;
}
// Transmit an amount of data in master mode
// input:
// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
// pBbuf - pointer to the data buffer
// nbytes - number of bytes to transmit
// devAddr - address of target device
// flags - options for transmission, combination of I2C_TX_xx values:
// I2C_TX_NOSTART - don't generate START condition
// I2C_TX_NOSTOP - don't generate STOP condition
// I2C_TX_CONT - this flag indicates that transmission will be continued
// e.g. by calling this function again with NOSTART flag
// zero value - generate both START and STOP conditions
// return:
// I2C_ERROR if there was a timeout during I2C operations, I2C_SUCCESS otherwise
I2CSTATUS i2c_transmit(I2C_TypeDef* I2Cx, const uint8_t *pBuf, uint32_t nbytes, uint8_t devAddr, uint32_t flags) {
uint32_t reg;
uint32_t tx_count;
uint32_t delay_val = i2c_calc_delay(I2C_TIMEOUT);
volatile uint32_t wait;
// Clear all flags
I2Cx->ICR = I2C_ICR_ALL;
// Everything regarding to the transmission is in the CR2 register
reg = I2Cx->CR2;
reg &= ~I2C_CR2_ALL;
// Slave device address
reg |= (devAddr & I2C_CR2_SADD);
// Whether it need to generate START condition
if (!(flags & I2C_TX_NOSTART)) { reg |= I2C_CR2_START; }
// Whether it need to generate STOP condition
if ((flags & I2C_TX_CONT) || (nbytes > I2C_NBYTES_MAX)) {
reg |= I2C_CR2_RELOAD;
} else {
if (!(flags & I2C_TX_NOSTOP)) { reg |= I2C_CR2_AUTOEND; }
}
// Transfer length
tx_count = (nbytes > I2C_NBYTES_MAX) ? I2C_NBYTES_MAX : nbytes;
nbytes -= tx_count;
reg |= tx_count << I2C_CR2_NBYTES_Pos;
// Write a composed value to the I2C register
I2Cx->CR2 = reg;
// Transmit data
while (tx_count) {
// Wait until either TXIS or NACK flag is set
wait = delay_val;
while (!((reg = I2Cx->ISR) & (I2C_ISR_TXIS | I2C_ISR_NACKF)) && --wait);
if ((reg & I2C_ISR_NACKF) || (wait == 0)) { return I2C_ERROR; }
// Transmit byte
I2Cx->TXDR = *pBuf++;
tx_count--;
if ((tx_count == 0) && (nbytes != 0)) {
// Wait until TCR flag is set (Transfer Complete Reload)
wait = delay_val;
while (!(I2Cx->ISR & I2C_ISR_TCR) && --wait);
if (wait == 0) { return I2C_ERROR; }
// Configure next (or last) portion transfer
reg = I2Cx->CR2;
reg &= ~(I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND);
if ((flags & I2C_TX_CONT) || (nbytes > I2C_NBYTES_MAX)) {
reg |= I2C_CR2_RELOAD;
} else {
if (!(flags & I2C_TX_NOSTOP)) { reg |= I2C_CR2_AUTOEND; }
}
tx_count = (nbytes > I2C_NBYTES_MAX) ? I2C_NBYTES_MAX : nbytes;
nbytes -= tx_count;
reg |= tx_count << I2C_CR2_NBYTES_Pos;
I2Cx->CR2 = reg;
}
}
// End of transmission
wait = delay_val;
while (!(I2Cx->ISR & (I2C_ISR_TC | I2C_ISR_TCR | I2C_ISR_STOPF)) && --wait);
return (wait) ? I2C_SUCCESS : I2C_ERROR;
}
// Receive an amount of data in master mode
// input:
// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
// buf - pointer to the data buffer
// nbytes - number of bytes to receive
// devAddr - address of target device
// return:
// I2C_ERROR if there was a timeout during I2C operations, I2C_SUCCESS otherwise
I2CSTATUS i2c_receive(I2C_TypeDef* I2Cx, uint8_t *pBuf, uint32_t nbytes, uint8_t devAddr) {
uint32_t reg;
uint32_t rx_count;
uint32_t delay_val = i2c_calc_delay(I2C_TIMEOUT);
volatile uint32_t wait;
// Clear all flags
I2Cx->ICR = I2C_ICR_ALL;
// Everything regarding to the transmission is in the CR2 register
reg = I2Cx->CR2;
reg &= ~I2C_CR2_ALL;
// Configure slave device address, enable START condition and set direction to READ
reg |= (devAddr & I2C_CR2_SADD) | I2C_CR2_START | I2C_CR2_RD_WRN;
// Transfer length
if (nbytes > I2C_NBYTES_MAX) {
rx_count = I2C_NBYTES_MAX;
reg |= I2C_CR2_RELOAD;
} else {
rx_count = nbytes;
reg |= I2C_CR2_AUTOEND;
}
reg |= rx_count << I2C_CR2_NBYTES_Pos;
nbytes -= rx_count;
// Write a composed value to the I2C register
I2Cx->CR2 = reg;
// Receive data
while (rx_count) {
// Wait until either RXNE or NACK flag is set
wait = delay_val;
while (!((reg = I2Cx->ISR) & (I2C_ISR_RXNE | I2C_ISR_NACKF)) && --wait);
if ((reg & I2C_ISR_NACKF) || (wait == 0)) { return I2C_ERROR; }
// Read received data
*pBuf++ = I2Cx->RXDR;
rx_count--;
if ((rx_count == 0) && (nbytes != 0)) {
// Wait until TCR flag is set (Transfer Complete Reload)
wait = delay_val;
while (!(I2Cx->ISR & I2C_ISR_TCR) && --wait);
if (wait == 0) { return I2C_ERROR; }
// Configure next (or last) portion transfer
reg = I2Cx->CR2;
reg &= ~(I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_RELOAD);
if (nbytes > I2C_NBYTES_MAX) {
rx_count = I2C_NBYTES_MAX;
reg |= I2C_CR2_RELOAD;
} else {
rx_count = nbytes;
reg |= I2C_CR2_AUTOEND;
}
reg |= rx_count << I2C_CR2_NBYTES_Pos;
nbytes -= rx_count;
I2Cx->CR2 = reg;
}
}
// Wait for the STOP flag
wait = delay_val;
while (!(I2Cx->ISR & I2C_ISR_STOPF) && --wait);
return (wait) ? I2C_SUCCESS : I2C_ERROR;
}

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#ifndef __I2C_H
#define __I2C_H
#include "global.h"
// Definitions of I2C analog filter state
#define I2C_AF_ENABLE ((uint32_t)0x00000000U) // Analog filter is enabled
#define I2C_AF_DISABLE I2C_CR1_ANFOFF // Analog filter is disabled
// Flags definitions for transmit function
#define I2C_TX_STOP ((uint32_t)0x00000000U) // Generate STOP condition
#define I2C_TX_NOSTOP ((uint32_t)0x10000000U) // Don't generate STOP condition
#define I2C_TX_NOSTART ((uint32_t)0x20000000U) // Don't generate START condition
#define I2C_TX_CONT ((uint32_t)0x40000000U) // The transmission will be continued
// Definitions for compatibility with old code using this library
#define I2C_GENSTOP_YES I2C_TX_STOP
#define I2C_GENSTOP_NO I2C_TX_NOSTOP
// Definition of bits to reset in CR2 register
#define I2C_CR2_ALL (I2C_CR2_SADD | \
I2C_CR2_NBYTES | \
I2C_CR2_RELOAD | \
I2C_CR2_AUTOEND | \
I2C_CR2_RD_WRN | \
I2C_CR2_START | \
I2C_CR2_STOP)
// Definition of all bits in ICR register (clear all I2C flags at once)
#define I2C_ICR_ALL (I2C_ICR_ADDRCF | \
I2C_ICR_ALERTCF | \
I2C_ICR_ARLOCF | \
I2C_ICR_BERRCF | \
I2C_ICR_NACKCF | \
I2C_ICR_OVRCF | \
I2C_ICR_PECCF | \
I2C_ICR_STOPCF | \
I2C_ICR_TIMOUTCF)
// Result of I2C functions
typedef enum {
I2C_ERROR = 0,
I2C_SUCCESS = !I2C_ERROR
} I2CSTATUS;
// Public functions and macros
// Enable I2C peripheral
// input:
// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
static inline void i2c_enable(I2C_TypeDef* I2Cx) {
I2Cx->CR1 |= I2C_CR1_PE;
}
// Disable I2C peripheral
// input:
// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
static inline void i2c_disable(I2C_TypeDef* I2Cx) {
I2Cx->CR1 &= ~I2C_CR1_PE;
}
// Configure I2C noise filters
// input:
// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
// af - analog filter state, I2C_AF_DISABLE or I2C_AF_ENABLE
// df - digital filter configuration, can be a value in range from 0 to 15
// zero value means the digital filter is disabled
// this values means filtering capability up to (df * ti2cclk)
// note: must be called only when I2C is disabled (PE bit in I2C_CR1 register is reset)
static inline void i2c_config_filters(I2C_TypeDef* I2Cx, uint32_t af, uint32_t df) {
I2Cx->CR1 &= ~(I2C_CR1_ANFOFF | I2C_CR1_DNF);
I2Cx->CR1 |= (af & I2C_CR1_ANFOFF) | ((df << I2C_CR1_DNF_Pos) & I2C_CR1_DNF);
}
// Configure the I2C timings (SDA setup/hold time and SCL high/low period)
// input:
// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
// timing - the value for I2C_TIMINGR register
// note: must be called only when I2C is disabled (PE bit in I2C_CR1 register is reset)
static inline void i2c_config_timing(I2C_TypeDef* I2Cx, uint32_t timing) {
I2Cx->TIMINGR = timing;
}
// Generate START condition
// input:
// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
// addr - I2C device address
// note: 7-bit addressing mode
static inline void i2c_genstart(I2C_TypeDef* I2Cx, uint32_t addr) {
I2Cx->CR2 = (addr & I2C_CR2_SADD) | I2C_CR2_START | I2C_CR2_AUTOEND;
}
// Generate STOP condition
// input:
// I2Cx - pointer to the I2C peripheral (I2C1, etc.)
static inline void i2c_genstop(I2C_TypeDef* I2Cx) {
I2Cx->CR2 |= I2C_CR2_STOP;
}
// Function prototypes
I2CSTATUS i2c_is_device_ready(I2C_TypeDef* I2Cx, uint8_t devAddr, uint32_t Trials);
I2CSTATUS i2c_transmit(I2C_TypeDef* I2Cx, const uint8_t *pBuf, uint32_t nbytes, uint8_t devAddr, uint32_t flags);
I2CSTATUS i2c_receive(I2C_TypeDef* I2Cx, uint8_t *pBuf, uint32_t nbytes, uint8_t devAddr);
#endif // __I2C_H

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#include "global.h"
#include "i2c.h"
#include "ina226.h"
void ina226_init() {
/* FIXME plug in final values for I meas backchannel */
uint16_t config = INA226_CONFIG_AVG_1 | INA226_CONFIG_VBUSCT_204u | INA226_CONFIG_VSHCT_4m156 |
INA226_CONFIG_MODE_SHUNT | INA226_CONFIG_MODE_BUS | INA226_CONFIG_MODE_CONT;
ina226_write_reg(INA226_REG_CONFIG, config);
ina226_write_reg(INA226_REG_CAL, INA226_CAL);
}
void ina226_write_reg(uint8_t reg, uint16_t val) {
uint8_t buf[3] = { reg, val>>8, val&0xff };
i2c_transmit(INA226_I2C_PERIPH, buf, sizeof(buf), INA226_I2C_ADDR, I2C_GENSTOP_YES);
}
uint16_t ina226_read_reg(uint8_t reg) {
uint8_t buf2[1] = { reg };
i2c_transmit(INA226_I2C_PERIPH, buf2, sizeof(buf2), INA226_I2C_ADDR, I2C_GENSTOP_NO);
uint8_t rx[2];
i2c_receive(INA226_I2C_PERIPH, rx, sizeof(rx), INA226_I2C_ADDR);
return (rx[0]<<8) | rx[1];
}

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driver_fw/ina226.h
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#ifndef __INA226_H__
#define __INA226_H__
#include <stdint.h>
#define INA226_I2C_PERIPH I2C1
#define INA226_I2C_ADDR 0x80
#define INA226_I_LSB_uA 2000
#define INA226_VB_LSB_uV 1250
#define INA226_VS_LSB_nV 2500
#define INA226_RSHUNT_uOhm 2000
/* FIXME validate this */
#define INA226_CAL (5120000 / INA226_I_LSB_uA * 1000 / INA226_RSHUNT_uOhm)
enum ina226_reg {
INA226_REG_CONFIG = 0x00,
INA226_REG_VS = 0x01,
INA226_REG_VB = 0x02,
INA226_REG_P = 0x03,
INA226_REG_I = 0x04,
INA226_REG_CAL = 0x05,
INA226_REG_MASK_EN = 0x06,
INA226_REG_ALERT = 0x07,
INA226_REG_MFGID = 0xfe,
INA226_REG_DIEID = 0xff
};
enum ina226_config {
INA226_CONFIG_RST = 1<<15,
INA226_CONFIG_AVG_Pos = 9,
INA226_CONFIG_AVG_Msk = 3<<9,
INA226_CONFIG_AVG_1 = 0<<9,
INA226_CONFIG_AVG_4 = 1<<9,
INA226_CONFIG_AVG_16 = 2<<9,
INA226_CONFIG_AVG_64 = 3<<9,
INA226_CONFIG_AVG_128 = 4<<9,
INA226_CONFIG_AVG_256 = 5<<9,
INA226_CONFIG_AVG_512 = 6<<9,
INA226_CONFIG_AVG_1024 = 7<<9,
INA226_CONFIG_VBUSCT_Pos = 6,
INA226_CONFIG_VBUSCT_Msk = 7<<6,
INA226_CONFIG_VBUSCT_140u = 0<<6,
INA226_CONFIG_VBUSCT_204u = 1<<6,
INA226_CONFIG_VBUSCT_332u = 2<<6,
INA226_CONFIG_VBUSCT_588u = 3<<6,
INA226_CONFIG_VBUSCT_1m1 = 4<<6,
INA226_CONFIG_VBUSCT_2m116 = 5<<6,
INA226_CONFIG_VBUSCT_4m156 = 6<<6,
INA226_CONFIG_VBUSCT_8m244 = 7<<6,
INA226_CONFIG_VSHCT_Pos = 3,
INA226_CONFIG_VSHCT_Msk = 7<<3,
INA226_CONFIG_VSHCT_140u = 0<<3,
INA226_CONFIG_VSHCT_204u = 1<<3,
INA226_CONFIG_VSHCT_332u = 2<<3,
INA226_CONFIG_VSHCT_588u = 3<<3,
INA226_CONFIG_VSHCT_1m1 = 4<<3,
INA226_CONFIG_VSHCT_2m116 = 5<<3,
INA226_CONFIG_VSHCT_4m156 = 6<<3,
INA226_CONFIG_VSHCT_8m244 = 7<<3,
INA226_CONFIG_MODE_Pos = 0,
INA226_CONFIG_MODE_Msk = 7,
INA226_CONFIG_MODE_POWERDOWN = 0,
INA226_CONFIG_MODE_SHUNT = 1,
INA226_CONFIG_MODE_BUS = 2,
INA226_CONFIG_MODE_TRIG = 0,
INA226_CONFIG_MODE_CONT = 4
};
void ina226_init(void);
void ina226_write_reg(uint8_t reg, uint16_t val);
uint16_t ina226_read_reg(uint8_t reg);
static inline int16_t ina226_read_i(void) { return (int16_t)ina226_read_reg(INA226_REG_I); }
static inline int16_t ina226_read_v(void) { return (int16_t)ina226_read_reg(INA226_REG_VB); }
static inline uint16_t ina226_read_p(void) { return ina226_read_reg(INA226_REG_P); }
static inline int16_t ina226_read_vs(void) { return (int16_t)ina226_read_reg(INA226_REG_VS); }
#endif /* __INA226_H__ */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.3
* @date 24. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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#ifndef __GLOBAL_H__
#define __GLOBAL_H__
#include <stdbool.h>
#include <stdint.h>
#include <sys/types.h>
#include <assert.h>
#include <string.h>
/* The IRQ header must be included before stm32_device.h since ST defines a bunch of messy macros there. */
#include <stm32_irqs.h> /* Header generated from stm32***_startup.s in Makefile */
#include <stm32g0xx.h>
#include <core_cm0plus.h>
#define COUNT_OF(x) ((sizeof(x)/sizeof(0[x])) / ((size_t)(!(sizeof(x) % sizeof(0[x])))))
#define AFRL(pin, val) ((val) << ((pin)*4))
#define AFRH(pin, val) ((val) << (((pin)-8)*4))
#define AF(pin) (2<<(2*(pin)))
#define OUT(pin) (1<<(2*(pin)))
#define IN(pin) (0)
#define ANALOG(pin) (3<<(2*(pin)))
#define CLEAR(pin) (~(3<<(2*(pin))))
#define PULLUP(pin) (1<<(2*pin))
#define PULLDOWN(pin) (2<<(2*pin))
#define BSRR_CLEAR(pin) ((1<<pin)<<16)
#define BSRR_SET(pin) (1<<pin)
#define BSRR_VALUE(pin, value) ((((!(value))<<pin)<<16) | ((!!(value))<<pin))
#ifndef SYSTICK_INTERVAL_US
#define SYSTICK_INTERVAL_US 1000
#endif /* SYSTICK_INTERVAL_US */
enum ErrorCode {
ERR_SUCCESS = 0,
ERR_TIMEOUT,
ERR_PHYSICAL_LAYER,
ERR_FRAMING,
ERR_PROTOCOL,
ERR_DMA,
ERR_BUSY,
ERR_BUFFER_OVERFLOW,
ERR_RX_OVERRUN,
ERR_TX_OVERRUN,
};
typedef enum ErrorCode ErrorCode;
void delay_us(int duration_us);
extern volatile uint64_t sys_time_us;
#endif /* __GLOBAL_H__ */

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#ifndef __IOMACROS_H__
#define __IOMACROS_H__
#define IN(pin) (0)
#define OUT(pin) (1<<(2*(pin)))
#define AF(pin) (2<<(2*(pin)))
#define ANALOG(pin) (3<<(2*(pin)))
#define CLEAR(pin) (~(3<<(2*(pin))))
#define AFRL(pin, val) ((val) << ((pin)*4))
#define AFRH(pin, val) ((val) << (((pin)-8)*4))
#endif __IOMACROS_H__

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/* AUTOGENERATED FILE! DO NOT MODIFY! */
/* Generated 2023-07-10 20:34:05.404513 from startup.s by gen_isr_header.py */
void _estack(void); /* 0 */
void Reset_Handler(void); /* 1 */
void NMI_Handler(void); /* 2 */
void HardFault_Handler(void); /* 3 */
/* IRQ 4 is undefined for this part. */
/* IRQ 5 is undefined for this part. */
/* IRQ 6 is undefined for this part. */
/* IRQ 7 is undefined for this part. */
/* IRQ 8 is undefined for this part. */
/* IRQ 9 is undefined for this part. */
/* IRQ 10 is undefined for this part. */
void SVC_Handler(void); /* 11 */
/* IRQ 12 is undefined for this part. */
/* IRQ 13 is undefined for this part. */
void PendSV_Handler(void); /* 14 */
void SysTick_Handler(void); /* 15 */
void WWDG_IRQHandler(void); /* 16 */
/* IRQ 17 is undefined for this part. */
void RTC_TAMP_IRQHandler(void); /* 18 */
void FLASH_IRQHandler(void); /* 19 */
void RCC_IRQHandler(void); /* 20 */
void EXTI0_1_IRQHandler(void); /* 21 */
void EXTI2_3_IRQHandler(void); /* 22 */
void EXTI4_15_IRQHandler(void); /* 23 */
/* IRQ 24 is undefined for this part. */
void DMA1_Channel1_IRQHandler(void); /* 25 */
void DMA1_Channel2_3_IRQHandler(void); /* 26 */
void DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler(void); /* 27 */
void ADC1_IRQHandler(void); /* 28 */
void TIM1_BRK_UP_TRG_COM_IRQHandler(void); /* 29 */
void TIM1_CC_IRQHandler(void); /* 30 */
/* IRQ 31 is undefined for this part. */
void TIM3_IRQHandler(void); /* 32 */
void TIM6_IRQHandler(void); /* 33 */
void TIM7_IRQHandler(void); /* 34 */
void TIM14_IRQHandler(void); /* 35 */
void TIM15_IRQHandler(void); /* 36 */
void TIM16_IRQHandler(void); /* 37 */
void TIM17_IRQHandler(void); /* 38 */
void I2C1_IRQHandler(void); /* 39 */
void I2C2_IRQHandler(void); /* 40 */
void SPI1_IRQHandler(void); /* 41 */
void SPI2_IRQHandler(void); /* 42 */
void USART1_IRQHandler(void); /* 43 */
void USART2_IRQHandler(void); /* 44 */
void USART3_4_IRQHandler(void); /* 45 */
#define NUM_IRQs 46
extern uint32_t g_pfnVectors[NUM_IRQs];
#define isr_vector g_pfnVectors

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/**
******************************************************************************
* @file stm32g0xx.h
* @author MCD Application Team
* @brief CMSIS STM32G0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32G0xx device used in the target application
* - To use or not the peripherals drivers in application code(i.e.
* code will be based on direct access to peripherals registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* Copyright (c) 2018-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32g0xx
* @{
*/
#ifndef STM32G0xx_H
#define STM32G0xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32G0)
#define STM32G0
#endif /* STM32G0 */
/* Uncomment the line below according to the target STM32G0 device used in your
application
*/
#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \
&& !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \
&& !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \
&& !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx)
/* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */
/* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */
/* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */
/* #define STM32G070xx */ /*!< STM32G070xx Devices */
/* #define STM32G071xx */ /*!< STM32G071xx Devices */
/* #define STM32G081xx */ /*!< STM32G081xx Devices */
/* #define STM32G050xx */ /*!< STM32G050xx Devices */
/* #define STM32G051xx */ /*!< STM32G051xx Devices */
/* #define STM32G061xx */ /*!< STM32G061xx Devices */
/* #define STM32G030xx */ /*!< STM32G030xx Devices */
/* #define STM32G031xx */ /*!< STM32G031xx Devices */
/* #define STM32G041xx */ /*!< STM32G041xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number $VERSION$
*/
#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
#define __STM32G0_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
|(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
|(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32G0_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32G0B1xx)
#include "stm32g0b1xx.h"
#elif defined(STM32G0C1xx)
#include "stm32g0c1xx.h"
#elif defined(STM32G0B0xx)
#include "stm32g0b0xx.h"
#elif defined(STM32G071xx)
#include "stm32g071xx.h"
#elif defined(STM32G081xx)
#include "stm32g081xx.h"
#elif defined(STM32G070xx)
#include "stm32g070xx.h"
#elif defined(STM32G031xx)
#include "stm32g031xx.h"
#elif defined(STM32G041xx)
#include "stm32g041xx.h"
#elif defined(STM32G030xx)
#include "stm32g030xx.h"
#elif defined(STM32G051xx)
#include "stm32g051xx.h"
#elif defined(STM32G061xx)
#include "stm32g061xx.h"
#elif defined(STM32G050xx)
#include "stm32g050xx.h"
#else
#error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/* Use of interrupt control for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t primask; \
primask = __get_PRIMASK(); \
__set_PRIMASK(1); \
SET_BIT((REG), (BIT)); \
__set_PRIMASK(primask); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t primask; \
primask = __get_PRIMASK(); \
__set_PRIMASK(1); \
CLEAR_BIT((REG), (BIT)); \
__set_PRIMASK(primask); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t primask; \
primask = __get_PRIMASK(); \
__set_PRIMASK(1); \
MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \
__set_PRIMASK(primask); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
/*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32g0xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32G0xx_H */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file system_stm32g0xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M0+ Device System Source File for STM32G0xx devices.
******************************************************************************
* @attention
*
* Copyright (c) 2018-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32g0xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef SYSTEM_STM32G0XX_H
#define SYSTEM_STM32G0XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32G0xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*SYSTEM_STM32G0XX_H */
/**
* @}
*/
/**
* @}
*/

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/*
This is free and unencumbered software released into the public domain.
( https://github.com/KonstantinDM )
Anyone is free to copy, modify, publish, use, compile, sell, or
distribute this software, either in source code form or as a compiled
binary, for any purpose, commercial or non-commercial, and by any
means.
In jurisdictions that recognize copyright laws, the author or authors
of this software dedicate any and all copyright interest in the
software to the public domain. We make this dedication for the benefit
of the public at large and to the detriment of our heirs and
successors. We intend this dedication to be an overt act of
relinquishment in perpetuity of all present and future rights to this
software under copyright law.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
For more information, please refer to <http://unlicense.org>
*/
#include "global.h"
#include "i2c.h"
#include "lcd1602.h"
static void write_byte(uint8_t in_u8Byte); // Отпвить байт на шину
static void send_half_byte(uint8_t in_u8Byte); // Отправить пол байта
static void send_command(uint8_t in_u8Byte); // Отправить байт команду
static void delay_micro(uint32_t in_u8micros);
static uint8_t lcd_gpio = 0;
/*
Инициализация дисплея, обязательнаяпроцедура
на входе: *
на выходе: *
*/
void lcd1602_init()
{
// Инициализация экрана обязательна
delay_micro(15000);
send_half_byte(LCD_INITIALIZATION);
delay_micro(4000);
send_half_byte(LCD_INITIALIZATION);
delay_micro(100000);
send_half_byte(LCD_INITIALIZATION);
delay_micro(1000);
send_half_byte(LCD_SET_CURSOR_TO_START);
// Найстрока дисплея
send_command(LCD_SET_INTERFACE_LINES_FONT | LCD_4BIT_INTERFACE | LCD_TWO_LINE | LCD_5x8_FONT);
send_command(LCD_SET_CURSOR_AND_POWE_MODE | LCD_DISPLAY_ON | LCD_CURSOR_OFF | LCD_CURSOR_BLINK_OFF);
send_command(LCD_SET_SHIFT_AND_CHAR_DIRECTION | LCD_CHAR_DIRECTION_LEFT_RIGHT | LCD_SHIFT_DISABLE);
// Очистить экран
lcd_clear();
// Включить подсветку и режим записи
lcd_gpio |= LCD_MODE_LED;
lcd_gpio &= ~LCD_MODE_WRITE;
};
/*
Отправить строку на экран с указанием позиции
на входе: in_u8X - позиция символа в строке
in_u8Y - номер строки
in_cChar - символ для установки
на выходе: *
*/
void lcd_write_str(uint8_t in_u8X, uint8_t in_u8Y, char* in_cChar)
{
lcd_set_pos(in_u8X, in_u8Y);
lcd_send_str(in_cChar);
};
/*
Установка курсора
на входе: in_u8X - позиция символа в строке
in_u8Y - номер строки
на выходе: *
*/
void lcd_set_pos(uint8_t in_u8X, uint8_t in_u8Y)
{
switch (in_u8Y) {
case 0:
send_command(in_u8X | LCD_SET_DDRAM_TO_ADDRESS);
break;
case 1:
send_command((LCD_2_LINE_OFFSET + in_u8X) | LCD_SET_DDRAM_TO_ADDRESS);
break;
}
};
/*
Отправка строки на экран
на входе: in_cChar - указатель на строку
на выходе: *
*/
void lcd_send_str(char* in_pszChar)
{
char* l_pszChar = in_pszChar;
while ((l_pszChar)[0])
lcd_send_char((l_pszChar++)[0]);
};
/*
Отправка символа на экран
на входе: in_cChar - символ
на выходе: *
*/
void lcd_send_char(char in_cChar)
{
lcd_gpio |= LCD_MODE_DATA;
send_half_byte(in_cChar >> 4);
send_half_byte(in_cChar);
};
/*
Очистить экран
на входе: *
на выходе: *
*/
void lcd_clear()
{
send_command(LCD_SET_CLEAR);
delay_micro(1530);
};
/*
Отправка байта на шину
на входе: in_u8Byte - байт с командой
на выходе: *
*/
void write_byte(uint8_t in_u8Byte)
{
uint8_t buf[1] = { lcd_gpio | in_u8Byte };
i2c_transmit(LCD_I2C_PERIPH, buf, 1, LCD_I2C_ADDR, I2C_GENSTOP_YES);
//delay_micro(39);
};
void i2c_transmit_one(const uint8_t b) {
LCD_I2C_PERIPH->CR2 = LCD_I2C_ADDR | I2C_CR2_START | I2C_CR2_AUTOEND | (1 << I2C_CR2_NBYTES_Pos);
}
/*
Отправка половины байта экрану
на входе: in_u8Byte - байт с командой
на выходе: *
*/
void send_half_byte(uint8_t in_u8Byte)
{
write_byte(LCD_MODE_E_SET | (in_u8Byte << 4));
write_byte(LCD_MODE_E_RESET);
};
/*
Отправка команды дисплею
на входе: in_u8Byte - байт с командой
на выходе: *
*/
void send_command(uint8_t in_u8Byte)
{
lcd_gpio &= ~LCD_MODE_DATA;
send_half_byte(in_u8Byte >> 4);
send_half_byte(in_u8Byte);
};
/*
Отправка половины байта экрану
на входе: in_u8Byte - байт с командой
на выходе: *
*/
void delay_micro(uint32_t in_u8micros)
{
/* FIXME */
in_u8micros *= (SystemCoreClock / 1000000) / 9;
while (in_u8micros--)
;
};

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/*
This is free and unencumbered software released into the public domain.
( https://github.com/KonstantinDM )
Anyone is free to copy, modify, publish, use, compile, sell, or
distribute this software, either in source code form or as a compiled
binary, for any purpose, commercial or non-commercial, and by any
means.
In jurisdictions that recognize copyright laws, the author or authors
of this software dedicate any and all copyright interest in the
software to the public domain. We make this dedication for the benefit
of the public at large and to the detriment of our heirs and
successors. We intend this dedication to be an overt act of
relinquishment in perpetuity of all present and future rights to this
software under copyright law.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
For more information, please refer to <http://unlicense.org>
*/
#ifndef _C_LCD1602_H_INCLUDED_
#define _C_LCD1602_H_INCLUDED_
#define LCD_I2C_PERIPH I2C1
#define LCD_I2C_ADDR 0x4e
/* 16 spaces you can concatenate to printf formats to make sure the entire LCD line is always cleared */
#define LCD_FILL " "" "" "" "
void lcd1602_init(); // Инициализация дисплея
void lcd_write_str(uint8_t in_u8X, uint8_t in_u8Y, char* in_cChar); // Отправить строку на экран с указанием позиции
void lcd_send_char(char in_cChar); // Отправить символ на экран
void lcd_send_str(char* in_cChar); // Отправить строку на экран
void lcd_set_pos(uint8_t in_u8X, uint8_t in_u8Y); // Установить позицию курсора
void lcd_clear(); // Очистить экран
/*
|P7|P6|P5|P4|P3|P2|P1|P0|
|B7|B6|B5|B4|LED|E|RW|RS|
*/
#define LCD_INITIALIZATION 0x03 // Инициализационный байт дисплея
#define LCD_MODE_COMMAND 0x00 // Флаг команды
#define LCD_MODE_DATA 0x01 // Флаг данных
#define LCD_MODE_LED 0x08 // флаг работы подсветки
#define LCD_MODE_WRITE 0x02 // Флаг записи
#define LCD_MODE_E_SET 0x04 // Флаг установки регистра Е
#define LCD_MODE_E_RESET 0xFB // Флаг сброса регистра Е
#define LCD_2_LINE_OFFSET 0x40 // Адрес второй строки дисплея
#define LCD_SET_CLEAR 0x01 // (1.53ms) Очистка дисплея с установкой курсора в начало первой строки
#define LCD_SET_CURSOR_TO_START 0x02 // (1.53ms) Установка курсора в начало первой строки
#define LCD_SET_SHIFT_AND_CHAR_DIRECTION 0x04 // (39mks) Установка направления вывода символов, разрешение сдвига экрана
#define LCD_CHAR_DIRECTION_LEFT_RIGHT 0x02 // Вывод символов справа-налево, декремент адресного указателя DDRAM/CGRAM памяти
#define LCD_CHAR_DIRECTION_RIGHT_LEFT 0x00 // Вывод символов слева-направо, инкремент адресного указателя DDRAM/CGRAM памяти
#define LCD_SHIFT_DISABLE 0x00 // Запрет сдвига экрана при выводе символов
#define LCD_SHIFT_ENABLE 0x01 // Разрешение сдвига экрана при выводе символов
#define LCD_SET_CURSOR_AND_POWE_MODE 0x08 // (39mks) Управление режимом питания дисплея и отображением курсора
#define LCD_DISPLAY_OFF 0x00 // Выключить экран дисплея, сегменты погашены, содержимое внутренней памяти сохраняется
#define LCD_DISPLAY_ON 0x04 // Включить экран дисплея, нормальный режим работы
#define LCD_CURSOR_OFF 0x00 // Отключить отображение курсора
#define LCD_CURSOR_ON 0x02 // Включить отображение курсора
#define LCD_CURSOR_BLINK_OFF 0x00 // Отключить функцию мигания курсора
#define LCD_CURSOR_BLINK_ON 0x01 // Включить функцию мигания курсора
#define LCD_SET_CURSOR_AND_DISPLAY_SHIFT 0x10 // (39mks) Команда сдвига курсора и экрана
#define LCD_CURSOR_SHIFT 0x00 // Выбрать курсор для сдвига
#define LCD_DISPLAY_AND_CURSOR_SHIFT 0x08 // Выбрать экран (вместе с курсором) для сдвига
#define LCD_LEFT_SHIFT 0x00 // Сдвиг влево (только курсор или весь экран, зависит от бита S/C)
#define LCD_RIGHT_SHIFT 0x04 // Сдвиг вправо (только курсор или весь экран, зависит от бита S/C)
#define LCD_SET_INTERFACE_LINES_FONT 0x20 // (39mks) Настройка интерфейса ввода/вывода данных, количества строк для вывода символов, размера шрифта
#define LCD_4BIT_INTERFACE 0x00 // Сдвиг вправо (только курсор или весь экран, зависит от бита S/C)
#define LCD_8BIT_INTERFACE 0x10 // 8-битный интерфейс ввода/вывода данных
#define LCD_ONE_LINE 0x00 // Использовать одну строку для вывода символов
#define LCD_TWO_LINE 0x08 // Задействовать 2 строки для вывода символов
#define LCD_5x8_FONT 0x00 // Размер шрифта 5×8 пикселей
#define LCD_5x11_FONT 0x04 // Размер шрифта 5×11 пикселей
#define LCD_SET_CGRAM_TO_ADDRESS 0x40 // (39mks) Запись адреса CGRAM памяти в адресный указатель
#define LCD_CGRAM_TO_ADDRESS_MASK 0x3F // Маска байта данных
#define LCD_SET_DDRAM_TO_ADDRESS 0x80 // (39mks) Запись адреса DDRAM памяти в адресный указатель
#define LCD_DDRAM_TO_ADDRESS_MASK 0x7F // Маска байта данных
#endif // _C_LCD1602_H_INCLUDED_

3
driver_fw/mac.c
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@ -1,3 +0,0 @@
#include "mac.h"
uint32_t device_mac = MAC_ADDR;

22
driver_fw/mac.h
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@ -1,22 +0,0 @@
#ifndef __MAC_H__
#define __MAC_H__
#include <unistd.h>
/* Device MAC address.
*
* 32 bits might seem a little short for a device MAC, but at 20 bus nodes the probablility of a collision is about 1 in
* 10 million. Check for yourself using the python code below.
*
* #!/usr/bin/env python3
* from operator import mul
* from functools import reduce
* m = 32
* n = 20
* print(reduce(mul, [2**m-i for i in range(n)]) / ((2**m)**n))
* # -> 0.9999999557621786
*/
extern uint32_t device_mac;
#endif /* __MAC_H__ */

361
driver_fw/main.c
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/* 8seg LED display driver firmware
* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "global.h"
#include "serial.h"
#include "i2c.h"
#include "lcd1602.h"
#include "mcp9801.h"
#include "ina226.h"
#include "mini-printf.h"
#include <8b10b.h>
/* Part number: STM32F030F4C6 */
volatile unsigned int comm_led_ctr, err_led_ctr;
volatile unsigned int sys_time_tick = 0;
volatile unsigned int sys_time_ms;
volatile unsigned int sys_time_s;
volatile unsigned int sys_flag_1Hz;
unsigned int frame_duration_us;
volatile uint8_t global_brightness; /* FIXME implement sending */
void trigger_error_led() {
err_led_ctr = STATUS_LED_DURATION_MS/TICK_MS;
}
void trigger_comm_led() {
comm_led_ctr = STATUS_LED_DURATION_MS/TICK_MS;
}
static volatile struct {
int current_symbol;
struct state_8b10b_enc st;
} txstate;
#define NO_SYMBOL (DECODER_RETURN_CODE_LAST + 1)
uint8_t random() {
static uint8_t x, a, b, c;
x++; //x is incremented every round and is not affected by any other variable
a = (a ^ c ^ x); //note the mix of addition and XOR
b = (b + a); //And the use of very few instructions
c = ((c + ((b >> 1) ^ a))); // the AES S-Box Operation ensures an even distributon of entropy
return c;
}
enum STATUS_LEDS {
STATUS_LED_COMMUNICATION = 1,
STATUS_LED_ERROR = 2,
STATUS_LED_LOAD = 4,
STATUS_LED_OPERATION = 8,
STATUS_LED_J5_GREEN = 16,
STATUS_LED_J5_YELLOW = 32,
STATUS_LED_J4_GREEN = 64,
STATUS_LED_J4_YELLOW = 128
};
static void set_status_leds(uint8_t val) {
/* Reset strobe. Will be set in systick handler */
GPIOA->BRR = 1<<4;
/* Workaround for *nasty* hardware behavior: If SPI data width is configured as 8 bit but DR is written as 16
* bit, SPI actually sends 16 clock cycles. Thus, we have to make sure the compiler emits a 8-bit write here.
* Thanks, TI! */
*((volatile uint8_t *)&(SPI1->DR)) = val ^ 0x0f; /* Invert LEDs connected to VCC instead of GND */
}
static int flipbits10(int in) {
return
(in&0x200)>>9 |
(in&0x100)>>7 |
(in&0x080)>>5 |
(in&0x040)>>3 |
(in&0x020)>>1 |
(in&0x010)<<1 |
(in&0x008)<<3 |
(in&0x004)<<5 |
(in&0x002)<<7 |
(in&0x001)<<9;
}
uint8_t spinner = 0; /* FIXME DEBUG */
int main(void) {
/* Startup code */
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR&RCC_CR_HSERDY));
RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk;
RCC->CFGR |= ((6-2)<<RCC_CFGR_PLLMUL_Pos) | RCC_CFGR_PLLSRC_HSE_PREDIV; /* PLL x6 -> 48.0MHz */
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR&RCC_CR_PLLRDY));
RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN;
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN | RCC_APB1ENR_PWREN | RCC_APB1ENR_I2C1EN;
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN| RCC_APB2ENR_DBGMCUEN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_SPI1EN;
SystemCoreClockUpdate();
SysTick_Config(SystemCoreClock/(1000/TICK_MS)); /* 10ms interval */
NVIC_EnableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn, 3<<5);
/* GPIO setup
*
* Note: since we have quite a bunch of pin constraints we can't actually use complementary outputs for the
* complementary MOSFET driver control signals (CTRL_A & CTRL_B). Instead, we use two totally separate output
* channels (1 & 4) and emulate the dead-time generator in software.
*/
GPIOA->MODER |=
(3<<GPIO_MODER_MODER0_Pos) /* PA0 - Vboot to ADC */
| (2<<GPIO_MODER_MODER1_Pos) /* PA1 - RS485 DE */
| (2<<GPIO_MODER_MODER2_Pos) /* PA2 - RS485 TX */
| (2<<GPIO_MODER_MODER3_Pos) /* PA3 - RS485 RX */
| (1<<GPIO_MODER_MODER4_Pos) /* PA4 - Strobe/Vin to ADC. CAUTION: This pin is dual-use */
| (2<<GPIO_MODER_MODER5_Pos) /* PA5 - SCK */
| (2<<GPIO_MODER_MODER6_Pos) /* PA6 - CTRL_A to TIM 3 ch 1 */
| (2<<GPIO_MODER_MODER7_Pos) /* PA7 - MOSI */
| (2<<GPIO_MODER_MODER9_Pos) /* PA9 - SCL */
| (2<<GPIO_MODER_MODER10_Pos);/* PA10 - SDA */
GPIOA->AFR[0] =
(1<<GPIO_AFRL_AFSEL1_Pos) /* PA1 */
| (1<<GPIO_AFRL_AFSEL2_Pos) /* PA2 */
| (1<<GPIO_AFRL_AFSEL3_Pos) /* PA3 */
| (1<<GPIO_AFRL_AFSEL6_Pos); /* PA6 */
GPIOA->AFR[1] =
(4<<GPIO_AFRH_AFSEL9_Pos) /* PA9 */
| (4<<GPIO_AFRH_AFSEL10_Pos);/* PA10 */
GPIOA->ODR = 0; /* Set PA4 ODR to 0 */
GPIOA->OTYPER |=
GPIO_OTYPER_OT_1
| GPIO_OTYPER_OT_2;
// FIXME lag 37.3us @ 720 Ohm / 16.0us @ 360 Ohm / 2.8us @ 88 Ohm
GPIOA->OSPEEDR |=
(3<<GPIO_OSPEEDR_OSPEEDR1_Pos)
| (3<<GPIO_OSPEEDR_OSPEEDR2_Pos);
GPIOB->MODER |=
(2<<GPIO_MODER_MODER1_Pos); /* PB1 - CTRL_B to TIM 3 ch 4 */
GPIOB->AFR[0] = (1<<GPIO_AFRL_AFSEL1_Pos); /* PB1 */
serial_init();
/* FIXME ADC config */
/* SPI config. SPI1 is used to control the shift register controlling the eight status LEDs. */
SPI1->CR2 = (7<<SPI_CR2_DS_Pos);
/* Baud rate PCLK/128 -> 375.0kHz */
SPI1->CR1 =
SPI_CR1_SSM
| SPI_CR1_SSI
| (6<<SPI_CR1_BR_Pos)
| SPI_CR1_MSTR;
SPI1->CR1 |= SPI_CR1_SPE;
/* I2C for LCD, temp sensor, current sensor */
i2c_config_filters(I2C1, I2C_AF_ENABLE, 0);
i2c_config_timing(I2C1, 0x2000090e); /* Magic value for 100kHz I2C @ 48MHz CLK. Fell out of STMCubeMX. I love
downloading 120MB of software to download another 100MB of software, only
this time over unsecured HTTP, to generate 3.5 bytes of configuration values
using a Java(TM) GUI. */
i2c_enable(I2C1);
lcd1602_init();
ina226_init(); /* Current/voltage monitor */
mcp9801_init(); /* MOSFET temperature. Placed between middle two low-side MOSFETs. */
/* TIM3 is used to generate the MOSFET driver control signals */
/* TIM3 running off 48MHz APB1 clk, T=20.833ns */
TIM3->CR1 = 0; /* Disable ARR preload (double-buffering) */
TIM3->PSC = 48-1; /* Prescaler 48 -> f=1MHz/T=1us */
TIM3->DIER = TIM_DIER_UIE; /* Enable update (overflow) interrupt */
/* Set both CCRs to 0xffff to ensure both bridge halves are turned off after we enable the timer. If we don't do
* this, we will cause a very low-ohm short circuit that at best will trigger our power supply's short-circuit or
* over-current protection right after power-on but at worst will detonate the mosfets. */
TIM3->CCR1 = 0xffff;
TIM3->CCR4 = 0xffff;
/* Configure output compare unit 1 to PWM mode 1, enable CCR1 preload */
TIM3->CCMR1 = 6<<TIM_CCMR1_OC1M_Pos | TIM_CCMR1_OC1PE;
/* Configure output compare unit 4 to PWM mode 1, enable CCR4 preload */
TIM3->CCMR2 = 6<<TIM_CCMR2_OC4M_Pos | TIM_CCMR2_OC4PE;
/* Confiugre CH1 to complementary outputs */
TIM3->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC4E | TIM_CCER_CC4P;
/* Enable MOE on next update event, i.e. on initial timer load. */
TIM3->BDTR = TIM_BDTR_MOE;
/* Enable timer */
TIM3->CR1 |= TIM_CR1_CEN;
/* Set f=1.25kHz/T=0.8ms */
TIM3->ARR = 800-1;
/* Initialize AC protocol state machine in TIM3 ISR with the AC protocol comma */
xfr_8b10b_encode_reset(&txstate.st);
txstate.current_symbol = flipbits10(xfr_8b10b_encode(&txstate.st, K28_1)) | 1<<10;
/* The timer is still stopped. Start it by manually triggering an update event. */
TIM3->EGR |= TIM_EGR_UG;
NVIC_EnableIRQ(TIM3_IRQn);
NVIC_SetPriority(TIM3_IRQn, 2<<4);
lcd_write_str(0, 0, "8seg driver");
lcd_write_str(0, 1, "initialized \xbc");
while (42) {
if (sys_flag_1Hz) { /* Update display every second */
sys_flag_1Hz = 0;
spinner = ~spinner;
char buf[17];
int temp = mcp9801_read_mdegC();
int deg = temp/1000;
int frac = (temp%1000)/100;
mini_snprintf(buf, sizeof(buf), "Temp: %d.%01d\xdf""C" LCD_FILL, deg, frac);
lcd_write_str(0, 0, buf);
mini_snprintf(buf, sizeof(buf), "I=%dmA U=%dmV" LCD_FILL, ina226_read_i()*INA226_I_LSB_uA/1000, ina226_read_v()*INA226_VB_LSB_uV/1000);
lcd_write_str(0, 1, buf);
}
}
}
#define BACKCHANNEL_INTERVAL 10
__attribute__((__noreturn__)) void __assert_func (const char *, int, const char *, const char *){
asm volatile ("bkpt");
while (1);
}
int hamming_weight(int i) {
int r = 0;
for (int j = 0; j < 32; j ++) {
if (i < 0) r ++;
i <<= 1;
}
return r;
}
void TIM3_IRQHandler() {
static int txpos = -1;
static unsigned int tx_start_tick = 0;
static uint8_t txbuf[3] = {0x05, 0x01, 0};
static int backchannel_counter = 0;
txbuf[2] = spinner;
TIM3->SR &= ~TIM_SR_UIF;
int sym = txstate.current_symbol;
int bit = sym&1;
sym >>= 1;
if (sym == 1) { /* last bit shifted out */
/* Insert the backchannel sync control symbol K.28.2 once every BACKCHANNEL_INTERVAL symbols independent from AC
* forward channel protocol framing. The backchannel sync control symbol is different from the AC protocol comma
* K.28.1. The backchannel sync control symbol is not a comma, so the 8b10b receiver cannot lock on it. The only
* practical implication of this is that after powerup or other loss of sync, the receiver will only lock on the
* backchannel sync once the first AC forward-channel protocol frame has been begun. Since all backchannel comm
* is triggered by the driver anyway this should not be noticeable in practice.
*/
backchannel_counter++;
if (backchannel_counter == BACKCHANNEL_INTERVAL) {
backchannel_counter = 0;
sym = xfr_8b10b_encode(&txstate.st, -K28_2); /* TODO factor out backchannel comma into constant */
} else {
if (txpos == -1)
sym = xfr_8b10b_encode(&txstate.st, -K28_1); /* TODO factor out comma into constant */
else
sym = xfr_8b10b_encode(&txstate.st, txbuf[txpos]);
txpos++;
if (txpos >= sizeof(txbuf)/sizeof(txbuf[0])) {
frame_duration_us = (sys_time_tick - tx_start_tick) * 10 * 1000;
tx_start_tick = sys_time_tick;
txpos = -1;
}
}
/* Append one '1' bit as an end-of-symbol marker for this state machine. This bit is not actually transmitted. */
sym = flipbits10(sym) | 1<<10;
}
txstate.current_symbol = sym;
/* FIXME factor out into header, or even make configurable */
#define DEAD_TIME 1
/* Set both CCRs to values for opposing polarities. The dead time is always inserted at the beginning of the timer
* cycle due to the way the capture/compare unit PWM machinery works. By setting the CCR to 0xffff we make sure the
* output is never turned on, since 0xffff is larger than the ARR/counter top value.
*/
TIM3->CCR1 = bit ? 0xffff : DEAD_TIME;
TIM3->CCR4 = bit ? DEAD_TIME : 0xffff;
}
void NMI_Handler(void) {
}
void HardFault_Handler(void) __attribute__((naked));
void HardFault_Handler() {
asm volatile ("bkpt");
}
void SVC_Handler(void) {
}
void PendSV_Handler(void) {
}
void SysTick_Handler(void) {
sys_time_tick++;
sys_time_ms += TICK_MS;
if (sys_time_ms++ == 1000) {
sys_time_ms = 0;
sys_time_s++;
sys_flag_1Hz = 1;
}
/* This is a hack. We could use the SPI interrupt here if that didn't fire at the start instead of end of transmission.... -.- */
if (sys_time_tick&1) {
uint8_t val = (sys_time_ms >= 300) ? STATUS_LED_OPERATION : 0;
if (comm_led_ctr) {
comm_led_ctr--;
val |= STATUS_LED_COMMUNICATION;
}
if (err_led_ctr) {
err_led_ctr--;
val |= STATUS_LED_ERROR;
}
set_status_leds(val);
} else {
/* Reset strobe for the status LED shift register. Reset in set_status_leds. */
GPIOA->BSRR = 1<<4;
}
}
void _init(void) {
}
void BusFault_Handler(void) __attribute__((naked));
void BusFault_Handler() {
asm volatile ("bkpt");
}

42
driver_fw/mcp9801.c
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/* 8seg LED display driver firmware
* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "global.h"
#include "i2c.h"
#include "mcp9801.h"
void mcp9801_init()
{
uint8_t config = MCP9801_ONESHOT_OFF | MCP9801_RES_12BIT | MCP9801_FAULT_QUEUE_1 | MCP9801_ALERT_LOW | \
MCP9801_MODE_COMP | MCP9801_SHUTDOWN_OFF;
uint8_t buf[2] = { MCP9801_REG_CONFIG, config };
i2c_transmit(MCP9801_I2C_PERIPH, buf, sizeof(buf), MCP9801_I2C_ADDR, I2C_GENSTOP_YES);
/* Address device here */
uint8_t buf2[1] = { MCP9801_REG_TEMP };
i2c_transmit(MCP9801_I2C_PERIPH, buf2, sizeof(buf2), MCP9801_I2C_ADDR, I2C_GENSTOP_NO);
}
int32_t mcp9801_read_mdegC()
{
uint8_t rx[2];
i2c_receive(MCP9801_I2C_PERIPH, rx, sizeof(rx), MCP9801_I2C_ADDR);
/* Fixup endianness, sign-extend */
int32_t temp = (int16_t)((rx[0]<<8) | rx[1]);
return (temp * 1000) /256;
}

66
driver_fw/mcp9801.h
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/* 8seg LED display driver firmware
* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __MCP9801_H__
#define __MCP9801_H__
#define MCP9801_I2C_ADDR 0x90
#define MCP9801_I2C_PERIPH I2C1
#include <stdint.h>
enum mcp9801_regmap {
MCP9801_REG_TEMP = 0,
MCP9801_REG_CONFIG = 1,
MCP9801_REG_HYST = 2,
MCP9801_REG_LIMIT = 3
};
enum mcp9801_config {
MCP9801_ONESHOT_ON = 1<<7,
MCP9801_ONESHOT_OFF = 0<<7,
MCP9801_ONESHOT_Msk = 1<<7,
MCP9801_RES_9BIT = 0<<5,
MCP9801_RES_10BIT = 1<<5,
MCP9801_RES_11BIT = 2<<5,
MCP9801_RES_12BIT = 3<<5,
MCP9801_RES_Msk = 3<<5,
MCP9801_FAULT_QUEUE_1 = 0<<3,
MCP9801_FAULT_QUEUE_2 = 1<<3,
MCP9801_FAULT_QUEUE_4 = 2<<3,
MCP9801_FAULT_QUEUE_6 = 3<<3,
MCP9801_FAULT_QUEUE_Msk = 3<<3,
MCP9801_ALERT_HIGH = 1<<2,
MCP9801_ALERT_LOW = 0<<2,
MCP9801_ALERT_Msk = 1<<2,
MCP9801_MODE_INT = 1<<1,
MCP9801_MODE_COMP = 0<<1,
MCP9801_MODE_Msk = 1<<1,
MCP9801_SHUTDOWN_ON = 1<<0,
MCP9801_SHUTDOWN_OFF = 0<<0,
MCP9801_SHUTDOWN_Msk = 1<<0,
};
void mcp9801_init(void);
int32_t mcp9801_read_mdegC(void);
#endif /* __MCP9801_H__ */

2
driver_fw/memory_map.ldi Normal file
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@ -0,0 +1,2 @@
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 36K
FLASH (rx ): ORIGIN = 0x08000000, LENGTH = 128K

208
driver_fw/mini-printf.c
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@ -1,208 +0,0 @@
/*
* The Minimal snprintf() implementation
*
* Copyright (c) 2013,2014 Michal Ludvig <michal@logix.cz>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the auhor nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ----
*
* This is a minimal snprintf() implementation optimised
* for embedded systems with a very limited program memory.
* mini_snprintf() doesn't support _all_ the formatting
* the glibc does but on the other hand is a lot smaller.
* Here are some numbers from my STM32 project (.bin file size):
* no snprintf(): 10768 bytes
* mini snprintf(): 11420 bytes (+ 652 bytes)
* glibc snprintf(): 34860 bytes (+24092 bytes)
* Wasting nearly 24kB of memory just for snprintf() on
* a chip with 32kB flash is crazy. Use mini_snprintf() instead.
*
*/
#include "mini-printf.h"
static unsigned int
mini_strlen(const char *s)
{
unsigned int len = 0;
while (s[len] != '\0') len++;
return len;
}
static unsigned int
mini_itoa(int value, unsigned int radix, unsigned int uppercase, unsigned int unsig,
char *buffer, unsigned int zero_pad)
{
char *pbuffer = buffer;
int negative = 0;
unsigned int i, len;
/* No support for unusual radixes. */
if (radix > 16)
return 0;
if (value < 0 && !unsig) {
negative = 1;
value = -value;
}
/* This builds the string back to front ... */
do {
int digit = value % radix;
*(pbuffer++) = (digit < 10 ? '0' + digit : (uppercase ? 'A' : 'a') + digit - 10);
value /= radix;
} while (value > 0);
for (i = (pbuffer - buffer); i < zero_pad; i++)
*(pbuffer++) = '0';
if (negative)
*(pbuffer++) = '-';
*(pbuffer) = '\0';
/* ... now we reverse it (could do it recursively but will
* conserve the stack space) */
len = (pbuffer - buffer);
for (i = 0; i < len / 2; i++) {
char j = buffer[i];
buffer[i] = buffer[len-i-1];
buffer[len-i-1] = j;
}
return len;
}
struct mini_buff {
char *buffer, *pbuffer;
unsigned int buffer_len;
};
static int
_putc(int ch, struct mini_buff *b)
{
if ((unsigned int)((b->pbuffer - b->buffer) + 1) >= b->buffer_len)
return 0;
*(b->pbuffer++) = ch;
*(b->pbuffer) = '\0';
return 1;
}
static int
_puts(char *s, unsigned int len, struct mini_buff *b)
{
unsigned int i;
if (b->buffer_len - (b->pbuffer - b->buffer) - 1 < len)
len = b->buffer_len - (b->pbuffer - b->buffer) - 1;
/* Copy to buffer */
for (i = 0; i < len; i++)
*(b->pbuffer++) = s[i];
*(b->pbuffer) = '\0';
return len;
}
int
mini_vsnprintf(char *buffer, unsigned int buffer_len, const char *fmt, va_list va)
{
struct mini_buff b;
char bf[24];
char ch;
b.buffer = buffer;
b.pbuffer = buffer;
b.buffer_len = buffer_len;
while ((ch=*(fmt++))) {
if ((unsigned int)((b.pbuffer - b.buffer) + 1) >= b.buffer_len)
break;
if (ch!='%')
_putc(ch, &b);
else {
char zero_pad = 0;
char *ptr;
unsigned int len;
ch=*(fmt++);
/* Zero padding requested */
if (ch=='0') {
ch=*(fmt++);
if (ch == '\0')
goto end;
if (ch >= '0' && ch <= '9')
zero_pad = ch - '0';
ch=*(fmt++);
}
switch (ch) {
case 0:
goto end;
case 'u':
case 'd':
len = mini_itoa(va_arg(va, unsigned int), 10, 0, (ch=='u'), bf, zero_pad);
_puts(bf, len, &b);
break;
case 'x':
case 'X':
len = mini_itoa(va_arg(va, unsigned int), 16, (ch=='X'), 1, bf, zero_pad);
_puts(bf, len, &b);
break;
case 'c' :
_putc((char)(va_arg(va, int)), &b);
break;
case 's' :
ptr = va_arg(va, char*);
_puts(ptr, mini_strlen(ptr), &b);
break;
default:
_putc(ch, &b);
break;
}
}
}
end:
return b.pbuffer - b.buffer;
}
int
mini_snprintf(char* buffer, unsigned int buffer_len, const char *fmt, ...)
{
int ret;
va_list va;
va_start(va, fmt);
ret = mini_vsnprintf(buffer, buffer_len, fmt, va);
va_end(va);
return ret;
}

50
driver_fw/mini-printf.h
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@ -1,50 +0,0 @@
/*
* The Minimal snprintf() implementation
*
* Copyright (c) 2013 Michal Ludvig <michal@logix.cz>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the auhor nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MINI_PRINTF__
#define __MINI_PRINTF__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdarg.h>
int mini_vsnprintf(char* buffer, unsigned int buffer_len, const char *fmt, va_list va);
int mini_snprintf(char* buffer, unsigned int buffer_len, const char *fmt, ...);
#ifdef __cplusplus
}
#endif
#define vsnprintf mini_vsnprintf
#define snprintf mini_snprintf
#endif

11
driver_fw/openocd.cfg
View file

@ -1,14 +1,9 @@
telnet_port 4444
gdb_port 3333
tcl_port disabled
telnet_port disabled
source [find interface/stlink.cfg]
hla_serial "54FF6B064987495026541187"
transport select hla_swd
source [find target/stm32f0x.cfg]
#adapter_khz 10000
source [find target/stm32g0x.cfg]
init
arm semihosting enable
#flash bank sysflash.alias stm32f0x 0x00000000 0 0 0 $_TARGETNAME

233
driver_fw/serial.c
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@ -1,233 +0,0 @@
/* 8seg LED display driver firmware
* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "serial.h"
#include "mac.h"
unsigned int uart_overruns = 0;
unsigned int invalid_frames = 0;
static union tx_buf_union tx_buf;
volatile union rx_buf_union rx_buf;
void serial_init() {
USART1->CR1 = /* 8-bit -> M1, M0 clear */
/* RTOIE clear */
(8 << USART_CR1_DEAT_Pos) /* 8 sample cycles/1 bit DE assertion time */
| (8 << USART_CR1_DEDT_Pos) /* 8 sample cycles/1 bit DE assertion time */
/* OVER8 clear. Use default 16x oversampling */
/* CMIF clear */
| USART_CR1_MME
/* WAKE clear */
/* PCE, PS clear */
| USART_CR1_RXNEIE /* Enable receive interrupt */
/* other interrupts clear */
| USART_CR1_TE
| USART_CR1_RE;
/* Invert TX and DE to accomodate the level shifters */
USART1->CR2 = USART_CR2_TXINV;
USART1->CR3 = USART_CR3_DEM | USART_CR3_DEP; /* enable RS485 DE (output on RTS) */
/* Set divider for 9600 baud rate @48MHz system clock. */
int usartdiv = 5000;
USART1->BRR = usartdiv;
/* And... go! */
USART1->CR1 |= USART_CR1_UE;
/* Enable receive interrupt */
NVIC_EnableIRQ(USART1_IRQn);
NVIC_SetPriority(USART1_IRQn, 1);
}
void tx_char(uint8_t c) {
while (!(USART1->ISR & USART_ISR_TC));
USART1->TDR = c;
}
void send_frame_formatted(uint8_t *buf, int len) {
uint8_t *p=buf, *q=buf, *end=buf+len;
do {
while (*q && q!=end)
q++;
tx_char(q-p+1);
while (*p && p!=end)
tx_char(*p++);
p++, q++;
} while (p < end);
tx_char('\0');
}
void send_status_reply(void) {
tx_buf.desc_reply.firmware_version = FIRMWARE_VERSION;
tx_buf.desc_reply.hardware_version = HARDWARE_VERSION;
tx_buf.desc_reply.pad[0] = tx_buf.desc_reply.pad[1] = 0;
tx_buf.desc_reply.uptime_s = sys_time_s;
//tx_buf.desc_reply.vcc_mv = adc_vcc_mv;
//tx_buf.desc_reply.temp_celsius = adc_temp_celsius;
tx_buf.desc_reply.global_brightness = global_brightness;
tx_buf.desc_reply.framerate_millifps = frame_duration_us > 0 ? 1000000000 / frame_duration_us : 0;
tx_buf.desc_reply.uart_overruns = uart_overruns;
tx_buf.desc_reply.invalid_frames = invalid_frames;
send_frame_formatted(tx_buf.byte_data, sizeof(tx_buf.desc_reply));
}
/* This is the higher-level protocol handler for the serial protocol. It gets passed the number of data bytes in this
* frame (which may be zero) and returns a pointer to the buffer where the next frame should be stored.
*/
volatile uint8_t *packet_received(int len) {
static enum {
PROT_ADDRESSED = 0,
PROT_IGNORE = 2,
} protocol_state = PROT_IGNORE;
/* Use mac frames as delimiters to synchronize this protocol layer */
trigger_comm_led();
if (len == 0) { /* Discovery packet */
if (sys_time_tick < 100) { /* Only respond during the first 100ms after boot */
send_frame_formatted((uint8_t*)&device_mac, sizeof(device_mac));
}
} else if (len == 1) { /* Command packet */
if (protocol_state == PROT_ADDRESSED) {
switch (rx_buf.byte_data[0]) {
case 0x01:
send_status_reply();
break;
}
} else {
invalid_frames++;
trigger_error_led();
}
protocol_state = PROT_IGNORE;
} else if (len == 4) { /* Address packet */
if (rx_buf.mac_data == device_mac) { /* we are addressed */
protocol_state = PROT_ADDRESSED; /* start listening for frame buffer data */
} else { /* we are not addressed */
protocol_state = PROT_IGNORE; /* ignore packet */
}
} else if (len == sizeof(rx_buf.set_fb_rq)/2) {
if (protocol_state == PROT_ADDRESSED) { /* First of two half-framebuffer data frames */
/* FIXME */
/* Go to "hang mode" until next zero-length packet. */
protocol_state = PROT_IGNORE;
}
} else {
/* FIXME An invalid packet has been received. What should we do? */
invalid_frames++;
trigger_error_led();
protocol_state = PROT_IGNORE; /* go into "hang mode" until next zero-length packet */
}
/* By default, return rx_buf.byte_data . This means if an invalid protocol state is reached ("hang mode"), the next
* frame is still written to rx_buf. This is not a problem since whatever garbage is written at that point will be
* overwritten before the next buffer transfer. */
return rx_buf.byte_data;
}
void USART1_IRQHandler(void) {
/* Since a large amount of data will be shoved down this UART interface we need a more reliable and more efficient
* way of framing than just waiting between transmissions.
*
* This code uses "Consistent Overhead Byte Stuffing" (COBS). For details, see its Wikipedia page[0] or the proper
* scientific paper[1] published on it. Roughly, it works like this:
*
* * A frame is at most 254 bytes in length.
* * The null byte 0x00 acts as a frame delimiter. There is no null bytes inside frames.
* * Every frame starts with an "overhead" byte indicating the number of non-null payload bytes until the next null
* byte in the payload, **plus one**. This means this byte can never be zero.
* * Every null byte in the payload is replaced by *its* distance to *its* next null byte as above.
*
* This means, at any point the receiver can efficiently be synchronized on the next frame boundary by simply
* waiting for a null byte. After that, only a simple state machine is necessary to strip the overhead byte and a
* counter to then count skip intervals.
*
* Here is Wikipedia's table of example values:
*
* Unencoded data Encoded with COBS
* 00 01 01 00
* 00 00 01 01 01 00
* 11 22 00 33 03 11 22 02 33 00
* 11 22 33 44 05 11 22 33 44 00
* 11 00 00 00 02 11 01 01 01 00
* 01 02 ...FE FF 01 02 ...FE 00
*
* [0] https://en.wikipedia.org/wiki/Consistent_Overhead_Byte_Stuffing
* [1] Cheshire, Stuart; Baker, Mary (1999). "Consistent Overhead Byte Stuffing"
* IEEE/ACM Transactions on Networking. doi:10.1109/90.769765
* http://www.stuartcheshire.org/papers/COBSforToN.pdf
*/
/* This pointer stores where we write data. The higher-level protocol logic decides on a frame-by-frame-basis where
* the next frame's data will be stored. */
static volatile uint8_t *writep = rx_buf.byte_data;
/* Index inside the current frame payload */
static int rxpos = 0;
/* COBS state machine. This implementation might be a little too complicated, but it works well enough and I find it
* reasonably easy to understand. */
static enum {
COBS_WAIT_SYNC = 0, /* Synchronize with frame */
COBS_WAIT_START = 1, /* Await overhead byte */
COBS_RUNNING = 2 /* Process payload */
} cobs_state = 0;
/* COBS skip counter. During payload processing this contains the remaining non-null payload bytes */
static int cobs_count = 0;
if (USART1->ISR & USART_ISR_ORE) { /* Overrun handling */
uart_overruns++;
trigger_error_led();
/* Reset and re-synchronize. Retry next frame. */
rxpos = 0;
cobs_state = COBS_WAIT_SYNC;
/* Clear interrupt flag */
USART1->ICR = USART_ICR_ORECF;
} else { /* Data received */
uint8_t data = USART1->RDR; /* This automatically acknowledges the IRQ */
if (data == 0x00) { /* End-of-packet */
/* Process higher protocol layers on this packet. */
writep = packet_received(rxpos);
/* Reset for next packet. */
cobs_state = COBS_WAIT_START;
rxpos = 0;
} else { /* non-null byte */
if (cobs_state == COBS_WAIT_SYNC) { /* Wait for null byte */
/* ignore data */
} else if (cobs_state == COBS_WAIT_START) { /* Overhead byte */
cobs_count = data;
cobs_state = COBS_RUNNING;
} else { /* Payload byte */
if (--cobs_count == 0) { /* Skip byte */
cobs_count = data;
data = 0;
}
/* Write processed payload byte to current receive buffer */
writep[rxpos++] = data;
}
}
}
}

62
driver_fw/serial.h
View file

@ -1,62 +0,0 @@
/* Megumin LED display firmware
* Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __SERIAL_H__
#define __SERIAL_H__
#include "global.h"
/* High-level stuff */
void serial_init(void);
void send_status_reply(void);
/* Internal low-level stuff */
void tx_char(uint8_t c);
void send_frame_formatted(uint8_t *buf, int len);
volatile uint8_t *packet_received(int len);
/* Error counters for debugging */
extern unsigned int uart_overruns;
extern unsigned int invalid_frames;
union tx_buf_union {
struct __attribute__((packed)) {
uint8_t firmware_version,
hardware_version,
pad[2];
uint32_t uptime_s,
framerate_millifps,
uart_overruns,
invalid_frames;
int16_t vin_mv,
v3v3_mv,
iload_ma,
temp_celsius;
uint8_t global_brightness;
} desc_reply;
uint8_t byte_data[0];
};
union rx_buf_union {
struct __attribute__((packed)) { uint8_t fb[32]; uint8_t end[0]; } set_fb_rq;
struct __attribute__((packed)) { uint8_t brightness; uint8_t end[0]; } set_global_brightness;
uint8_t byte_data[0];
uint32_t mac_data;
};
extern volatile union rx_buf_union rx_buf;
#endif/*__SERIAL_H__*/

252
driver_fw/src/main.c Normal file
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@ -0,0 +1,252 @@
#include <global.h>
#include <string.h>
volatile uint64_t sys_time_us;
uint32_t read_fuse_monitor(void);
void set_rj45_leds(uint32_t leds);
void set_status_leds(uint32_t leds);
int main(void) {
/* Configure clocks for 168 MHz system clock.
*
* HSE @ 8 MHz --[PLL x16 /2]--> PLL "R" clock @ 64 MHz
*/
/* Enable peripherals */
RCC->APBENR1 |= RCC_APBENR1_PWREN;
/* Enable High-speed external crystal oscillator. The board has an 8 MHz crystal. */
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY)) {
/* wait for HSE osc to stabilize. */
}
/* Increase flash wait states to 5 required for operation above 136 MHz */
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (2<<FLASH_ACR_LATENCY_Pos);
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (2<<FLASH_ACR_LATENCY_Pos)) {
/* wait for flash controller to acknowledge change. */
}
/* Configure PLL with multiplier 16, divisor 2 for "R" output, and enable "R" (sysclk) output */
RCC->PLLCFGR = (16<<RCC_PLLCFGR_PLLN_Pos) | (3<<RCC_PLLCFGR_PLLSRC_Pos) | (1<<RCC_PLLCFGR_PLLR_Pos) | RCC_PLLCFGR_PLLREN;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) {
/* wait for PLL to stabilize. */
}
/* Switch SYSCLK to PLL source. */
RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != (2<<RCC_CFGR_SWS_Pos)) {
/* wait for RCC to switch over. */
}
RCC->AHBENR |= RCC_AHBENR_DMA1EN;
RCC->APBENR1 |= RCC_APBENR1_USART3EN | RCC_APBENR1_I2C1EN;
RCC->APBENR2 |= RCC_APBENR2_USART1EN | RCC_APBENR2_TIM1EN;
RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | RCC_IOPENR_GPIOCEN | RCC_IOPENR_GPIODEN;
/* GPIOA:
* A0: MON_H
* A1: MON_FAULT_CURRENT
* A2: MON_L
* A3: (testpoint)
* A4: VIN_MON
* A5: (testpoint)
* A6: RJ45 LED 2
* A7: Pulse RX
* A8: Fuse monitor 6
* A9: RS485 TX
* A10: RS485 RX
* A11: Fuse monitor 1
* A12: RS485 DE
* A13: SWDIO
* A14: SWCLK
* A15: Fuse monitor 4
*/
GPIOA->MODER =
ANALOG(0) | ANALOG(1) | ANALOG(2) | ANALOG(4) |
IN(3) | IN(5) |
OUT(6) |
ANALOG(7) |
IN(8) | IN(11) | IN(15) |
AF(9) | AF(10) | AF(12) |
AF(13) | AF(14);
GPIOA->AFR[1] = AFRH(9, 1) | AFRH(10, 1) | AFRH(12, 1) | AFRH(13, 0) | AFRH(14, 0);
GPIOA->OSPEEDR = (3<<(2*9)) | (3<<(2*12)) | (3<<(2*13));
/* GPIOB:
* B0: Driver A low (TIM1_CH2N)
* B1: Driver B low (TIM1_CH3N)
* B2: RJ45 LED 1
* B3: Driver A high (TIM1_CH2)
* B4: V_ISO_SENSE
* B5: (testpoint)
* B6: SCL
* B7: SDA
* B8: DBG_TX
* B9: DBG_RX
* B10: LED 3 "On"
* B11: LED 5 "RS458 Ping"
* B12: LED 1 "Overheating"
* B13: LED 6 "Control Error"
* B14: LED 4 "Input Error"
* B15: LED 2 "Output Error"
*/
GPIOB->MODER =
AF(0) | AF(1) | AF(3) |
OUT(2) |
IN(4) |
IN(5) |
AF(6) | AF(7) |
AF(8) | AF(9) |
OUT(10) | OUT(11) | OUT(12) | OUT(13) | OUT(14) | OUT(15);
GPIOB->AFR[0] = AFRL(0, 2) | AFRL(1, 2) | AFRL(3, 1) | AFRL(6, 6) | AFRL(7, 6);
GPIOB->AFR[1] = AFRH(8, 4) | AFRH(9, 4);
/* GPIOC:
* C0-C3: (testpoint)
* C4: RJ45 LED 4
* C5: RJ45 LED 3
* C6: Fuse monitor 7
* C7: Fuse monitor 2
* C8: Fuse monitor 5
* C9: (testpoint)
* C10: Driver B high
* C11-C15: (testpoint)
*/
GPIOC->MODER =
IN(0) | IN(1) | IN(2) | IN(3) | IN(9) | IN(11) | IN(12) | IN(13) | IN(14) | IN(15) |
OUT(4) | OUT(5) |
IN(6) | IN(7) | IN(8) |
AF(10);
GPIOC->AFR[1] = AFRH(10, 2);
/* GPIOD:
* D0-D6: (testpoint)
* D8: Fuse monitor 3
* D9: Fuse monitor 0
*/
GPIOD->MODER = IN(0) | IN(1) | IN(2) | IN(3) | IN(4) | IN(5) | IN(6) |
IN(8) | IN(9);
TIM1->CCMR1 = (6<<TIM_CCMR1_OC2M_Pos);
TIM1->CCMR2 = (6<<TIM_CCMR2_OC3M_Pos);
TIM1->CCER = TIM_CCER_CC2E | TIM_CCER_CC2NE | TIM_CCER_CC3E | TIM_CCER_CC3NE;
TIM1->BDTR = TIM_BDTR_MOE | (32<<TIM_BDTR_DTG_Pos);
TIM1->PSC = 0;
TIM1->ARR = 256;
TIM1->CR1 |= TIM_CR1_CEN;
int i = 0;
int j = 0;
while (23) {
i++;
j++;
i %= 6;
j %= 4;
delay_us(100000);
set_rj45_leds(1 << j);
set_status_leds(1 << i);
}
}
uint32_t read_fuse_monitor() {
uint32_t idr_a = GPIOA->IDR;
uint32_t idr_c = GPIOC->IDR;
uint32_t idr_d = GPIOD->IDR;
int fm0 = !!(idr_d & (1<<9));
int fm1 = !!(idr_a & (1<<11));
int fm2 = !!(idr_c & (1<<7));
int fm3 = !!(idr_d & (1<<8));
int fm4 = !!(idr_a & (1<<15));
int fm5 = !!(idr_c & (1<<8));
int fm6 = !!(idr_a & (1<<8));
int fm7 = !!(idr_c & (1<<6));
return (fm0<<0) | (fm1<<1) | (fm2<<2) | (fm3<<3) | (fm4<<4) | (fm5<<5) | (fm6<<6) | (fm7<<7);
}
void set_rj45_leds(uint32_t leds) {
leds = ~leds;
if (leds&1) {
GPIOB->BSRR = (1<<2);
} else {
GPIOB->BSRR = (1<<2)<<16;
}
if (leds&2) {
GPIOA->BSRR = (1<<6);
} else {
GPIOA->BSRR = (1<<6)<<16;
}
if (leds&4) {
GPIOC->BSRR = (1<<5);
} else {
GPIOC->BSRR = (1<<5)<<16;
}
if (leds&8) {
GPIOC->BSRR = (1<<4);
} else {
GPIOC->BSRR = (1<<4)<<16;
}
}
void set_status_leds(uint32_t leds) {
GPIOB->BSRR = ((0x3f<<10)<<16) | (((~leds)&0x3f)<<10);
}
void SysTick_Handler() {
sys_time_us += SYSTICK_INTERVAL_US;
}
void HardFault_Handler() {
asm volatile ("bkpt");
}
void delay_us(int duration_us) {
while (duration_us--) {
for (int i=0; i<3; i++) {
asm volatile ("nop");
}
}
}
void *memcpy(void *restrict dest, const void *restrict src, size_t n)
{
unsigned char *d = dest;
const unsigned char *s = src;
for (; n; n--) {
*d++ = *s++;
}
return dest;
}
void *memmove(void *dest, const void *src, size_t n)
{
return memcpy(dest, src, n);
}
void *memset(void *dest, int c, size_t n)
{
unsigned char *d = dest;
while (n--) {
*d++ = c;
}
return dest;
}
size_t strlen(const char *s)
{
const char *start = s;
while (*s) {
s++;
}
return s - start;
}
void __libc_init_array (void) __attribute__((weak));
void __libc_init_array () {
}

282
driver_fw/startup.s Normal file
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@ -0,0 +1,282 @@
/**
******************************************************************************
* @file startup_stm32g070xx.s
* @author MCD Application Team
* @brief STM32G070xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0+ processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2018-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0plus
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application s entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window WatchDog */
.word 0 /* reserved */
.word RTC_TAMP_IRQHandler /* RTC through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
.word 0 /* reserved */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
.word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */
.word ADC1_IRQHandler /* ADC1 */
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word 0 /* reserved */
.word TIM3_IRQHandler /* TIM3 */
.word TIM6_IRQHandler /* TIM6 */
.word TIM7_IRQHandler /* TIM7 */
.word TIM14_IRQHandler /* TIM14 */
.word TIM15_IRQHandler /* TIM15 */
.word TIM16_IRQHandler /* TIM16 */
.word TIM17_IRQHandler /* TIM17 */
.word I2C1_IRQHandler /* I2C1 */
.word I2C2_IRQHandler /* I2C2 */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_4_IRQHandler /* USART3, USART4 */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak RTC_TAMP_IRQHandler
.thumb_set RTC_TAMP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_1_IRQHandler
.thumb_set EXTI0_1_IRQHandler,Default_Handler
.weak EXTI2_3_IRQHandler
.thumb_set EXTI2_3_IRQHandler,Default_Handler
.weak EXTI4_15_IRQHandler
.thumb_set EXTI4_15_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
.thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_4_IRQHandler
.thumb_set USART3_4_IRQHandler,Default_Handler

273
driver_fw/startup_stm32f030x6.s
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@ -1,273 +0,0 @@
/**
******************************************************************************
* @file startup_stm32f030x6.s
* copied from: STM32Cube/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc
* @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief STM32F030x4/STM32F030x6 devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
// bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window WatchDog */
.word 0 /* Reserved */
.word RTC_IRQHandler /* RTC through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
.word 0 /* Reserved */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
.word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
.word ADC1_IRQHandler /* ADC1 */
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word 0 /* Reserved */
.word TIM3_IRQHandler /* TIM3 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word TIM14_IRQHandler /* TIM14 */
.word 0 /* Reserved */
.word TIM16_IRQHandler /* TIM16 */
.word TIM17_IRQHandler /* TIM17 */
.word I2C1_IRQHandler /* I2C1 */
.word 0 /* Reserved */
.word SPI1_IRQHandler /* SPI1 */
.word 0 /* Reserved */
.word USART1_IRQHandler /* USART1 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_1_IRQHandler
.thumb_set EXTI0_1_IRQHandler,Default_Handler
.weak EXTI2_3_IRQHandler
.thumb_set EXTI2_3_IRQHandler,Default_Handler
.weak EXTI4_15_IRQHandler
.thumb_set EXTI4_15_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_IRQHandler
.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1
driver_fw/stm32_buildinfo.defines Normal file
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@ -0,0 +1 @@
STM32G070xx

136
driver_fw/stm32_flash.ld
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@ -1,136 +0,0 @@
ENTRY(Reset_Handler)
MEMORY {
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 0x3C00
CONFIGFLASH (rw): ORIGIN = 0x08003C00, LENGTH = 0x400
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 4K
}
/* highest address of the user mode stack */
_estack = 0x20001000;
SECTIONS {
/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
.isr_vector : {
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* the program code is stored in the .text section, which goes to Flash */
.text : {
. = ALIGN(4);
*(.text) /* normal code */
*(.text.*) /* -ffunction-sections code */
*(.rodata) /* read-only data (constants) */
*(.rodata*) /* -fdata-sections read only data */
*(.glue_7) /* TBD - needed ? */
*(.glue_7t) /* TBD - needed ? */
*(.source_tarball)
/* Necessary KEEP sections (see http://sourceware.org/ml/newlib/2005/msg00255.html) */
KEEP (*(.init))
KEEP (*(.fini))
KEEP (*(.source_tarball))
. = ALIGN(4);
_etext = .;
/* This is used by the startup in order to initialize the .data section */
_sidata = _etext;
} >FLASH
/*
.configflash : {
. = ALIGN(0x400);
*(.configdata)
_econfig = .;
} >FLASH
*/
/* This is the initialized data section
The program executes knowing that the data is in the RAM
but the loader puts the initial values in the FLASH (inidata).
It is one task of the startup to copy the initial values from FLASH to RAM. */
.data : AT ( _sidata ) {
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
_data = . ;
*(.data)
*(.data.*)
*(.RAMtext)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
/* This is the uninitialized data section */
.bss : {
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
_bss = .;
*(.bss)
*(.bss.*) /* patched by elias - allows the use of -fdata-sections */
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
} >RAM
PROVIDE ( end = _ebss);
PROVIDE (_end = _ebss);
__exidx_start = .;
__exidx_end = .;
/* after that it's only debugging information. */
/* remove the debugging information from the standard libraries */
/* /DISCARD/ : {
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}*/
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

302
driver_fw/system.c Normal file
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@ -0,0 +1,302 @@
/**
******************************************************************************
* @file system_stm32g0xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32g0xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | HSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 16000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 16000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB Prescaler | 1
*-----------------------------------------------------------------------------
* HSI Division factor | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* Require 48MHz for RNG | Disabled
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* Copyright (c) 2018-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32g0xx_system
* @{
*/
/** @addtogroup STM32G0xx_System_Private_Includes
* @{
*/
#include "stm32g0xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
#if !defined (LSI_VALUE)
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
#endif /* LSI_VALUE */
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
#endif /* LSE_VALUE */
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000UL;
const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G0xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
#endif /* USER_VECT_TAB_ADDRESS */
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
*
* - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp;
uint32_t pllvco;
uint32_t pllr;
uint32_t pllsource;
uint32_t pllm;
uint32_t hsidiv;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_0: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
SystemCoreClock = LSI_VALUE;
break;
case RCC_CFGR_SWS_2: /* LSE used as system clock */
SystemCoreClock = LSE_VALUE;
break;
case RCC_CFGR_SWS_1: /* PLL used as system clock */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
if(pllsource == 0x03UL) /* HSE used as PLL clock source */
{
pllvco = (HSE_VALUE / pllm);
}
else /* HSI used as PLL clock source */
{
pllvco = (HSI_VALUE / pllm);
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
SystemCoreClock = pllvco/pllr;
break;
case 0x00000000U: /* HSI used as system clock */
default: /* HSI used as system clock */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
SystemCoreClock = (HSI_VALUE/hsidiv);
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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@ -1,336 +0,0 @@
/**
******************************************************************************
* @file system_stm32f0xx.c
* copied from: STM32Cube/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates
* @author MCD Application Team
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f0xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. This file configures the system clock as follows:
*=============================================================================
* Supported STM32F0xx device
*-----------------------------------------------------------------------------
* System Clock source | HSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 8000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 8000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f0xx_system
* @{
*/
/** @addtogroup STM32F0xx_System_Private_Includes
* @{
*/
#include "stm32f0xx.h"
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI48_VALUE */
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock there is no need to
call the 2 first functions listed above, since SystemCoreClock variable is
updated automatically.
*/
uint32_t SystemCoreClock = 8000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001U;
#if defined (STM32F051x8) || defined (STM32F058x8)
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
RCC->CFGR &= (uint32_t)0xF8FFB80CU;
#else
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
RCC->CFGR &= (uint32_t)0x08FFB80CU;
#endif /* STM32F051x8 or STM32F058x8 */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFFU;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFFU;
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
#if defined (STM32F072xB) || defined (STM32F078xx)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
#elif defined (STM32F071xB)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
#elif defined (STM32F091xC) || defined (STM32F098xx)
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
#elif defined (STM32F051x8) || defined (STM32F058xx)
/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
#elif defined (STM32F042x6) || defined (STM32F048xx)
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
#elif defined (STM32F070x6) || defined (STM32F070xB)
/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
/* Set default USB clock to PLLCLK, since there is no HSI48 */
RCC->CFGR3 |= (uint32_t)0x00000080U;
#else
#warning "No target selected"
#endif
/* Reset HSI14 bit */
RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
/* Disable all interrupts */
RCC->CIR = 0x00000000U;
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
pllmull = ( pllmull >> 18) + 2;
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
{
/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
}
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
{
/* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
}
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
|| defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
|| defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
#else
/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
STM32F091xC || STM32F098xx || STM32F030xC */
}
break;
default: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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driver_fw/tools/__pycache__/usb_test.cpython-311.pyc Normal file
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88
driver_fw/tools/decode_logic_analzyer.py Normal file
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#!/usr/bin/env python
import sys
import subprocess
import binascii
from statistics import mean
from dataclasses import dataclass, fields
import struct
from pprint import pprint
from cobs import cobs
time = [*sys.argv, '1s'][1]
proc = subprocess.run(f'sigrok-cli --driver dreamsourcelab-dslogic --config samplerate=10M --channels 0,1 --protocol-decoders uart:baudrate=250000:rx=1 --protocol-decoder-annotations uart=rx-data,uart=tx-data --time {time}'.split(), check=True, capture_output=True, text=True)
data = [line.partition(':')[2] for line in proc.stdout.splitlines()]
data = bytes([int(x, 16) for x in data if x])
class Serialized:
@classmethod
def deserialize(kls, data):
fields = struct.unpack(kls._struct_format(), data)
mapped = [cast(val) for cast, val in zip(kls._struct_casts(), fields)]
return kls(*mapped)
@classmethod
def _struct_format(kls):
return kls._parse_fields()[0]
@classmethod
def _struct_casts(kls):
return kls._parse_fields()[1]
@classmethod
def _parse_fields(kls):
fmt = '<'
casts = []
for field in fields(kls):
if isinstance(field.type, tuple):
struct_type, cast = field.type
else:
struct_type, cast = field.type, int
fmt += struct_type
casts.append(cast)
return fmt, casts
@dataclass
class Header(Serialized):
crc: 'I'
src: 'B'
dst: 'B'
pid: 'B'
packet_type: 'B'
@dataclass
class ADCPacket(Serialized):
timestamp: 'Q'
sampling_interval: 'I'
total_samples: 'I'
sample_count: 'I'
samples: ('96s', bytes)
def __post_init__(self):
data = self.samples
foo = lambda x: x if x < 0x800000 else x-0x1000000
self.samples = [[
foo(struct.unpack('<I', data[3*(2*sample + channel):][:3] + b'\0')[0])
for sample in range(16)
] for channel in range(2)]
norm_a, norm_b = 0, 0
for packet in data.split(b'\0'):
try:
packet = cobs.decode(packet)
hdr = Header.deserialize(packet[:8])
if hdr.packet_type == 2:
packet = ADCPacket.deserialize(packet[8:])
diff_a = max([abs(x - norm_a) for x in packet.samples[0][:packet.sample_count]])
diff_b = max([abs(x - norm_b) for x in packet.samples[1][:packet.sample_count]])
if diff_a > 10000 or diff_b > 10000:
pprint(packet)
norm_a = mean(packet.samples[0][:packet.sample_count])
norm_b = mean(packet.samples[1][:packet.sample_count])
elif any(x != 0 for x in packet.samples[0][packet.sample_count:] + packet.samples[1][packet.sample_count:]):
pprint('nonzero', packet)
except (cobs.DecodeError, struct.error):
print('Decoding error')

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driver_fw/tools/extract_pinmap.py Normal file
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#!/usr/bin/env python
import click
@click.command()
@click.option('sch_file')
def cli():
if __name__ == '__main__':
cli()

67
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#!/usr/bin/env python3
import subprocess
import os
import re
import datetime
from pathlib import Path
def cpp_preprocess(input_path, cpp='cpp'):
return subprocess.check_output([cpp, '-P', input_path]).decode()
def gen_isr_header(f, cpp='cpp'):
stripped_code = cpp_preprocess(args.input, args.use_cpp)
armed = False
for line in stripped_code.splitlines():
line = line.strip()
if armed:
if not line.startswith('.word'):
break
word, value = line.split()
assert word == '.word'
if value == '0':
yield None
else:
yield value
else:
if line.startswith('g_pfnVectors:'):
armed = True
else:
raise ValueError('Cannot find interrupt vector definition!')
if __name__ == '__main__':
import argparse
parser = argparse.ArgumentParser()
parser.add_argument('--use-cpp', type=str, default=os.getenv('CPP', 'cpp'), help='cpp (C preprocessor) executable to use')
parser.add_argument('-g', '--generate-include-guards', action='store_true', help='Whether to generate include guards')
parser.add_argument('input', help='Input stm32****_startup.s file')
args = parser.parse_args()
print('/* AUTOGENERATED FILE! DO NOT MODIFY! */')
print(f'/* Generated {datetime.datetime.utcnow()} from {args.input} by {Path(__file__).name} */')
if args.generate_include_guards:
include_guard_id = '__ISR_HEADER_' + re.sub('[^A-Za-z0-9]', '_', args.input.split('/')[-1]) + '__'
print(f'#ifndef {include_guard_id}')
print(f'#define {include_guard_id}')
print()
for i, handler_name in enumerate(gen_isr_header(args.input, args.use_cpp)):
if handler_name is None:
print(f'/* IRQ {i} is undefined for this part. */')
else:
print(f'void {handler_name}(void); {" " * (30-len(handler_name))} /* {i:> 3} */')
print()
print(f'#define NUM_IRQs {i+1}')
print('extern uint32_t g_pfnVectors[NUM_IRQs];')
print('#define isr_vector g_pfnVectors')
print()
if args.generate_include_guards:
print(f'#endif /* {include_guard_id} */')

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import sys
import pyparsing as pp
from pyparsing import pyparsing_common as ppc
LPAREN, RPAREN, LBRACE, RBRACE, LBROK, RBROK, COLON, SEMICOLON, EQUALS, COMMA = map(pp.Suppress, '(){}<>:;=,')
parse_suffix_int = lambda lit: int(lit[:-1]) * (10**(3*(1 + 'kmgtpe'.find(lit[-1].lower()))))
si_suffix = pp.oneOf('k m g t p e', caseless=True)
numeric_literal = pp.Regex('0x[0-9a-fA-F]+').setName('hex int').setParseAction(pp.tokenMap(int, 16)) \
| (pp.Regex('[0-9]+[kKmMgGtTpPeE]')).setName('size int').setParseAction(pp.tokenMap(parse_suffix_int)) \
| pp.Word(pp.nums).setName('int').setParseAction(pp.tokenMap(int))
access_def = pp.Regex('[rR]?[wW]?[xX]?').setName('access literal').setParseAction(pp.tokenMap(str.lower))
origin_expr = pp.Suppress(pp.CaselessKeyword('ORIGIN')) + EQUALS + numeric_literal
length_expr = pp.Suppress(pp.CaselessKeyword('LENGTH')) + EQUALS + numeric_literal
mem_expr = pp.Group(ppc.identifier + LPAREN + access_def + RPAREN + COLON + origin_expr + COMMA + length_expr)
mem_contents = pp.ZeroOrMore(mem_expr)
mem_toplevel = pp.CaselessKeyword("MEMORY") + pp.Group(LBRACE + pp.Optional(mem_contents, []) + RBRACE)
glob = pp.Word(pp.alphanums + '._*')
match_expr = pp.Forward()
assignment = pp.Forward()
funccall = pp.Group(pp.Word(pp.alphas + '_') + LPAREN + (assignment | numeric_literal | match_expr | glob | ppc.identifier) + RPAREN + pp.Optional(SEMICOLON))
value = numeric_literal | funccall | ppc.identifier | '.'
formula = (value + pp.oneOf('+ = * / %') + value) | value
# suppress stray semicolons
assignment << (SEMICOLON | pp.Group((ppc.identifier | '.') + EQUALS + (formula | value) + pp.Optional(SEMICOLON)))
match_expr << (glob + LPAREN + pp.OneOrMore(funccall | glob) + RPAREN)
section_contents = pp.ZeroOrMore(assignment | funccall | match_expr);
section_name = pp.Regex('\.[a-zA-Z0-9_.]+')
section_def = pp.Group(section_name + pp.Optional(numeric_literal) + COLON + LBRACE + pp.Group(section_contents) +
RBRACE + pp.Optional(RBROK + ppc.identifier + pp.Optional('AT' + RBROK + ppc.identifier)))
sec_contents = pp.ZeroOrMore(section_def | assignment)
sections_toplevel = pp.Group(pp.CaselessKeyword("SECTIONS").suppress() + LBRACE + sec_contents + RBRACE)
toplevel_elements = mem_toplevel | funccall | sections_toplevel | assignment
ldscript = pp.Group(pp.ZeroOrMore(toplevel_elements))
ldscript.ignore(pp.cppStyleComment)
if __name__ == '__main__':
import argparse
parser = argparse.ArgumentParser()
parser.add_argument('linker_script', type=argparse.FileType('r'))
args = parser.parse_args()
#print(mem_expr.parseString('FLASH (rx) : ORIGIN = 0x0800000, LENGTH = 512K', parseAll=True))
# print(ldscript.parseString('''
# /* Entry Point */
# ENTRY(Reset_Handler)
#
# /* Highest address of the user mode stack */
# _estack = 0x20020000; /* end of RAM */
# /* Generate a link error if heap and stack don't fit into RAM */
# _Min_Heap_Size = 0x200;; /* required amount of heap */
# _Min_Stack_Size = 0x400;; /* required amount of stack */
# ''', parseAll=True))
print(ldscript.parseFile(args.linker_script, parseAll=True))
#print(funccall.parseString('KEEP(*(.isr_vector))'))
#print(section_contents.parseString('''
# . = ALIGN(4);
# KEEP(*(.isr_vector)) /* Startup code */
# . = ALIGN(4);
# ''', parseAll=True))
#print(section_def.parseString('''
# .text :
# {
# . = ALIGN(4);
# *(.text) /* .text sections (code) */
# *(.text*) /* .text* sections (code) */
# *(.glue_7) /* glue arm to thumb code */
# *(.glue_7t) /* glue thumb to arm code */
# *(.eh_frame)
#
# KEEP (*(.init))
# KEEP (*(.fini))
#
# . = ALIGN(4);
# _etext = .; /* define a global symbols at end of code */
# } >FLASH
# ''', parseAll=True))
#print(section_def.parseString('.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH', parseAll=True))
#print(assignment.parseString('__preinit_array_start = .', parseAll=True))
#print(assignment.parseString('a = 23', parseAll=True))
#print(funccall.parseString('foo (a=23)', parseAll=True))
#print(funccall.parseString('PROVIDE_HIDDEN (__preinit_array_start = .);', parseAll=True))
#print(section_def.parseString('''
# .preinit_array :
# {
# PROVIDE_HIDDEN (__preinit_array_start = .);
# KEEP (*(.preinit_array*))
# PROVIDE_HIDDEN (__preinit_array_end = .);
# } >FLASH''', parseAll=True))
#print(match_expr.parseString('*(SORT(.init_array.*))', parseAll=True))
#print(funccall.parseString('KEEP (*(SORT(.init_array.*)))', parseAll=True))
#print(section_def.parseString('''
# .init_array :
# {
# PROVIDE_HIDDEN (__init_array_start = .);
# KEEP (*(SORT(.init_array.*)))
# KEEP (*(.init_array*))
# PROVIDE_HIDDEN (__init_array_end = .);
# } >FLASH
# ''', parseAll=True))
#print(match_expr.parseString('*(.ARM.extab* .gnu.linkonce.armextab.*)', parseAll=True))
#print(formula.parseString('. + _Min_Heap_Size', parseAll=True))
#print(assignment.parseString('. = . + _Min_Heap_Size;', parseAll=True))
#print(sections_toplevel.parseString('''
# SECTIONS
# {
# .ARMattributes : { }
# }
# ''', parseAll=True))
#sys.exit(0)

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import tempfile
import os
from os import path
import sys
import re
import subprocess
from contextlib import contextmanager
from collections import defaultdict
import colorsys
import cxxfilt
from elftools.elf.elffile import ELFFile
from elftools.elf.enums import ENUM_ST_SHNDX
from elftools.elf.descriptions import describe_symbol_type, describe_sh_type
import libarchive
import matplotlib.cm
@contextmanager
def chdir(newdir):
old_cwd = os.getcwd()
try:
os.chdir(newdir)
yield
finally:
os.chdir(old_cwd)
def keep_last(it, first=None):
last = first
for elem in it:
yield last, elem
last = elem
def delim(start, end, it, first_only=True):
found = False
for elem in it:
if end(elem):
if first_only:
return
found = False
elif start(elem):
found = True
elif found:
yield elem
def delim_prefix(start, end, it):
yield from delim(lambda l: l.startswith(start), lambda l: end is not None and l.startswith(end), it)
def trace_source_files(linker, cmdline, trace_sections=[], total_sections=['.text', '.data', '.rodata']):
with tempfile.TemporaryDirectory() as tempdir:
out_path = path.join(tempdir, 'output.elf')
output = subprocess.check_output([linker, '-o', out_path, f'-Wl,--print-map', *cmdline])
lines = [ line.strip() for line in output.decode().splitlines() ]
# FIXME also find isr vector table references
defs = {}
objs = defaultdict(lambda: 0)
aliases = {}
sec_name = None
last_loc = None
last_sym = None
line_cont = None
for last_line, line in keep_last(delim_prefix('Linker script and memory map', 'OUTPUT', lines), first=''):
if not line or line.startswith('LOAD '):
sec_name = None
continue
# first part of continuation line
if m := re.match('^(\.[0-9a-zA-Z-_.]+)$', line):
line_cont = line
sec_name = None
continue
if line_cont:
line = line_cont + ' ' + line
line_cont = None
# -ffunction-sections/-fdata-sections section
if m := re.match('^(\.[0-9a-zA-Z-_.]+)\.([0-9a-zA-Z-_.]+)\s+(0x[0-9a-f]+)\s+(0x[0-9a-f]+)\s+(\S+)$', line):
sec, sym, loc, size, obj = m.groups()
*_, sym = sym.rpartition('.')
sym = cxxfilt.demangle(sym)
size = int(size, 16)
obj = path.abspath(obj)
if sec not in total_sections:
size = 0
objs[obj] += size
defs[sym] = (sec, size, obj)
sec_name, last_loc, last_sym = sec, loc, sym
continue
# regular (no -ffunction-sections/-fdata-sections) section
if m := re.match('^(\.[0-9a-zA-Z-_]+)\s+(0x[0-9a-f]+)\s+(0x[0-9a-f]+)\s+(\S+)$', line):
sec, _loc, size, obj = m.groups()
size = int(size, 16)
obj = path.abspath(obj)
if sec in total_sections:
objs[obj] += size
sec_name = sec
last_loc, last_sym = None, None
continue
# symbol def
if m := re.match('^(0x[0-9a-f]+)\s+(\S+)$', line):
loc, sym = m.groups()
sym = cxxfilt.demangle(sym)
loc = int(loc, 16)
if sym in defs:
continue
if loc == last_loc:
assert last_sym is not None
aliases[sym] = last_sym
else:
assert sec_name
defs[sym] = (sec_name, None, obj)
last_loc, last_sym = loc, sym
continue
refs = defaultdict(lambda: set())
for sym, (sec, size, obj) in defs.items():
fn, _, member = re.match('^([^()]+)(\((.+)\))?$', obj).groups()
fn = path.abspath(fn)
if member:
subprocess.check_call(['ar', 'x', '--output', tempdir, fn, member])
fn = path.join(tempdir, member)
with open(fn, 'rb') as f:
elf = ELFFile(f)
symtab = elf.get_section_by_name('.symtab')
symtab_demangled = { cxxfilt.demangle(nsym.name).replace(' ', ''): i
for i, nsym in enumerate(symtab.iter_symbols()) }
s = set()
sec_map = { sec.name: i for i, sec in enumerate(elf.iter_sections()) }
matches = [ i for name, i in sec_map.items() if re.match(f'\.rel\..*\.{sym}', name) ]
if matches:
sec = elf.get_section(matches[0])
for reloc in sec.iter_relocations():
refsym = symtab.get_symbol(reloc['r_info_sym'])
name = refsym.name if refsym.name else elf.get_section(refsym['st_shndx']).name.split('.')[-1]
s.add(name)
refs[sym] = s
for tsec in trace_sections:
matches = [ i for name, i in sec_map.items() if name == f'.rel{tsec}' ]
s = set()
if matches:
sec = elf.get_section(matches[0])
for reloc in sec.iter_relocations():
refsym = symtab.get_symbol(reloc['r_info_sym'])
s.add(refsym.name)
refs[tsec.replace('.', '_')] |= s
return objs, aliases, defs, refs
@contextmanager
def wrap(leader='', print=print, left='{', right='}'):
print(leader, left)
yield lambda *args, **kwargs: print(' ', *args, **kwargs)
print(right)
def mangle(name):
return re.sub('[^a-zA-Z0-9_]', '_', name)
hexcolor = lambda r, g, b, *_a: f'#{int(r*255):02x}{int(g*255):02x}{int(b*255):02x}'
def vhex(val):
r,g,b,_a = matplotlib.cm.viridis(1.0-val)
fc = hexcolor(r, g, b)
h,s,v = colorsys.rgb_to_hsv(r,g,b)
cc = '#000000' if v > 0.8 else '#ffffff'
return fc, cc
if __name__ == '__main__':
import argparse
parser = argparse.ArgumentParser()
parser.add_argument('--trace-sections', type=str, action='append', default=[])
parser.add_argument('--trim-stubs', type=str, action='append', default=[])
parser.add_argument('--highlight-subdirs', type=str, default=None)
parser.add_argument('linker_binary')
parser.add_argument('linker_args', nargs=argparse.REMAINDER)
args = parser.parse_args()
trace_sections = args.trace_sections
trace_sections_mangled = { sec.replace('.', '_') for sec in trace_sections }
objs, aliases, syms, refs = trace_source_files(args.linker_binary, args.linker_args, trace_sections)
clusters = defaultdict(lambda: [])
for sym, (sec, size, obj) in syms.items():
clusters[obj].append((sym, sec, size))
max_ssize = max(size or 0 for _sec, size, _obj in syms.values())
max_osize = max(objs.values())
subdir_prefix = path.abspath(args.highlight_subdirs) + '/' if args.highlight_subdirs else '### NO HIGHLIGHT ###'
first_comp = lambda le_path: path.dirname(le_path).partition(os.sep)[0]
subdir_colors = sorted({ first_comp(obj[len(subdir_prefix):]) for obj in objs if obj.startswith(subdir_prefix) })
subdir_colors = { path: hexcolor(*matplotlib.cm.Pastel1(i/len(subdir_colors))) for i, path in enumerate(subdir_colors) }
subdir_sizes = defaultdict(lambda: 0)
for obj, size in objs.items():
if not isinstance(size, int):
continue
if obj.startswith(subdir_prefix):
subdir_sizes[first_comp(obj[len(subdir_prefix):])] += size
else:
subdir_sizes['<others>'] += size
print('Subdir sizes:', file=sys.stderr)
for subdir, size in sorted(subdir_sizes.items(), key=lambda x: x[1]):
print(f'{subdir:>20}: {size:>6,d} B', file=sys.stderr)
def lookup_highlight(path):
if args.highlight_subdirs:
if obj.startswith(subdir_prefix):
highlight_head = first_comp(path[len(subdir_prefix):])
return subdir_colors[highlight_head], highlight_head
else:
return '#e0e0e0', None
else:
return '#ddf7f4', None
with wrap('digraph G', print) as lvl1print:
print('size="23.4,16.5!";')
print('graph [fontsize=40];')
print('node [fontsize=40];')
#print('ratio="fill";')
print('rankdir=LR;')
print('ranksep=5;')
print('nodesep=0.2;')
print()
for i, (obj, obj_syms) in enumerate(clusters.items()):
with wrap(f'subgraph cluster_{i}', lvl1print) as lvl2print:
print('style = "filled";')
highlight_color, highlight_head = lookup_highlight(obj)
print(f'bgcolor = "{highlight_color}";')
print('pencolor = none;')
fc, cc = vhex(objs[obj]/max_osize)
highlight_subdir_part = f'<font face="carlito" color="{cc}" point-size="40">{highlight_head} / </font>' if highlight_head else ''
lvl2print(f'label = <<table border="0"><tr><td border="0" cellpadding="5" bgcolor="{fc}">'
f'{highlight_subdir_part}'
f'<font face="carlito" color="{cc}"><b>{path.basename(obj)} ({objs[obj]}B)</b></font>'
f'</td></tr></table>>;')
lvl2print()
for sym, sec, size in obj_syms:
has_size = isinstance(size, int) and size > 0
size_s = f' ({size}B)' if has_size else ''
fc, cc = vhex(size/max_ssize) if has_size else ('#ffffff', '#000000')
shape = 'box' if sec == '.text' else 'oval'
lvl2print(f'{mangle(sym)}[label = "{sym}{size_s}", style="rounded,filled", shape="{shape}", fillcolor="{fc}", fontname="carlito", fontcolor="{cc}" color=none];')
lvl1print()
edges = set()
for start, ends in refs.items():
for end in ends:
end = aliases.get(end, end)
if (start in syms or start in trace_sections_mangled) and end in syms:
edges.add((start, end))
for start, end in edges:
lvl1print(f'{mangle(start)} -> {mangle(end)} [style="bold", color="#333333"];')
for sec in trace_sections:
lvl1print(f'{sec.replace(".", "_")} [label = "section {sec}", shape="box", style="filled,bold"];')

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#!/usr/bin/env python3
def parse_linker_script(data):
pass
def link(groups):
defined_symbols = {}
undefined_symbols = set()
for group, files in groups:
while True:
found_something = False
for fn in files:
symbols = load_symbols(fn)
for symbol in symbols:
if symbol in defined_symbols:
if not group or not found_something:
break
if __name__ == '__main__':
import argparse
parser = argparse.ArgumentParser()
parser.add_argument('-T', '--script', type=str, help='Linker script to use')
parser.add_argument('-o', '--output', type=str, help='Output file to produce')
args, rest = parser.parse_known_intermixed_args()
print(rest)
addprefix = lambda *xs: [ prefix + opt for opt in xs for prefix in ('', '-Wl,') ]
START_GROUP = addprefix('-(', '--start-group')
END_GROUP = addprefix('-)', '--end-group')
GROUP_OPTS = [*START_GROUP, *END_GROUP]
input_files = [ arg for arg in rest if not arg.startswith('-') or arg in GROUP_OPTS ]
def input_file_iter(input_files):
group = False
files = []
for arg in input_files:
if arg in START_GROUP:
assert not group
if files:
yield False, files # nested -Wl,--start-group
group, files = True, []
elif arg in END_GROUP:
assert group # missing -Wl,--start-group
if files:
yield True, files
group, files = False, []
else:
files.append(arg)
assert not group # missing -Wl,--end-group
if files:
yield False, files

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#!/usr/bin/env python3
import re
import subprocess
import tempfile
import pprint
ARCHIVE_RE = r'([^(]*)(\([^)]*\))?'
def trace_source_files(linker, cmdline):
with tempfile.NamedTemporaryFile() as mapfile:
output = subprocess.check_output([linker, f'-Wl,--Map={mapfile.name}', *cmdline])
# intentionally use generator here
idx = 0
lines = [ line.rstrip() for line in mapfile.read().decode().splitlines() if line.strip() ]
for idx, line in enumerate(lines[idx:], start=idx):
#print('Dropping', line)
if line == 'Linker script and memory map':
break
idx += 1
objects = []
symbols = {}
sections = {}
current_object = None
last_offset = None
last_symbol = None
cont_sec = None
cont_ind = None
current_section = None
for idx, line in enumerate(lines[idx:], start=idx):
print(f'Processing >{line}')
if line.startswith('LOAD'):
_load, obj = line.split()
objects.append(obj)
continue
if line.startswith('OUTPUT'):
break
m = re.match(r'^( ?)([^ ]+)? +(0x[0-9a-z]+) +(0x[0-9a-z]+)?(.*)?$', line)
if m is None:
m = re.match(r'^( ?)([^ ]+)?$', line)
if m:
cont_ind, cont_sec = m.groups()
else:
cont_ind, cont_sec = None, None
last_offset, last_symbol = None, None
continue
indent, sec, offx, size, sym_or_src = m.groups()
if sec is None:
sec = cont_sec
ind = cont_ind
cont_sec = None
cont_ind = None
print(f'vals: indent={indent} sec={sec} offx={offx} size={size} sym_or_src={sym_or_src}')
if not re.match('^[a-zA-Z_0-9<>():*]+$', sym_or_src):
continue
if indent == '':
print(f'Section: {sec} 0x{size:x}')
current_section = sec
sections[sec] = size
last_offset = None
last_symbol = None
continue
if offx is not None:
offx = int(offx, 16)
if size is not None:
size = int(size, 16)
if size is not None and sym_or_src is not None:
# archive/object line
archive, _member = re.match(ARCHIVE_RE, sym_or_src).groups()
current_object = archive
last_offset = offx
else:
if sym_or_src is not None:
assert size is None
if last_offset is not None:
last_size = offx - last_offset
symbols[last_symbol] = (last_size, current_section)
print(f'Symbol: {last_symbol} 0x{last_size:x} @{current_section}')
last_offset = offx
last_symbol = sym_or_src
idx += 1
for idx, line in enumerate(lines[idx:], start=idx):
if line == 'Cross Reference Table':
break
idx += 1
# map which symbol was pulled from which object in the end
used_defs = {}
for line in lines:
*left, right = line.split()
archive, _member = re.match(ARCHIVE_RE, right).groups()
if left:
used_defs[''.join(left)] = archive
#pprint.pprint(symbols)
if __name__ == '__main__':
import argparse
parser = argparse.ArgumentParser()
parser.add_argument('linker_binary')
parser.add_argument('linker_args', nargs=argparse.REMAINDER)
args = parser.parse_args()
source_files = trace_source_files(args.linker_binary, args.linker_args)

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import re
from collections import defaultdict, namedtuple
Section = namedtuple('Section', ['name', 'offset', 'objects'])
ObjectEntry = namedtuple('ObjectEntry', ['filename', 'object', 'offset', 'size'])
FileEntry = namedtuple('FileEntry', ['section', 'object', 'offset', 'length'])
class Memory:
def __init__(self, name, origin, length, attrs=''):
self.name, self.origin, self.length, self.attrs = name, origin, length, attrs
self.sections = {}
self.files = defaultdict(lambda: [])
self.totals = defaultdict(lambda: 0)
def add_toplevel(self, name, offx, length):
self.sections[name] = Section(offx, length, [])
def add_obj(self, name, offx, length, fn, obj):
base_section, sep, subsec = name[1:].partition('.')
base_section = '.'+base_section
if base_section in self.sections:
sec = secname, secoffx, secobjs = self.sections[base_section]
secobjs.append(ObjectEntry(fn, obj, offx, length))
else:
sec = None
self.files[fn].append(FileEntry(sec, obj, offx, length))
self.totals[fn] += length
class MapFile:
def __init__(self, s):
self._lines = s.splitlines()
self.memcfg = {}
self.defaultmem = Memory('default', 0, 0xffffffffffffffff)
self._parse()
def __getitem__(self, offx_or_name):
''' Lookup a memory area by name or address '''
if offx_or_name in self.memcfg:
return self.memcfg[offx_or_name]
elif isinstance(offx_or_name, int):
for mem in self.memcfg.values():
if mem.origin <= offx_or_name < mem.origin+mem.length:
return mem
else:
return self.defaultmem
raise ValueError('Invalid argument type for indexing')
def _skip(self, regex):
matcher = re.compile(regex)
for l in self:
if matcher.match(l):
break
def __iter__(self):
while self._lines:
yield self._lines.pop(0)
def _parse(self):
self._skip('^Memory Configuration')
# Parse memory segmentation info
self._skip('^Name')
for l in self:
if not l:
break
name, origin, length, *attrs = l.split()
if not name.startswith('*'):
self.memcfg[name] = Memory(name, int(origin, 16), int(length, 16), attrs[0] if attrs else '')
# Parse section information
toplevel_m = re.compile('^(\.[a-zA-Z0-9_.]+)\s+(0x[0-9a-fA-F]+)\s+(0x[0-9a-fA-F]+)')
secondlevel_m = re.compile('^ (\.[a-zA-Z0-9_.]+)\s+(0x[0-9a-fA-F]+)\s+(0x[0-9a-fA-F]+)\s+(.*)$')
secondlevel_linebreak_m = re.compile('^ (\.[a-zA-Z0-9_.]+)\n')
filelike = re.compile('^(/?[^()]*\.[a-zA-Z0-9-_]+)(\(.*\))?')
linebreak_section = None
for l in self:
# Toplevel section
match = toplevel_m.match(l)
if match:
name, offx, length = match.groups()
offx, length = int(offx, 16), int(length, 16)
self[offx].add_toplevel(name, offx, length)
match = secondlevel_linebreak_m.match(l)
if match:
linebreak_section, = match.groups()
continue
if linebreak_section:
l = ' {} {}'.format(linebreak_section, l)
linebreak_section = None
# Second-level section
match = secondlevel_m.match(l)
if match:
name, offx, length, misc = match.groups()
match = filelike.match(misc)
if match:
fn, obj = match.groups()
obj = obj.strip('()') if obj else None
offx, length = int(offx, 16), int(length, 16)
self[offx].add_obj(name, offx, length, fn, obj)
if __name__ == '__main__':
import argparse
parser = argparse.ArgumentParser(description='Parser GCC map file')
parser.add_argument('mapfile', type=argparse.FileType('r'), help='The GCC .map file to parse')
parser.add_argument('-m', '--memory', type=str, help='The memory segments to print, comma-separated')
args = parser.parse_args()
mf = MapFile(args.mapfile.read())
args.mapfile.close()
mems = args.memory.split(',') if args.memory else mf.memcfg.keys()
for name in mems:
mem = mf.memcfg[name]
print('Symbols by file for memory', name)
for tot, fn in reversed(sorted( (tot, fn) for fn, tot in mem.totals.items() )):
print(' {:>8} {}'.format(tot, fn))
for length, offx, sec, obj in reversed(sorted(( (length, offx, sec, obj) for sec, obj, offx, length in
mem.files[fn] ), key=lambda e: e[0] )):
name = sec.name if sec else None
print(' {:>8} {:>#08x} {}'.format(length, offx, obj))
#print('{:>16} 0x{:016x} 0x{:016x} ({:>24}) {}'.format(name, origin, length, length, attrs))

23
driver_fw/tools/musl_include_shims/bits/alltypes.h Normal file
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/* shim file for musl */
#ifndef __MUSL_SHIM_BITS_ALLTYPES_H__
#define __MUSL_SHIM_BITS_ALLTYPES_H__
#define _REDIR_TIME64 1
#define _Addr int
#define _Int64 long long
#define _Reg int
#define __BYTE_ORDER 1234
#define __LONG_MAX 0x7fffffffL
#ifndef __cplusplus
typedef unsigned wchar_t;
#endif
typedef float float_t;
typedef double double_t;
#endif /* __MUSL_SHIM_BITS_ALLTYPES_H__ */

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driver_fw/tools/musl_include_shims/endian.h Normal file
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#ifndef _ENDIAN_H
#define _ENDIAN_H
#include <features.h>
#define __NEED_uint16_t
#define __NEED_uint32_t
#define __NEED_uint64_t
#include <bits/alltypes.h>
#define __PDP_ENDIAN 3412
#define BIG_ENDIAN __BIG_ENDIAN
#define LITTLE_ENDIAN __LITTLE_ENDIAN
#define PDP_ENDIAN __PDP_ENDIAN
#define BYTE_ORDER __BYTE_ORDER
static __inline uint16_t __bswap16(uint16_t __x)
{
return __x<<8 | __x>>8;
}
static __inline uint32_t __bswap32(uint32_t __x)
{
return __x>>24 | __x>>8&0xff00 | __x<<8&0xff0000 | __x<<24;
}
static __inline uint64_t __bswap64(uint64_t __x)
{
return __bswap32(__x)+0ULL<<32 | __bswap32(__x>>32);
}
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define htobe16(x) __bswap16(x)
#define be16toh(x) __bswap16(x)
#define htobe32(x) __bswap32(x)
#define be32toh(x) __bswap32(x)
#define htobe64(x) __bswap64(x)
#define be64toh(x) __bswap64(x)
#define htole16(x) (uint16_t)(x)
#define le16toh(x) (uint16_t)(x)
#define htole32(x) (uint32_t)(x)
#define le32toh(x) (uint32_t)(x)
#define htole64(x) (uint64_t)(x)
#define le64toh(x) (uint64_t)(x)
#else
#define htobe16(x) (uint16_t)(x)
#define be16toh(x) (uint16_t)(x)
#define htobe32(x) (uint32_t)(x)
#define be32toh(x) (uint32_t)(x)
#define htobe64(x) (uint64_t)(x)
#define be64toh(x) (uint64_t)(x)
#define htole16(x) __bswap16(x)
#define le16toh(x) __bswap16(x)
#define htole32(x) __bswap32(x)
#define le32toh(x) __bswap32(x)
#define htole64(x) __bswap64(x)
#define le64toh(x) __bswap64(x)
#endif
#if defined(_GNU_SOURCE) || defined(_BSD_SOURCE)
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define betoh16(x) __bswap16(x)
#define betoh32(x) __bswap32(x)
#define betoh64(x) __bswap64(x)
#define letoh16(x) (uint16_t)(x)
#define letoh32(x) (uint32_t)(x)
#define letoh64(x) (uint64_t)(x)
#else
#define betoh16(x) (uint16_t)(x)
#define betoh32(x) (uint32_t)(x)
#define betoh64(x) (uint64_t)(x)
#define letoh16(x) __bswap16(x)
#define letoh32(x) __bswap32(x)
#define letoh64(x) __bswap64(x)
#endif
#endif
#endif

40
driver_fw/tools/musl_include_shims/features.h Normal file
View file

@ -0,0 +1,40 @@
#ifndef _FEATURES_H
#define _FEATURES_H
#if defined(_ALL_SOURCE) && !defined(_GNU_SOURCE)
#define _GNU_SOURCE 1
#endif
#if defined(_DEFAULT_SOURCE) && !defined(_BSD_SOURCE)
#define _BSD_SOURCE 1
#endif
#if !defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) \
&& !defined(_XOPEN_SOURCE) && !defined(_GNU_SOURCE) \
&& !defined(_BSD_SOURCE) && !defined(__STRICT_ANSI__)
#define _BSD_SOURCE 1
#define _XOPEN_SOURCE 700
#endif
#if __STDC_VERSION__ >= 199901L
#define __restrict restrict
#elif !defined(__GNUC__)
#define __restrict
#endif
#if __STDC_VERSION__ >= 199901L || defined(__cplusplus)
#define __inline inline
#elif !defined(__GNUC__)
#define __inline
#endif
#if __STDC_VERSION__ >= 201112L
#elif defined(__GNUC__)
#define _Noreturn __attribute__((__noreturn__))
#else
#define _Noreturn
#endif
#define __REDIR(x,y) __typeof__(x) x __asm__(#y)
#endif

6
driver_fw/tools/musl_include_shims/fp_arch.h Normal file
View file

@ -0,0 +1,6 @@
#ifndef __MUSL_SHIM_FP_ARCH_H__
#define __MUSL_SHIM_FP_ARCH_H__
#define hidden
#endif /* __MUSL_SHIM_FP_ARCH_H__ */

270
driver_fw/tools/musl_include_shims/libm.h Normal file
View file

@ -0,0 +1,270 @@
#ifndef _LIBM_H
#define _LIBM_H
#include <stdint.h>
#include <float.h>
#include <math.h>
#include <endian.h>
#include "fp_arch.h"
#if LDBL_MANT_DIG == 53 && LDBL_MAX_EXP == 1024
#elif LDBL_MANT_DIG == 64 && LDBL_MAX_EXP == 16384 && __BYTE_ORDER == __LITTLE_ENDIAN
union ldshape {
long double f;
struct {
uint64_t m;
uint16_t se;
} i;
};
#elif LDBL_MANT_DIG == 64 && LDBL_MAX_EXP == 16384 && __BYTE_ORDER == __BIG_ENDIAN
/* This is the m68k variant of 80-bit long double, and this definition only works
* on archs where the alignment requirement of uint64_t is <= 4. */
union ldshape {
long double f;
struct {
uint16_t se;
uint16_t pad;
uint64_t m;
} i;
};
#elif LDBL_MANT_DIG == 113 && LDBL_MAX_EXP == 16384 && __BYTE_ORDER == __LITTLE_ENDIAN
union ldshape {
long double f;
struct {
uint64_t lo;
uint32_t mid;
uint16_t top;
uint16_t se;
} i;
struct {
uint64_t lo;
uint64_t hi;
} i2;
};
#elif LDBL_MANT_DIG == 113 && LDBL_MAX_EXP == 16384 && __BYTE_ORDER == __BIG_ENDIAN
union ldshape {
long double f;
struct {
uint16_t se;
uint16_t top;
uint32_t mid;
uint64_t lo;
} i;
struct {
uint64_t hi;
uint64_t lo;
} i2;
};
#else
#error Unsupported long double representation
#endif
/* Support non-nearest rounding mode. */
#define WANT_ROUNDING 1
/* Support signaling NaNs. */
#define WANT_SNAN 0
#if WANT_SNAN
#error SNaN is unsupported
#else
#define issignalingf_inline(x) 0
#define issignaling_inline(x) 0
#endif
#ifndef TOINT_INTRINSICS
#define TOINT_INTRINSICS 0
#endif
#if TOINT_INTRINSICS
/* Round x to nearest int in all rounding modes, ties have to be rounded
consistently with converttoint so the results match. If the result
would be outside of [-2^31, 2^31-1] then the semantics is unspecified. */
static double_t roundtoint(double_t);
/* Convert x to nearest int in all rounding modes, ties have to be rounded
consistently with roundtoint. If the result is not representible in an
int32_t then the semantics is unspecified. */
static int32_t converttoint(double_t);
#endif
/* Helps static branch prediction so hot path can be better optimized. */
#ifdef __GNUC__
#define predict_true(x) __builtin_expect(!!(x), 1)
#define predict_false(x) __builtin_expect(x, 0)
#else
#define predict_true(x) (x)
#define predict_false(x) (x)
#endif
/* Evaluate an expression as the specified type. With standard excess
precision handling a type cast or assignment is enough (with
-ffloat-store an assignment is required, in old compilers argument
passing and return statement may not drop excess precision). */
static inline float eval_as_float(float x)
{
float y = x;
return y;
}
static inline double eval_as_double(double x)
{
double y = x;
return y;
}
/* fp_barrier returns its input, but limits code transformations
as if it had a side-effect (e.g. observable io) and returned
an arbitrary value. */
#ifndef fp_barrierf
#define fp_barrierf fp_barrierf
static inline float fp_barrierf(float x)
{
volatile float y = x;
return y;
}
#endif
#ifndef fp_barrier
#define fp_barrier fp_barrier
static inline double fp_barrier(double x)
{
volatile double y = x;
return y;
}
#endif
#ifndef fp_barrierl
#define fp_barrierl fp_barrierl
static inline long double fp_barrierl(long double x)
{
volatile long double y = x;
return y;
}
#endif
/* fp_force_eval ensures that the input value is computed when that's
otherwise unused. To prevent the constant folding of the input
expression, an additional fp_barrier may be needed or a compilation
mode that does so (e.g. -frounding-math in gcc). Then it can be
used to evaluate an expression for its fenv side-effects only. */
#ifndef fp_force_evalf
#define fp_force_evalf fp_force_evalf
static inline void fp_force_evalf(float x)
{
volatile float y;
y = x;
}
#endif
#ifndef fp_force_eval
#define fp_force_eval fp_force_eval
static inline void fp_force_eval(double x)
{
volatile double y;
y = x;
}
#endif
#ifndef fp_force_evall
#define fp_force_evall fp_force_evall
static inline void fp_force_evall(long double x)
{
volatile long double y;
y = x;
}
#endif
#define FORCE_EVAL(x) do { \
if (sizeof(x) == sizeof(float)) { \
fp_force_evalf(x); \
} else if (sizeof(x) == sizeof(double)) { \
fp_force_eval(x); \
} else { \
fp_force_evall(x); \
} \
} while(0)
#define asuint(f) ((union{float _f; uint32_t _i;}){f})._i
#define asfloat(i) ((union{uint32_t _i; float _f;}){i})._f
#define asuint64(f) ((union{double _f; uint64_t _i;}){f})._i
#define asdouble(i) ((union{uint64_t _i; double _f;}){i})._f
#define EXTRACT_WORDS(hi,lo,d) \
do { \
uint64_t __u = asuint64(d); \
(hi) = __u >> 32; \
(lo) = (uint32_t)__u; \
} while (0)
#define GET_HIGH_WORD(hi,d) \
do { \
(hi) = asuint64(d) >> 32; \
} while (0)
#define GET_LOW_WORD(lo,d) \
do { \
(lo) = (uint32_t)asuint64(d); \
} while (0)
#define INSERT_WORDS(d,hi,lo) \
do { \
(d) = asdouble(((uint64_t)(hi)<<32) | (uint32_t)(lo)); \
} while (0)
#define SET_HIGH_WORD(d,hi) \
INSERT_WORDS(d, hi, (uint32_t)asuint64(d))
#define SET_LOW_WORD(d,lo) \
INSERT_WORDS(d, asuint64(d)>>32, lo)
#define GET_FLOAT_WORD(w,d) \
do { \
(w) = asuint(d); \
} while (0)
#define SET_FLOAT_WORD(d,w) \
do { \
(d) = asfloat(w); \
} while (0)
hidden int __rem_pio2_large(double*,double*,int,int,int);
hidden int __rem_pio2(double,double*);
hidden double __sin(double,double,int);
hidden double __cos(double,double);
hidden double __tan(double,double,int);
hidden double __expo2(double);
hidden int __rem_pio2f(float,double*);
hidden float __sindf(double);
hidden float __cosdf(double);
hidden float __tandf(double,int);
hidden float __expo2f(float);
hidden int __rem_pio2l(long double, long double *);
hidden long double __sinl(long double, long double, int);
hidden long double __cosl(long double, long double);
hidden long double __tanl(long double, long double, int);
hidden long double __polevll(long double, const long double *, int);
hidden long double __p1evll(long double, const long double *, int);
hidden double __lgamma_r(double, int *);
hidden float __lgammaf_r(float, int *);
/* error handling functions */
hidden float __math_xflowf(uint32_t, float);
hidden float __math_uflowf(uint32_t);
hidden float __math_oflowf(uint32_t);
hidden float __math_divzerof(uint32_t);
hidden float __math_invalidf(float);
hidden double __math_xflow(uint32_t, double);
hidden double __math_uflow(uint32_t);
hidden double __math_oflow(uint32_t);
hidden double __math_divzero(uint32_t);
hidden double __math_invalid(double);
#endif

188
driver_fw/tools/usb_test.py Normal file
View file

@ -0,0 +1,188 @@
#!/usr/bin/env python
import time
from pprint import pprint
from enum import Enum
from functools import cache
from dataclasses import dataclass, fields, astuple
import struct
import binascii
import numpy as np
import click
import serial
from cobs import cobs
class CobsSerial:
def __init__(self, port, timeout):
self.ser = serial.Serial(port, timeout=timeout)
self.ser.flushOutput()
self.ser.flushInput()
self.ser.write(bytes([0])) # synchronize
self.ser.flushOutput()
def write_packet(self, data):
self.ser.write(cobs.encode(data))
self.ser.write(bytes([0]))
self.ser.flushOutput()
def read_packet(self):
data = b''
while (b := self.ser.read(1)):
if b[0] == 0:
break
data += b
if data:
return parse_packet(cobs.decode(data))
else:
return None
def command(self, command, args=b''):
self.write_packet(bytes([command.value]) + args)
return self.read_packet()
class SerializableEnum(Enum):
def __int__(self):
return self.value
class PacketType(SerializableEnum):
USBP_GET_STATUS = 0
USBP_GET_MEASUREMENTS = 1
USBP_SET_MOTOR = 2
class ErrorCode(Enum):
ERR_SUCCESS = 0
ERR_TIMEOUT = 1
ERR_PHYSICAL_LAYER = 2
ERR_FRAMING = 3
ERR_PROTOCOL = 4
ERR_DMA = 5
ERR_BUSY = 6
ERR_BUFFER_OVERFLOW = 7
ERR_RX_OVERRUN = 8
ERR_TX_OVERRUN = 9
class BoardConfig(Enum):
BCFG_UNCONFIGURED = 0
BCFG_DISPLAY = 1
BCFG_MOTOR = 2
BCFG_MEAS = 3
class Serialized:
@classmethod
def deserialize(kls, data):
fields = struct.unpack(kls._struct_format(), data)
mapped = [cast(val) for cast, val in zip(kls._struct_casts(), fields)]
return kls(*mapped)
def serialize(self):
mapped = [uncast(val) for uncast, val in zip(self._struct_uncasts(), astuple(self))]
return struct.pack(self._struct_format(), *mapped)
@classmethod
@cache
def _struct_format(kls):
return kls._parse_fields()[0]
@classmethod
@cache
def _struct_casts(kls):
return kls._parse_fields()[1]
@classmethod
@cache
def _struct_uncasts(kls):
return kls._parse_fields()[2]
@classmethod
def _parse_fields(kls):
fmt = '<'
casts = []
uncasts = []
for field in fields(kls):
if isinstance(field.type, tuple):
struct_type, cast, uncast, *_ = *field.type, int
else:
struct_type, cast, uncast = field.type, int, int
fmt += struct_type
casts.append(cast)
uncasts.append(uncast)
return fmt, casts, uncasts
def timestamp(value):
return float(value) / 1e6
@dataclass
class StatusPacket(Serialized):
packet_type: ('B', PacketType)
sys_time_us: ('Q', timestamp)
has_lcd: ('B', bool)
has_adc: ('B', bool)
board_config: ('B', BoardConfig)
bus_addr: 'B'
last_uart_error: ('B', ErrorCode)
last_uart_error_timestamp: ('Q', timestamp)
last_uart_rx: ('Q', timestamp)
last_uart_tx: ('Q', timestamp)
last_bus_error: ('B', ErrorCode)
last_bus_error_timestamp: ('Q', timestamp)
@dataclass
class MotorPacket(Serialized):
packet_type: ('B', PacketType)
speed_rpm: 'i'
def parse_packet(data):
packet_type = PacketType(data[0])
if packet_type == PacketType.USBP_GET_STATUS:
return StatusPacket.deserialize(data)
if packet_type == PacketType.USBP_GET_MEASUREMENTS:
return MeasurementPacket.deserialize(data)
else:
raise ValueError(f'Unsupported packet type {packet_type}')
@dataclass
class MeasurementPacket(Serialized):
packet_type: ('B', PacketType)
num_channels: 'B'
_num_samples_a: 'I'
_num_samples_b: 'I'
_measurements_raw: ('240s', bytes)
@property
def measurements(self):
return np.frombuffer(self._measurements_raw, np.dtype(np.int32).newbyteorder('<')).reshape([2, 2, -1])
@property
def num_samples(self):
return [self._num_samples_a, self._num_samples_b]
@click.group()
def cli():
pass
@cli.command()
@click.argument('port')
@click.option('--timeout', type=float, default=1)
def probe(port, timeout):
ser = CobsSerial(port, timeout)
pprint(ser.command(PacketType.USBP_GET_STATUS))
while True:
time.sleep(0.01)
packet = ser.command(PacketType.USBP_GET_MEASUREMENTS)
for i in range(packet.num_samples[1]):
print(packet.measurements[1,1,i], packet.num_samples[1])
@cli.command()
@click.argument('port')
@click.argument('speed_rpm', type=int, default=0)
@click.option('--timeout', type=float, default=1)
def motor(port, speed_rpm, timeout):
ser = CobsSerial(port, timeout)
packet = MotorPacket(PacketType.USBP_SET_MOTOR, speed_rpm)
ser.write_packet(packet.serialize())
if __name__ == '__main__':
cli()

171754
sfp-debug-breakout/fp-info-cache
View file

File diff suppressed because it is too large Load diff

2
sfp-debug-breakout/sfp-debug-breakout.kicad_prl
View file

@ -3,10 +3,12 @@
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,

26
sfp-debug-breakout/sfp-debug-breakout.kicad_pro
View file

@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
@ -62,6 +63,7 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
@ -70,6 +72,7 @@
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
@ -113,6 +116,7 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
@ -133,9 +137,6 @@
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
@ -144,29 +145,35 @@
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
@ -423,7 +430,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -437,21 +444,26 @@
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""