Transmission works including sync and whitening

This commit is contained in:
jaseg 2023-10-02 14:50:03 +02:00
parent 72cffd586a
commit 8e42ca0978
5 changed files with 41 additions and 8 deletions

View file

@ -28,3 +28,8 @@ define jdump
continue
end
end
define reconnect
disconnect
target extended-remote 192.168.1.97:2022
end

View file

@ -1569,6 +1569,27 @@
"1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0110001011 1000111010 0001011110 1000011001 0111001011 0010010111\n",
"1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 1100101001 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0101001110 0110001011 1000111010 0001011110 1000011001 0111001011 1100000110"
]
},
{
"cell_type": "code",
"execution_count": 221,
"id": "bfd80ba5-b943-4eaa-894c-f87c30ab7735",
"metadata": {},
"outputs": [
{
"name": "stdout",
"output_type": "stream",
"text": [
"\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;2m11\u001b[38;5;3m00 0\u001b[38;5;2m11\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;2m11\u001b[38;5;1m0\u001b[38;5;3m1 11\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;2m00 \u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;2m11\u001b[38;5;1m0\u001b[38;5;2m11\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0 \u001b[38;5;1m1\u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;3m000\u001b[38;5;4m1111 \u001b[38;5;1m0\u001b[38;5;1m1\u001b[38;5;1m0"
]
}
],
"source": [
"bits = np.fromfile('/tmp/dump_bit.bin', dtype=np.uint8)\n",
"pos, = np.fromfile('/tmp/dump_bit_idx.bin', dtype=np.uint32)\n",
"bits = bits[:pos]\n",
"print_rl(*bits, break_groups={'00000', '11111'}, split_each=10, split_offset=0)"
]
}
],
"metadata": {

View file

@ -155,11 +155,15 @@ int main(void) {
if (packet_received) {
if (rng_reset) {
packet_rng_state = xorshift32(1);
rng_reset = false;
GPIOB->BSRR = (1<<7);
} else {
GPIOB->BRR = (1<<7);
}
for(size_t i=0; i<sizeof(rx_buf.packet); i++) {
packet_rng_state = xorshift32(packet_rng_state);
// rx_buf.bytes[i] ^= packet_rng_state; FIXME DEBUG
rx_buf.bytes[i] ^= packet_rng_state;
}
uint32_t crc_state = crc32_reset();
@ -169,6 +173,7 @@ int main(void) {
crc_state = crc32_finalize(crc_state);
if (crc_state == rx_buf.packet.crc) {
GPIOA->BSRR = (1<<6);
/* good packet received */
int val = rx_buf.packet.brightness[CONFIG_MODULE_ADDRESS/2];
if (CONFIG_MODULE_ADDRESS & 1) {
@ -178,6 +183,7 @@ int main(void) {
channel_mask = rx_buf.packet.channels[CONFIG_MODULE_ADDRESS];
} else {
GPIOA->BRR = (1<<6);
errors.crc_errors++;
}
@ -203,7 +209,6 @@ void gdb_dump(void) {
void ADC1_IRQHandler(void) {
static int phase = 0;
static int last_bit = 0;
GPIOB->BSRR = (1<<7);
/* Read sample and apply threshold */
int sample = ADC1->DR; /* resets the EOC interrupt flag */
@ -300,11 +305,9 @@ void ADC1_IRQHandler(void) {
if (phase == SAMPLES_PER_BAUD - LED_DEAD_TIME || bit != last_bit || bit_margin < MIN_RECTIFIER_MARGIN) { /* reset */
GPIOA->BRR = (1<<11); /* RECT1 */
GPIOC->BRR = (1<<15); /* RECT2 */
GPIOA->BRR = (1<<6);
} else if (phase == LED_DEAD_TIME) { /* set */
if (bit) {
GPIOA->BSRR = (1<<6);
#ifndef DEBUG_DISABLE_DRIVERS
GPIOC->BSRR = (1<<15); /* RECT2 */
#endif
@ -329,7 +332,6 @@ void ADC1_IRQHandler(void) {
}
last_bit = bit;
GPIOB->BRR = (1<<7);
}
void TIM14_IRQHandler(void) {

View file

@ -8,7 +8,7 @@ set print elements 512
# Convert GDB to interpret in Python
python
import os,subprocess,sys
import os, subprocess, sys
# Execute a Python using the user's shell and pull out the sys.path (for site-packages)
paths = subprocess.check_output('python -c "import os,sys;print(os.linesep.join(sys.path).strip())"',shell=True).decode("utf-8").split()
# Extend GDB's Python's search path
@ -18,3 +18,8 @@ end
source ~/ref/PyCortexMDebug/cmdebug/svd_gdb.py
svd_load ~/ref/stm32square/svd/STM32G070.svd
define reconnect
disconnect
target extended-remote 192.168.1.95:2022
end

View file

@ -15,7 +15,7 @@ static void set_status_leds(uint32_t leds);
static void dma_tx_constant(size_t table_size, uint16_t constant);
static void dma_tx_waveform(size_t table_size, const uint16_t *table);
#define SYNC_INTERVAL 2
#define SYNC_INTERVAL 13
static size_t time_to_sync = 0;
static size_t tx_bitpos = 0;
@ -282,7 +282,7 @@ void DMA1_Channel1_IRQHandler() {
} else {
uint8_t b = tx_buf_read->bytes[tx_sympos];
packet_rng_state = xorshift32(packet_rng_state);
//b ^= packet_rng_state; FIXME DEBUG
b ^= packet_rng_state;
current_symbol = xfr_8b10b_encode(&encoder_state_8b10b, b);
sym_arr[sym_pos] = current_symbol;
tx_sympos ++;