tachibana/test_bench/term_renderer_tb.v

107 lines
No EOL
2.1 KiB
Verilog

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/15/2021 10:49:32 AM
// Design Name:
// Module Name: window_matcher_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module term_renderer_tb();
parameter GLYPHMEM_W = 256; /* glyphs */
parameter GLYPHMEM_H = 128; /* glyphs */
localparam period = 4;
localparam REC_MAXLEN = 200000;
reg rst, clk;
reg vsync, hsync;
reg [19:0] glyphmem_data;
wire [15:0] glyphmem_r_addr;
wire [7:0] out_red;
wire [7:0] out_green;
wire [7:0] out_blue;
initial begin
rst = 1;
clk = 0;
repeat(2) #period clk = ~clk;
rst = 0;
forever #period clk = ~clk;
end
reg [23:0] data_recording [0:REC_MAXLEN];
integer testcase_id;
integer rec_pos;
initial begin
`include "test_data/00TERM_RENDERER_TC_IDX.v"
$finish();
end
always @(posedge clk) begin
if (rst) begin
rec_pos <= 0;
for (integer i=0; i<REC_MAXLEN; i=i+1) begin
data_recording[i] <= 0;
end
end else begin
if (rec_pos != REC_MAXLEN-1) begin
data_recording[rec_pos] = {out_red, out_green, out_blue};
rec_pos = rec_pos + 1;
end else begin
$finish();
end
end
end
reg [19:0] glyphmem [0:GLYPHMEM_W*GLYPHMEM_H-1];
initial $readmemh("../../../../test_bench/test_data/test_glyphmem_data.hex", glyphmem);
always @(posedge clk) begin
if (rst) begin
glyphmem_data <= 0;
end else begin
if (glyphmem_r_addr < GLYPHMEM_W*GLYPHMEM_H) begin
glyphmem_data <= glyphmem[glyphmem_r_addr];
end else begin
glyphmem_data <= 0;
end
end
end
term_renderer #(
.GLYPHMEM_W(GLYPHMEM_W),
.GLYPHMEM_H(GLYPHMEM_H)
) term_renderer_dut (
.rst(rst),
.clk(clk),
.in_vsync(vsync),
.in_hsync(hsync),
.glyphmem_data(glyphmem_data),
.glyphmem_r_addr(glyphmem_r_addr),
.out_red(out_red),
.out_green(out_green),
.out_blue(out_blue)
);
endmodule