102 lines
1.9 KiB
Verilog
102 lines
1.9 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 06/15/2021 10:49:32 AM
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// Design Name:
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// Module Name: window_matcher_tb
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module window_matcher_tb();
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reg clk;
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reg rst;
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reg in_blank;
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reg in_hsync;
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reg in_vsync;
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reg [7:0] in_red;
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reg [7:0] in_green;
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reg [7:0] in_blue;
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wire win_blank;
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wire win_hsync;
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wire win_locked;
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wire [11:0] win_w;
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wire [11:0] win_h;
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wire out_data_en;
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wire out_data_valid;
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localparam period = 4;
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initial begin
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clk = 0;
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rst = 1;
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in_blank = 1;
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in_hsync = 0;
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in_vsync = 0;
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in_red = 0;
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in_green = 0;
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in_blue = 0;
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repeat(2) #period clk = ~clk;
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rst = 0;
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forever #period clk = ~clk;
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end
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`include "test_data/00WM_TEST_POS_LOADERS.v"
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integer read_pos;
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reg [23:0] expected_data;
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reg [23:0] expected_data_last;
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integer testcase_id;
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reg win_blank_exp, win_header;
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reg win_blank_exp_last, win_header_last;
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reg in_vsync_last;
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initial begin
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`include "test_data/00WM_TEST_POS_RUNNERS.v"
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$finish;
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end
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window_matcher window_matcher_i (
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.clk(clk),
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.rst(rst),
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.bypass(1'b0),
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.in_blank(in_blank),
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.in_hsync(in_hsync),
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.in_vsync(in_vsync),
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.in_red(in_red),
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.in_green(in_green),
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.in_blue(in_blue),
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.win_blank(win_blank),
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.win_locked(win_locked),
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.win_w(win_w),
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.win_h(win_h),
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.out_data_en(out_data_en),
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.out_data_valid(out_data_valid),
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.win_red(8'haa),
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.win_green(8'haa),
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.win_blue(8'haa)
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);
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endmodule
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