77 lines
No EOL
1.5 KiB
Verilog
77 lines
No EOL
1.5 KiB
Verilog
`timescale 1ns / 1ps
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module term_emu_tb();
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parameter GLYPHMEM_W = 256; /* glyphs */
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parameter GLYPHMEM_H = 128; /* glyphs */
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localparam period = 4;
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reg clk, rst;
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reg in_byte_valid;
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reg [7:0] in_byte;
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wire in_byte_ack;
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wire glyph_buffer_w_valid;
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wire [15:0] glyph_buffer_w_addr;
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wire [19:0] glyph_buffer_w_data;
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reg [19:0] glyph_buffer;
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initial begin
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rst = 1;
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clk = 0;
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repeat(2) #period clk = ~clk;
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rst = 0;
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forever #period clk = ~clk;
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end
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`include "test_data/00TEMU_TEST_STR_LOADERS.v"
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integer testcase_id;
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integer read_pos;
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initial begin
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`include "test_data/00TEMU_TEST_STR_RUNNERS.v"
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$finish;
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end
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reg [19:0] glyphmem [0:GLYPHMEM_W*GLYPHMEM_H-1];
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reg last_rst;
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always @(posedge clk) begin
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last_rst <= rst;
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if (~last_rst && rst) begin
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for (integer i=0; i<GLYPHMEM_W*GLYPHMEM_H; i=i+1) begin
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glyphmem[i] = 20'h00000;
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end
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end else begin
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if (glyph_buffer_w_valid) begin
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if (glyph_buffer_w_addr < GLYPHMEM_W*GLYPHMEM_H) begin
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glyphmem[glyph_buffer_w_addr] <= glyph_buffer_w_data;
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end else begin
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$display("Glyph memory write access out of bounds");
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$finish();
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end
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end
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end
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end
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term_emu #(
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.GLYPHMEM_W(GLYPHMEM_W),
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.GLYPHMEM_H(GLYPHMEM_H)
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) term_emu_dut (
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.clk(clk), .rst(rst),
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.in_byte_valid(in_byte_valid),
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.in_byte(in_byte),
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.in_byte_ack(in_byte_ack),
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.glyph_buffer_w_valid(glyph_buffer_w_valid),
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.glyph_buffer_w_addr(glyph_buffer_w_addr),
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.glyph_buffer_w_data(glyph_buffer_w_data)
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);
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endmodule |