128 lines
No EOL
2.6 KiB
Verilog
128 lines
No EOL
2.6 KiB
Verilog
`timescale 1ns / 1ps
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module spi_regfile_tb();
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localparam period = 10;
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parameter WORDSIZE = 8;
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reg clk, rst;
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reg sck, sdi, ncs;
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wire sdo;
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reg [15:0] spi_data_in;
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wire [15:0] spi_data_out;
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wire [15:0] spi_status_word = 16'h3141;
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wire [15:0] spi_cmd_word;
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wire spi_cmd_begin, spi_cmd_active, spi_cmd_step;
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wire [19:0] spi_cmd_idx;
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initial begin
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clk = 0;
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/* rst set below */
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sck = 0;
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sdi = 0;
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ncs = 1;
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forever #period clk = ~clk;
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end
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integer i;
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integer j;
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integer k;
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integer testcase;
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reg [WORDSIZE-1:0] sim_rxdata [1:4];
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reg [WORDSIZE-1:0] sim_txdata [1:4];
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reg [WORDSIZE-1:0] sim_txbuf;
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initial begin
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sim_rxdata[1] = 16'h523a;
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sim_rxdata[2] = 16'hbeef;
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sim_rxdata[3] = 16'h7721;
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sim_rxdata[4] = 16'h0108;
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sim_txdata[1] = 16'h1234;
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sim_txdata[2] = 16'h5678;
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sim_txdata[3] = 16'h9abc;
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sim_txdata[4] = 16'hdef9;
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for (j=1; j<=4; j=j+1) begin
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$display("TC-%d: rx/tx %d word", j, j);
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testcase = j;
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rst = 1;
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repeat(2) @(posedge clk);
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rst = 0;
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@(posedge clk);
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spi_data_in = sim_txdata[1];
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@(posedge clk);
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ncs = 0;
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@(posedge clk);
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if (spi_cmd_begin) $finish;
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if (spi_cmd_active) $finish;
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if (spi_cmd_step) $finish;
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for (k=1; k<=j; k=k+1) begin
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sim_txbuf = 0;
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for (i=1; i<=WORDSIZE; i=i+1) begin
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sdi = sim_rxdata[k][WORDSIZE-i];
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sck = 0;
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@(posedge clk);
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sck = 1;
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sim_txbuf[WORDSIZE-i] = sdo;
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if (i == WORDSIZE) begin
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spi_data_in = sim_txdata[k+1];
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end
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if (spi_cmd_step) $finish;
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@(posedge clk);
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end
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if (!spi_cmd_active) $finish;
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if (k == 1 && !spi_cmd_begin) $finish;
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if (k > 1 && spi_cmd_begin) $finish;
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if (k == 1 && spi_cmd_step) $finish;
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if (k > 1 && !spi_cmd_step) $finish;
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if (spi_cmd_word != sim_rxdata[1]) $finish;
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if (k > 1 && spi_data_out != sim_rxdata[k]) $finish;
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if (k == 1 && sim_txbuf != 16'h3141) $finish;
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if (k > 1 && sim_txbuf != sim_txdata[k]) $finish;
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if (spi_cmd_idx != k-1) $finish;
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end
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sck = 0;
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@(posedge clk);
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ncs = 1;
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@(posedge clk);
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if (spi_cmd_active) $finish;
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if (spi_cmd_step) $finish;
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if (spi_cmd_begin) $finish;
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repeat(10) @(posedge clk);
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end
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$finish;
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end
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spi_regfile spi_regfile_dut (
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.clk(clk), .rst(rst),
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.sck(sck), .sdi(sdi), .sdo(sdo), .ncs(ncs),
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.spi_data_in(spi_data_in),
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.spi_data_out(spi_data_out),
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.spi_status_word(spi_status_word),
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.spi_cmd_word(spi_cmd_word),
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.spi_cmd_begin(spi_cmd_begin),
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.spi_cmd_active(spi_cmd_active),
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.spi_cmd_step(spi_cmd_step),
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.spi_cmd_idx(spi_cmd_idx)
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);
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endmodule |