Merge pull request #1 from mithro/master

s/alingment/alignment/

Artix-7-HDMI-processing.xpr

@@ -31,7 +31,7 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/src/alingment_detect.vhd">
+      <File Path="$PPRDIR/src/alignment_detect.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>

src/alignment_detect.vhd

@@ -1,7 +1,7 @@
 ----------------------------------------------------------------------------------
 -- Engineer: Mike Field <hamster@snap.net.nz< 
 -- 
--- Module Name: alingment_detect - Behavioral
+-- Module Name: alignment_detect - Behavioral
 --
 -- Description: Manage the dealy and bitslipping of the SERDES based on invald 
 --              symbols being received.  
@@ -49,16 +49,16 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
-entity alingment_detect is
+entity alignment_detect is
     Port ( clk            : in  STD_LOGIC;
            invalid_symbol : in  STD_LOGIC;
            delay_count    : out std_logic_vector(4 downto 0);
            delay_ce       : out STD_LOGIC;
            bitslip        : out STD_LOGIC;
            symbol_sync    : out STD_LOGIC);
-end alingment_detect;
+end alignment_detect;
 
-architecture Behavioral of alingment_detect is
+architecture Behavioral of alignment_detect is
     --------------------------------------
     -- Signals for controlling the bitslip 
     -- and delay so we can sync symbols

src/hdmi_input.vhd

@@ -120,7 +120,7 @@ architecture Behavioral of hdmi_input is
     
     signal clk_pixel_raw     : std_logic;
     
-    component alingment_detect is
+    component alignment_detect is
         Port ( clk            : in STD_LOGIC;
                invalid_symbol : in STD_LOGIC;
                delay_count    : out STD_LOGIC_VECTOR(4 downto 0);

src/input_channel.vhd

@@ -98,7 +98,7 @@ architecture Behavioral of input_channel is
            data            : out std_logic_vector (7 downto 0));
     end component;
     
-    component alingment_detect is
+    component alignment_detect is
         Port ( clk            : in STD_LOGIC;
                invalid_symbol : in STD_LOGIC;
                delay_count    : out STD_LOGIC_VECTOR(4 downto 0);
@@ -146,7 +146,7 @@ i_decoder: tmds_decoder port map (
     
     invalid_symbol <= invalid_symbol_i;
      
-i_alignment_detect: alingment_detect port map (
+i_alignment_detect: alignment_detect port map (
            clk            => clk,
            invalid_symbol => invalid_symbol_i,
            delay_count    => delay_count,