jaseg/tachibana
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Fix typos I added when I added headers

Browse source
This commit is contained in:
Mike Field 2015-08-04 22:38:52 +12:00
parent 89ee75121b
commit 91f3aea0c4
3 changed files with 1 additions and 32 deletions
Download patch file Download diff file Expand all files Collapse all files

3
Artix-7-HDMI-processing.cache/wt/java_command_handlers.wdf
View file

@ -1,3 +0,0 @@
version:1
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:2d31:00:00
eof:625436222

29
Artix-7-HDMI-processing.cache/wt/webtalk_pa.xml
View file

@ -1,29 +0,0 @@
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Aug 04 21:42:27 2015">
<section name="Project Information" visible="false">
<property name="ProjectID" value="1b5c2076c55343a1a76449823623e509" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="NewProject" value="-1" type="JavaHandler"/>
</item>
<item name="Other">
<property name="GuiMode" value="103" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="76" type="TclMode"/>
</item>
</section>
</application>
</document>

1
src/edid_rom.vhd
View file

@ -43,6 +43,7 @@
-- Commercial use - A weeks pay for an engineer (I wish!)
--
----------------------------------------------------------------------------------library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;